simulation and synthesis of fir filter design using...

© 2014, IJARCSSE All Rights Reserved Page | 1011

Volume 4, Issue 3, March 2014 ISSN: 2277 128X

International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com

Simulation and Synthesis of Fir Filter Design Using VHDL Vishwajit K. Barbudhe

Department of Electronics & Telecommunication

Jagdambha C.O.E.T, Yawatmal,

Maharashtra, India

Abstract: In this Module an attempt has been made to develop a simulation model of an FIR filter using VHDL. This

simulation model will incorporate a mixture of both Behavioral as well as Structural modeling constructs that were

briefly described above. The above aim has been furthered by taking a stepwise approach, that is, behavioral as well as

dataflow simulation models of less complex devices such as program counter, memory controller, memory modules

(SRAM & ROM), multiplier, accumulator and stack pointer have been developed and these models would be

integrated together in the FIR filter model. All FIR filters support low pass, high pass, band pass, and band stop

options. The FIR filters Rectangular, Bartlett, Hanning, Hamming, Blackman, Kaiser, and Dolph-Chebyshev are all

Window FIR filters. The name "Window" comes from the fact that these filters are created by scaling a sinc (sin(x)/x)

pattern with a window to produce the desired frequency effect.

Keyword ( FIR filter , program counter , memory controller, memory modules SRAM & ROM , multiplier ,

accumulator and stack pointer )

I. Introduction

The FIR filter performs high speed multiply and accumulate operations. The FIR filter consists of the various

sub modules as shown. The ROM contains the coefficients and the SRAM stores the data entered by the user. The

memory controller is used to control the ROM and SRAM chip selection logic and the read write logic. It also generates

address for the ROM. The stack pointer generates addresses for the SRAM. The data in the SRAM and ROM are

multiplied and accumulated to get the final output. This project aims at simulating and synthesizing the above sub

systems using VHDL.

II. Memory Control Unit

This unit has clocks (fsclk_edge and mclk), reset and window select (wnsel) as inputs and also some other inputs sent by

different units. It is used to generate ROM address from where the next filter coefficients are fetched and it generates

different control signals to perform the other operations such as enabling the memory and accumulator, and to enable the

read and write lines of memory.

Block Diagram

Clock Generator Unit

This unit is used to generate clocks that are used by the different modules (FSCLK_ED, MCLK and RCLK).

This unit supports the memory control unit for fetching the data and filter coefficients synchronously.

Stack pointer

The stack pointer is used to generate address for the data coefficients i.e. for the SRAM.

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Vishwajit et al., International Journal of Advanced Research in Computer Science and Software Engineering 4(3),

March - 2014, pp. 1011-1017


Memory Unit

There are two memory modules-ROM and SRAM memory. The RAM has a read, a write, and a chip selection

signal. The ROM has a read and a chip selection signal. The memory controller sends these signals. In response to the

read signal, coefficients are latched into the respective registers and in response to the write signals, the input data of the

register is loaded onto the output lines of the memory.

Multiplier

Both the memory modules hold 16 bit data. The multiplier acts on this data and multiplies the contents from the

RAM and ROM. The multiplier operations performed is not the shift and add operation as this makes the process slow.

Here in multiplier the data is directly multiplied in single cycle with the help of the multiplier operator.

Accumulator

This unit gets the multiplied output at its input pins. This unit has two inputs viz. accumulator enable

(ACCENB) and accumulator latch (ACCLAT) and one output accumulator out (ACC_OUT). ACCENB is used to enable

the accumulator and ACCLAT is used when all the accumulation process cycle is over. It latches the accumulated data

and provide it to the output pins.

FIR Filter Design

The design of FIR filters involves the selection of a finite sequence that best represents the impulse response

of an ideal filter. FIR filters are always stable. Even more important, FIR filters are capable of perfectly linear phase (a

pure time delay), meaning total freedom from phase distortion. The three most commonly used methods for FIR filter

design are window-based design using the impulse response of ideal filters, frequency sampling, and iterative design

based on optimal constraints. We are implementing the window-based design technique.

Window-Based Design

The window method starts by selecting the impulse response hN [n] as a symmetrically truncated version of the

impulse response h[n] of an ideal filter with frequency response H(F). The impulse response of an ideal lowpass filter

with a cutoff frequency Fc is h[n] = 2Fcsinc{2nFc). Its symmetric truncation yields

hN[n] =2Fcsinc(2nFc). n 0.5(N-1)

III. Characteristics of Window Functions

The amplitude response of symmetric, finite-duration windows invariably shows a mainlobe and decaying

sidelobes that may be entirely positive or that may alternate in sign. The spectral measures for a typical window are

illustrated in Figure

Fig. Magnitude spectrum of a typical window

The Window Technique

The window technique is best described in terms of a specific example. We want to design a symmetric lowpass linear-

phase FIR filter having a desired frequency response

Hd() = 1e-j(N-1) / 2

, 0 c

= 0 , otherwise

A delay of (N-1) / 2 units is incorporated into Hd() in anticipation of forcing the filter to be of length N. The

corresponding unit sample response hd(n) is non-causal and infinite in duration. If we multiply hd(n) by the rectangular

window sequence,

W(n) = 1, n = 0,1,….,N-1

= 0, otherwise

we obtain an FIR filter of length N having the unit sample response

h(n)

1sin

2

1

2

c

Nn

Nn

,0 n N-1 , n (N-1) / 2


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If M is selected to be odd, the value of h(n) at n = (N-1)/2 is

h[(N-1) / 2] = c /

IV. SIMULATION AND SYNTHESIS RESULTS

Memory Control Unit

The simulation of the memory control unit is shown on the next page. Initially the reset is kept asserted for 10ns

during which the counters get loaded with the initial value. The window selection signal is kept at ‘00’ and this ensures

that the addresses of the first set of coefficients in the ROM are generated. The ROM addresses are generated for the

eight coefficients and after the last one it is reset to the first value. As the window selection signal is changed the

addresses generated by the memory controller change accordingly. The red line shows the point where the system starts

working.

Fig Simulation result of the Memory Controller

Fig Simulation Result of the Memory Controller (contd.)

Clock Generator Unit

The clock generator unit has no input and it generates the clocks required by the design. The different duty cycles can be

seen from the simulated waveforms.


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Fig simulation result of the Clock Generator Unit

SRAM Memory Unit

The locations in the SRAM are loaded with values as shown in the simulation result. After writing the data the data can

be read by enabling the RDN signal and specifying the address.

Fig Simulation Result of the SRAM

ROM Memory Unit

The ROM coefficients are stored in the memory and they are loaded onto the data output lines by specifying the address

location.

Fig Simulation result of the ROM Memory Unit

Multiplier Unit

The Multiplier Unit performs both signed and unsigned multiplication of two 16-bit numbers. In fig 5.6 +5 (5)H is

multiplied with +2 (2)H and we get +10 (A)H as the result.


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Fig Simulation result of the Multiplier Unit

In fig 5 (FFFB)H is multiplied with +2 (2)H and we get -10 (FFFFFFF6)H as the result. This is actually the twos

complement notation of -10.

Fig Simulation result of the Multiplier Unit (contd.)

The Stack Pointer Unit

The Stack Pointer unit generates the SRAM addresses which are stored in its memory.

Fig Simulation result of the Stack pointer


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The FIR-TOP module

The FIR TOP module interconnects the remaining modules. It gets data at the input pins and then final

accumulated data is obtained at the output lines. The simulation results are shown below. Here data input is fed by a

counter incrementing at every 1.25 ns.

Fig Simulation Result of the FIR-TOP

Fig Simulation result of the FIR-TOP (contd.)


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Fig Simulation Result of the FIR-TOP (contd.)

V. Result

Finite Impulse Response (FIR) filters are used in every aspect of present day technology because filtering is one

of the basic tools of information acquisition and manipulation. Digital filters form an integral part in digital signal

processing applications. The FIR filter designed uses a window selection algorithm. The design can be easily modified to

change the filter parameters according to the requirement. The different blocks were simulated in Active HDL and the

waveforms verified the workability of the sub modules. The sub modules were integrated and the whole 8-tap 16-bit FIR

filter was realized. The synthesis results were obtained on Leonardo spectrum for every block and they fit the

technology. Renoir Graphics was used to generate the flow chart within the process declarations.

Future Modifications

Testbenches for all VHDL codes can be developed.The FIR filter can be modified to increase the number of taps

and the number of bits used to represent the coefficients.The Stack Pointer Unit can be removed and replaced by an

optimal address calculator and shifter . The design can be implemented on an FPGA or CPLD. It can be used as a sub

module for a DSP processor.

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