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CFES Annual Symposium April 12, 2019 T.P. Chow
Smart Power Devices and ICs in GaN
T. Paul Chow Rensselaer Polytechnic Institute
Troy, NY 12180 E-mail: [email protected]
1
CFES Annual Symposium April 12, 2019 T.P. Chow
Outline
• Material Properties and Device Potentials • GaN Power Device Structures • HV Device Performance • Power ICs and Optoelectronic Integration • Summary
2
CFES Annual Symposium April 12, 2019 T.P. Chow
Widespread Application of GaN LEDs
Typical GaN LED schematic cross-section
(D. Hwang et al. Appl. Phys. Express, 2017) Backlighting
LED Headlights
Large Displays
LED Plant Growth (Wasabi)
Streetlights
Micro-LED
Display
Visible Light
Communication
(VLC)
CFES Annual Symposium April 12, 2019 T.P. Chow
Power Semiconductor Devices
4
CFES Annual Symposium April 12, 2019 T.P. Chow
Note: a – mobility along a-axis, c-mobility along c-axis, *Estimated value, **2DEG
Semiconductor Properties
• GaN grown on SiC can have a similar thermal conductivity as that of SiC • GaN grown on Si can reduce the wafer cost, have larger wafer size and use Si foundries for processing
5
Material Eg Direct/ ni er mn Ec vsat l
(eV) Indirect (cm-3) (cm2/V-s) (MV/cm) (107 cm/s) (W/cm-K)
Si 1.12 I 1.5x1010 11.8 1350 0.2 1.0 1.5
GaAs 1.42 D 1.8x106 13.1 8500 0.4 1.2 0.55
2H-GaN 3.39 D 1.9x10-10 9.9 1200a
2000** 3.3* 3.75a 2.5 2.5
4.1*
4H-SiC 3.26 I 8.2x10-9 10 720a 650c 2.0a 2.0 4.5
Diamond 5.45 I 1.6x10-27 5.5 3800 10 2.7 22
2H-AlN 6.2 D ~10-34 8.5 300 12* 1.7 2.85
Conventional Semiconductors
Wide Bandgap Semiconductors
Extreme Bandgap Semiconductors
CFES Annual Symposium April 12, 2019 T.P. Chow 6
Applications of Power Devices Modified from an Application Note of Powerex, Inc. Youngwood, PA. •Some devices are
pushing Si boundary
•SiC/GaN and
Diamond/AlN offer
promise for
improvement
GTO
DISCRETE
MOSFET
TRI-MOD
IGBT-MOD
MOSFET
MOD
TRANSISTOR
MODULES
IGBTMODTM
MODULES
100M
10M
1M
100
10
Po
wer
(V
A)
100K
10K
1K
10 100
Operation Frequency (Hz)
1K 10K 100K 1M
CFES Annual Symposium April 12, 2019 T.P. Chow
Vertical and Lateral Power Transistors
Lateral HEMT
Dra
in
So
urc
e
Gate
CFES Annual Symposium April 12, 2019 T.P. Chow
Vertical vs. Lateral Breakdown
0
200
400
600
800
1000
1200
1400
0 10 20 30 40 50 60 70 80
Bre
akd
ow
n V
olt
age
(V
)
Drift length (µm)
Si SOI oxide1.2um
Si SOI oxide1.6um
Si SOI oxide4.4um
Si SOI ideal
GaN epi 1um
GaN epi 2um
GaN epi 3um
GaN Ideal
8
CFES Annual Symposium April 12, 2019 T.P. Chow
Specific On-Resistance vs. Breakdown Voltage
• At 1000 V blocking voltage, projected lateral RESURF GaN specific on-resistance is 2 orders of magnitude lower than the Si lateral RESURF limit
• At above 1000 V blocking voltage, predicted on-resistance is close to the 1D 4H-SiC limit
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+02 1.0E+03 1.0E+04Breakdown Voltage (V)
Sp
ec
ific
On
-re
sis
tan
ce
(oh
m-c
m2)
4H-SiC 1D
2H-GaN 1D
Silicon 1D
Si 2D RESURFSiC 2D RESURF
GaN 2D RESURF
Ron,sp ( BV )1.0-1.2
CFES Annual Symposium April 12, 2019 T.P. Chow
Lateral SiC and/or GaN Power Transistors
10
Source
Gate
Substrate (p+)
RESURF (n)
Silicon
Al0.05GaN
DrainSource
UID GaN
Gate
AlN/GaN Buffer
Silicon
UID Al0.05GaN
SiO2
DrainSource
UID GaN
GateUID Al0.25GaN
ILDUID GaN
AlN/GaN Buffer
HEMT/HFET RESURF MOSFET
MOSHC-HEMT/HFET MOSC-HEMT/HFET
CFES Annual Symposium April 12, 2019 T.P. Chow
GaN Polarization Charges and 2DEG
* O. Ambacher et al., J. Appl. Phys. 85(6), 3222-3233 (1999).
• Net positive fixed charge (Qf) at AlGaN/GaN, due to the difference in spontaneous (PSP) and piezoelectric (PPE) polarization between GaN and AlGaN
• Qf can be controlled by Al mole fraction and thickness of AlGaN
• Qf of around 1013cm-2 is the desirable value for RESURF dose
11
CFES Annual Symposium April 12, 2019 T.P. Chow
GaN 2DEG Mobility
12
Vitanov, SSE, 2010
CFES Annual Symposium April 12, 2019 T.P. Chow
Specific On-Resistance vs. Breakdown Voltage
13
Si IGBT Limit
Revised from N. Ikeda, ISPSD, 2008
RPI
CFES Annual Symposium April 12, 2019 T.P. Chow
Panasonic 600V GaN GIT
14
Current Collapse
No destruction and degradation was not observed up to 800V.
0
2
4
6
8
10
300 400 500 600 700 800
Drain-Source Voltage (V)
On-
resi
stan
ce (a
.u.)
Measured under the condition of practical use
Dyn
amic
on-
stat
e re
sist
ance
(a.u
.)
D
SG
FOM(Figure of Merit) RonA, RonQg
10 2 10 3 10 410-1
10 0
10 1
10 2
Breakdown voltage [V]
Spec
ific
On-
Res
ista
nce
Ron
A [
mcm
2 ]
10 5
10 3
10 4
Si Limit
Si Super Junction
MOSFET
Si IGBT
GaN Limit
Panasonic’s GaN-GIT
SiC Limit
10 2 10 3 10 410-1
10 0
10 1
10 2
Breakdown voltage [V]
Spec
ific
On-
Res
ista
nce
Ron
A [
mcm
2 ]
10 5
10 3
10 4
Si Limit
Si Super Junction
MOSFET
Si IGBT
GaN Limit
Panasonic’s GaN-GIT
SiC Limit
RonA and Breakdown Voltage State of art RonQg
Latest MOSFET
Panasonic GaN Transistor
Ron
Qg
Qg: Gate charge
4.03 nC
0.57 nC
1/7
D
SGFOM(Figure of Merit) RonA, RonQg
10 2 10 3 10 410-1
10 0
10 1
10 2
Breakdown voltage [V]
Spe
cific
On-
Res
ista
nce
Ron
A [
mcm
2 ]
10 5
10 3
10 4
Si Limit
Si Super Junction
MOSFET
Si IGBT
GaN Limit
Panasonic’s GaN-GIT
SiC Limit
10 2 10 3 10 410-1
10 0
10 1
10 2
Breakdown voltage [V]
Spe
cific
On-
Res
ista
nce
Ron
A [
mcm
2 ]
10 5
10 3
10 4
Si Limit
Si Super Junction
MOSFET
Si IGBT
GaN Limit
Panasonic’s GaN-GIT
SiC Limit
RonA and Breakdown Voltage State of art RonQg
Latest MOSFET
Panasonic GaN Transistor
Ron
Qg
Qg: Gate charge
4.03 nC
0.57 nC
1/7
D
SG
APEC, 2014
CFES Annual Symposium April 12, 2019 T.P. Chow
Cascode Switch
• Normally-off switch made with HV normally-on GaN HEMT
• Packaging cost and parasitics (inductances, thermal) make current up-scaling difficult
15
CFES Annual Symposium April 12, 2019 T.P. Chow
High Voltage Stressing (HTRB)
CFES Annual Symposium April 12, 2019 T.P. Chow
Bi-Directional 600V GaN GIT
17
*Morita et al, IEDM 2007
CFES Annual Symposium April 12, 2019 T.P. Chow
Specific On-Resistance vs. Breakdown Voltage
• At 1000 V blocking voltage, ideal 1D GaN and AlN devices has more than three and four orders of magnitude lower specific on-resistance than silicon devices respectively
Ron,sp ( BV )2.4-2.6
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+02 1.0E+03 1.0E+04Breakdown Voltage (V)
Sp
ec
ific
On
-re
sis
tan
ce
(oh
m-c
m2)
4H-SiC 1D
2H-GaN 1D
Silicon 1D
18
AlN 1D
CFES Annual Symposium April 12, 2019 T.P. Chow
GaN Vertical Power UMOSFETs Benchmarking of reported GaN vertical power FETs • Ron,sp vs. BV of GaN vertical
power FETs are benchmarked
• Most vertical GaN devices exceed silicon limit and approach SiC limit
• However, fully-vertical devices are not integrable
• Very few reports on quasi-vertical structure; two reported
quasi-vertical UMOSFETs are
as follows:
• BV of 645 V; however, the gate trench area was used to calculate Ron,sp of 6.8 mΩ-cm2, which is incorrect
Liu et al (EPFL), IEEE Electron Device Lett. 2017
• No n- drift layer and hence not power FETs • No BV and Ron,sp reported; m-plane better than a-plane
Gupta et al (UCSB), Appl. Phys. Express 2016
Stripe-cell GaN quasi-vertical power UMOSFETs Hexagonal-cell GaN quasi-vertical UMOSFETs
CFES Annual Symposium April 12, 2019 T.P. Chow
Vertical Superjunction MOSFET
0.00 1.00 2.00Distance (Microns)
0.0
2.5
5.0
7.5
10.0
Dist
anc
e (M
icro
ns)
0.00 1.00 2.00
0.0
2.5
5.0
7.5
10.0
0.00 1.00 2.00
0.0
2.5
5.0
7.5
10.0
0.0
2.5
5.0
7.5
10.0
0 010 1050 50
100
500
100
500
CFES Annual Symposium April 12, 2019 T.P. Chow
• Pillar dosage of GaN SJ structure optimized using simple diode structure. Doping unbalance effects was also examined.
• Keeping the optimized pillar dosage, pillar width and height were varied to obtain Ron,sp-BV trade-off design curves
GaN SJ diode structure BV and Ron,sp vs doping
Ron,sp vs BV for different doping Ron,sp vs BV for different pillar width and height
0
2000
4000
6000
8000
10000
12000
14000
0.0E+00
1.0E-02
2.0E-02
3.0E-02
4.0E-02
5.0E-02
6.0E-02
7.0E-02
8.0E-02
9.0E-02
1.0E-01
0.0E+00 5.0E+15 1.0E+16 1.5E+16 2.0E+16
Bre
akd
ow
n V
olt
age
(V
)
N-t
ype
GaN
Pill
ar R
on
,sp
(oh
m-c
m2)
Doping Concentration (cm-3)
Ron,sp
BV
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+03 1.0E+04
Spe
cifi
c O
n-r
esi
stan
ce
(oh
m-c
m2)
Breakdown Voltage (V)
SiC 1D limit
GaN 1D limit
0
2000
4000
6000
8000
10000
12000
8.20
8.22
8.24
8.26
8.28
8.30
8.32
6 7 8 9 10 11 12 13 14B
reak
do
wn
Vo
ltag
e (
V)
N-t
ype
GaN
Pill
ar R
on
,sp
(mo
hm
-cm
2)
P GaN Doping Concentration (x 1015 cm-3)
Series2
BV
Ron,sp and BV of unbalanced SJ doping
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+03 1.0E+04 1.0E+05
Spe
cifi
c O
n-r
esi
stan
ce
(oh
m-c
m2)
Breakdown Voltage (V)
SJ only, pillar 8um
SJ only, pillar 5um
SJ only, pillar 3um
SJ only, pillar 1um
SiC 1D limit
GaN 1D limit
Design of GaN Superjunction FET
Z. Li, and T. P. Chow, IWN 2012
CFES Annual Symposium April 12, 2019 T.P. Chow
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+03 1.0E+04 1.0E+05
Spe
cifi
c O
n-r
esi
stan
ce
(oh
m-c
m2)
Breakdown Voltage (V)
SJ diode, pillar 8um
SJ diode, pillar 5um
SJ diode, pillar 3um
SJ diode, pillar 1um
SJ HEMT, pillar 8um
SJ HEMT, pillar 5um
SJ HEMT, pillar 3um
SiC Thyristors
SiC 1D limit
GaN 1D limit• Designed
enhancement mode GaN vertical SJ HEMT with the optimized SJ structure using simulations:
• VTH of +1.3V • Ron,sp, for
example, of 4.2 mΩ-cm2 for BV of 12.4kV
• Design curve has
been obtained for different Ron,sp-BV trade-offs
Drain
P GaN
N+ GaN
N GaN
Source
GateP+ GaN
Source
N AlGaN
P+ GaN
GaN SJ vertical HEMT
-20
0
20
40
60
80
100
120
140
0 5 10 15 20 25 30
ID(m
A/m
m)
VD (V)
*Z. Li, and T. P. Chow, IWN 2012
Simulated output ID-VD
Simulated Ron,sp vs BV design curve
0
2000
4000
6000
8000
10000
12000
13.55
13.60
13.65
13.70
13.75
13.80
13.85
13.90
13.95
6 7 8 9 10 11 12 13 14
Bre
akd
ow
n V
olt
age
(V
)
Ro
n,s
p(m
Ω-c
m2)
P GaN Doping Concentration (x 1015 cm-3)
Ron,sp
BV
Ron,sp and BV of unbalanced SJ doping
Design of GaN Superjunction FET
CFES Annual Symposium April 12, 2019 T.P. Chow
GaN Superjunction Devices
23
Amano, 2017
CFES Annual Symposium April 12, 2019 T.P. Chow
Performance of SiC and GaN SJ Devices
24
D. Disney, ISPSD, 2008
H. Ishida, EDL, 2008
• JFET effect limit the performance of conventional vertical superjunction device
• Natural polarization superjunction device uses intrinsic charge balance, no JFET region
CFES Annual Symposium April 12, 2019 T.P. Chow
Performance of SiC and GaN SJ Devices
25
• Keep dosage QSJ constant, shrinks pillar to increase doping concentration, also improve Ron,sp
• But more drift region consumed by depletion region when pillar width too small
Conventional Superjunction MOSFET
N+ substrate Drain
P
Source Gate
P-body
N+
N P N P N P N
CFES Annual Symposium April 12, 2019 T.P. Chow
Performance of SiC and GaN SJ Devices
26
• Keep dosage constant fixed charge at interfaces, shrinks pillar to reduce specific on-resistance
Natural Polarization Superjunction
MOSFET
CFES Annual Symposium April 12, 2019 T.P. Chow
Performance of SiC and GaN SJ Devices
27
• Numerical simulations verify the analytical model of optimum specific on-resistance
CFES Annual Symposium April 12, 2019 T.P. Chow
Performance of SiC and GaN SJ Devices
28
• 1D electric field profile along different symmetric lines in superjunction device
• BV usually happens along line #1 or #3 since electric field direction all vertical
• Electric field magnitude along line#2 is highest, but mostly horizontal
CFES Annual Symposium April 12, 2019 T.P. Chow
Performance of SiC and GaN SJ Devices
29
CFES Annual Symposium April 12, 2019 T.P. Chow
Performance of SiC and GaN SJ Devices
30
A. Nakajima, APL, 2006
• Natural polarization superjunction device, established by inherent spontaneous and piezoelectric polarization
• Use 2D Electron Gas (2DEG) and 2D Hole Gas (2DHG) for conducting current under forward bias
• Under reverse bias, intrinsic charge balance help drift region be depleted
• Nearly strain-free structures can be achieved by lattice-matching (LM) of AlInN/GaN heterostructures with the Indium mole fraction x = 0.18
CFES Annual Symposium April 12, 2019 T.P. Chow
Performance of SiC and GaN SJ Devices
31
• For 1 and 10kV devices, Ron,sp is about 3X and 100X lower for conventional 4H-SiC superjunction devices
• Ron,sp of vertical 2H-GaN SJ devices can reach 0.03 mΩ·cm2 and 1 mΩ·cm2 for breakdown of 1kV and 50kV
• For natural superjunction devices, Ron,sp reachs 0.06 to 3 mΩ·cm2 level for the BV range of 1kV to 50kV
CFES Annual Symposium April 12, 2019 T.P. Chow
GaN Power ICs
32
Panasonic, ISSCC, 2014
700V, 93% efficient for 100W motor
Panasonic, IEDM, 2009
CFES Annual Symposium April 12, 2019 T.P. Chow
Monolithic Integration
33
Monolithic Integration Transistor
Objective: • Develop a process to enable monolithic integration of LEDs, control logic and power transistors. This IC will have the full spectrum of smart lighting features for a wider variety of applications due to reduced package size and cost and improved reliability.
SL-ERC Project S1.3.1: • Start date: July, 2010 • Duration: Through June, 2018
CFES Annual Symposium April 12, 2019 T.P. Chow
Optoelectronic Integration
34
SER: Grow wafers with necessary EPI layers, use subtractive etching to make components
Sapphire/Silicon
GaN
N-GaN
InGaN-GaN QW Layers
P-GaN
Buffer Al0.05GaN
Al0.21GaN GaN
P-GaN
Starting EPI MOS-HEMT Etch
CMOS Etch
N-FET P-FET
LED Etch
Advantages Risks High temperature steps of layer growth complete before processing
Thermal budget of processing may be incompatible
Highly non-planar, lithography obstacle Larger thermal path for cooling LEDs Need selective or high controlled etch to hit depth
CFES Annual Symposium April 12, 2019 T.P. Chow
GaN Optoelectronic Integration • Literature review of GaN FET/LED monolithic integration
– Normally-on and normally-off HEMTs;
– Lateral and vertical MOSFETs; nanowire FETs
CFES Annual Symposium April 12, 2019 T.P. Chow
Integrated GaN Optoelectronics (Gen I)
36
• Successful demonstration of GaN LED driven by monolithically integrated GaN MOS-channel HEMT with selective epi removal
LED GaN MOSC-HEMT
Cathode
Anode
Drain Source
Gate
LED Epi
HEMT Epi
GND
Supply Voltage
Gate
LED
HEMTRPI, 2013
CFES Annual Symposium April 12, 2019 T.P. Chow
*
Integrated GaN Optoelectronics (Gen I)
LED GaN MOSC-HEMT
Cathode
Anode
Drain Source
Gate
LED Epi
HEMT Epi
RPI, 2013
CFES Annual Symposium April 12, 2019 T.P. Chow
RPI: GaN MOSC-HEMT/LED Integration
38
CFES Annual Symposium April 12, 2019 T.P. Chow
Integrated GaN Optoelectronics (Gen II)
39
• Successful demonstration of GaN LED driven by monolithically integrated vertical GaN UMOSFET with Selective Epi Removal (SER)
RPI, 2018
CFES Annual Symposium April 12, 2019 T.P. Chow
Integrated GaN Optoelectronics (Gen II)
40
RPI, 2018
Current and LOP vs. voltage LOP and EQE vs. current density
CFES Annual Symposium April 12, 2019 T.P. Chow
Integrated GaN Optoelectronics (Gen II)
41
RPI, 2018
CFES Annual Symposium April 12, 2019 T.P. Chow
Summary
• Lateral GaN p-HEMTs offer substantial performance advantages over Si
• Vertical superjunction GaN power FETs with polarization HJs are >1000X better
• Power ICs and Optoelectronic Integration have been demonstrated
42
CFES Annual Symposium April 12, 2019 T.P. Chow
Thank You!
43
CFES Annual Symposium April 12, 2019 T.P. Chow
600V Power Device Comparison
CFES Annual Symposium April 12, 2019 T.P. Chow
1.2 kV Power Device Comparisons
Device Ron,sp (mΩ.cm2)
VF (V)
Vth (V)
Esw (mJ/cm2)
ton (ns)
toff (ns)
Si UMOS FS-IGBT - 1.2 4 26.4 5 1230
SiC DMOSFET 2.3 - 2.3 0.85 1 30
GaN UMOSFET 1.5 - 4 0.5 4 40
GaN HEMT 0.9 - - 4.8 1.0 3.7 35
SiC and GaN unipolar switches can operate at much higher frequency – lower requirements on passive components
CFES Annual Symposium April 12, 2019 T.P. Chow
SiC and GaN Power Device Commericalization
• SiC – 0.6-1.7kV Schottky, MOSFET and JFET – < 600V or > 1.7kV? – 10-25kV pin rectifier or IGBT?
• GaN – 30V HEMT – 400-600V HEMT – 1-1.2kV HEMT?
46
CFES Annual Symposium April 12, 2019 T.P. Chow
*S.M. Goodnick et al., J. Vac. Sci.
Technol. B, vol. 1 (3), pp. 803-808, 1983.
GaN MOS vs. Si MOS
47
CitSRSPBtotal mmmmm
11111
itfT NNN
,)1(),( Cit
scrT
CitTCit
N
nT
NnN
m
B
B
ref
BND
T
mm
)/(1)/300(max
Bulk Mobility
3/1
TE
B
E
ASPm
Surface Phonon
2
E
SR
m
Surface Roughness Coulombic
CFES Annual Symposium April 12, 2019 T.P. Chow
Interface State Density Comparisons
EvSi EcSi Ec4H-SiCEv4H-SiC
1E10
1E11
1E12
1E13
EcGaNEvGaN
Interfacestateden
sity(cm
-2eV-1) Si
4H-SiCGaN
CFES Annual Symposium April 12, 2019 T.P. Chow
JI, SOI and DI RESURF Junction Isolation (JI)
RESURF Silicon on Insulator (SOI)
RESURF Dielectric Isolation (DI)
RESURF
• Junction Isolation (JI) RESURF balance the ionized donor (ND
+) in n- drift region with ionized acceptors (NA-) in the p-
substrate.
• Silicon on Insulator (SOI) RESURF balance the ND+ in drift
region with electrons in the n+ substrate.
• Dielectric Isolation (DI) RESURF balance the ND+ with other
negative charges such as anode or field plates
49
CFES Annual Symposium April 12, 2019 T.P. Chow
Drift Region Optimization
Silicon
UID Al0.05GaN
SiO2
DrainSource
UID GaN
GateUID Al0.25GaN
ILD
AlN/GaN Buffer
Silicon
UID Al0.05GaN
SiO2
DrainSource
UID GaN
GateUID Al0.25GaN
ILDUID GaN
AlN/GaN Buffer
Without GaN cap With GaN cap
• Without GaN cap, interface charges between ILD and AlGaN make surface electric field uniformity difficult
• With GaN cap, charge balance in AlGaN layer and minimization of interface charges between ILD and GaN cap enhances surface electric field uniformity (Natural RESURF)
50
CFES Annual Symposium April 12, 2019 T.P. Chow
Enhancement Mode GaN Power Transistor
• Recessed channel – etch control • F implantation – epi dependent • MOS channel – low mobility and gate oxide
reliability • P-(Al)GaN gate – etch stop and damage • Back channel - structural and compositional
control • Cascoded HEMT – Packaging parasitics, device
matching and difficulty in current scale-up
51
CFES Annual Symposium April 12, 2019 T.P. Chow 52
Wch = 200 mm, Lch= 2 mm, LGS= 3 mm
• Breakdown voltage saturated over Lgd of 15 µm • Thicker Epi wafer => Higher Breakdown voltage • Growth of thick GaN epi or insulating buffer is the major limitation on breakdown voltage for devices of GaN on silicon • Specific on-resistances of 16.3-16.8m-cm2 have been obtained.
Buffer
Si(111) Substrate
GaN:Mg
DSAlGaNu GaN
G
① Breakdownbetween G-D
② Breakdown in epilayer
0
100
200
300
400
500
600
700
0 4 8 12 16 20 24 28 32 36Lgd (μm)
Bre
akdo
wn
Vol
tage
(V)
①
②
Thickness 4.4 mm
Thickness 2.6 mm
Furukawa MOS Channel-HEMT
Furukawa, ISPSD, 2009
CFES Annual Symposium April 12, 2019 T.P. Chow
RPI MOSC-HEMT • BV = 350V
• Ron,sp=4.0mOhm-cm2 • VT=0.3V
RPI, ISPSD 2012
• Lch=0.3 um • Ldrift=8 um
53
-2.00E-02
0.00E+00
2.00E-02
4.00E-02
6.00E-02
8.00E-02
1.00E-01
1.20E-01
0 2 4 6 8 10 12 14 16
-1.00E-04
0.00E+00
1.00E-04
2.00E-04
3.00E-04
4.00E-04
5.00E-04
6.00E-04
0.00E+00 1.00E+02 2.00E+02 3.00E+02 4.00E+02
Id
Ig
Id
Ig
Id
Ig
MOS Channel-HEMT on Si
CFES Annual Symposium April 12, 2019 T.P. Chow
Current Collapse
54
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
0 10 20 30 40
DC
Cu
rren
t C
oll
ap
se
Ra
tio
RESURF length (um)
MOSHEMT on UID GaN
MOSHEMT on P GaN
• Current collapse measured on both GaN RESURF MOS-HEMT on UID and p GaN epi
• No correlation of current ratios for different RESURF length
• MOS-HEMTs on p GaN showed ratio close to 1, which is much less as compared with that of UID GaN
0 20 40 60 80 100 120
0.80
0.85
0.90
0.95
1.00
1.05
10 12 14 16 18 20 22 24 26
Channel length of Non-RESURF Device (um)
DC
Cu
rren
t C
oll
ap
se
Ra
tio
RESURF length of RESURF Device (um)
RESURF Devices
Non-RESURF Devices
• Current collapse measured on RESURF and non-RESURF MOS-HEMTs on p GaN
• Current ratio all close to 1, with little dependence on the MOS channel length for non-RESURF devices and the RESURF length for RESURF devices.
MOSC-HEMT on UID GaN vs. P GaN Non-RESURF vs. RESURF device
CFES Annual Symposium April 12, 2019 T.P. Chow
Current Collapse
55
GaN MOSFET GaN MOSC-HEMTs on UID
GaN vs. P GaN
*RPI, ISPSD 2010
CFES Annual Symposium April 12, 2019 T.P. Chow
Integrated GaN HEMT Cascoded Pair
56
UKNC,, ICNS, 2015
CFES Annual Symposium April 12, 2019 T.P. Chow
GaN PWM IC
57
HKUST, ISPSD, 2014
CFES Annual Symposium April 12, 2019 T.P. Chow
GaN PWM Power Converter
58
CPEC, CICC, 2015
CFES Annual Symposium April 12, 2019 T.P. Chow
Optoelectronic IC Integration
59
Silicon
UID Al0.05GaN
SiO2
DrainSource
UID GaN
GateUID Al0.25GaN
ILDUID GaN
AlN/GaN Buffer
Left to Right: MOS-HEMT structure for GaN on Silicon, Current LED structure, Proposed GaN-CMOS structure.
Sapphire
GaN N-GaN
InGaN-GaN QW Layers
P-GaN
P-contact/spreading
N-contact
Drain Source Drain Source Source
Sapphire GaN
P-GaN N-GaN
gate gate
N-GaN P-GaN
The ability to use Silicon as a substrate for LEDs will lead to a lower overall cost. To prepare for this paradigm shift, we have included research on GaN-MOS-HEMTs built on a Silicon substrate.
GaN controls and power FETs will enable high frequency and high efficiency switching for data and power conversion applications