Software Defined Radio Technology for Radar Systems

Dr. Bertalan EGED

Sagax Communications, Ltd., Haller u. 11-13. Budapest 1096 Hungary www.sagax.hu

Introduction In the following paper we will receive a short introduction of the softwer defined radio (SDR) technology which could be used in the radar systems too. First we will see the roots of this technology, where does it come from

and what is the basic idea behind that. Second a short modelling of the digital radio device based on the SDR

technology will be presented and following on that the different kind of implementation level will be introduced. This simple model will be devided on the three main parts of the SDR based implementation such as analog

front-end processing, domain conversion and digital signal processing. Following on that the software

communication architecture operationg environment will be introduced. Later some related work in RTO and future trends will be described.

I. Motivation factors of SDR technology To introduce of the roots of the SDR concept the following figure (Fig. 1.) shows a soldier with all of the

modern communication equipments which should be carried on the battlefield. Containing all the radio device antenna, external battery, communication equipment etc. rom this picture it could be seen that it is a non-

manageable situation and some kind of solution should be find out to provide more useful, more lightweight,

more effective equipments for the soldiers.

Fig. 1.

Beyond this the other fact which was driven the SDR technology is that the US department of defence

inventories has got at least 25 or 30 different radio types which actually means 75 000 radios in all and many of these radios are near to the end of its operational lifetime. So it seems to be that the managing and logistic

support which should be provided for such number of radios is really nightmare for logistics experts. For this

reason it was decided that some kind of new solution should be provided for the soldiers and this was the basic

driver motivation factor which started the development of the software defined radio technology.

II. Modelling of SDR based devices

On the following figure (Fig. 2.) you could see a radio electronic device models. In the traditional implementation we can find dedicated hardver components including the antenna, IF down conversion, after that

IF to base-band conversion, base-band demodulating and processing. Finally we can find a man-machine

interface (MMI), which could be seen as a traditional hardver including push-buttons, switches etc.

Fig. 2.

In the case we use software defined implementation we could devide the model of the device only three main parts. After the antenna we can find an analog signal processing, it is followed by a domain conversion, which

means that we have to convert the signal from analog domain to digital domain or vica versa from digital domain

to analog domain, when we are talking about the receiving equipments or transmitting equipments respectively. The third part of the model contains only the digital signal processing. The man-machine interface of this kind of

device looks like a graphical application program (GUI). We have no real hardver components on the man-

machine interface, we can use this type of radio as a standard computer software. In the figure the analog signal processing is represented with traditional radio frequency hardver, domain

conversion is represented as a high speed digital circuit containing different kind of digital hardver components

and digital signal processing could be represented as a block diagram of the signal processing algorithms running on a computing platform. As it was mentioned the user interface is implemented as a graphical program.

II.1. Inplementation level of SDR

We can differentiate different kind of implemetation levels in the radio device and on the following figure (Fig. 3.) we can see a model of a simple digital signal handling implementation level where after the demodulation we

can handle the message content of the radio device in digital way, this is the digital signal handling

implementation level. The second step when all of the base-band processing implemented in digital domain, in

this case we talk about digital base-band processing, after that, of course, it is possible to implement all the

intermediate frequency processing in digital domain, and this is the digital IF level. In the case we have a radiated band in the converter’s frequency range it is possible to implement all of the radio frequency, RF to IF

down conversion in digital domain. This kind of implemetation is called digital RF processing radio, or direct digital radio.

Fig. 3.

As you can see this is the basic idea behind the SDR technology: we have to place the analog to digital converter as close to the antenna as possible. It means that all the other functionality of the radio device could be

implemented in digital domian. In this case we have a very future-proof and very easy-to-upgrade structure

because only the software should be changed and the functionality of the device is mainly deterimined by the software running on the platform.

II.2. Analog signal processing

After this short introduction let’s walk trough of the different parts of this model. The first part is the analog

front end signal processing. Basically it is responsible for frequency transformation for radiated airband to the digitally processable frequency band. Air band means the frequency range which is received or transmitted by

the antenna. The performance merits of this part of the model is mainly the noise level, dynamic range, the

frequency bandwidth, the frequency agility, which means how fast is it possible to change the frequency of this front end. Tipical technologies which are used in this part of the devices are the frequency generation, mixing,

filtering, gain control and of course, amplification. Representing of this part of the device I placed here simple

heterodyne conversion block including basic radio frequency filter, intermediate frequency filter, and a mixer using a local oscillator signal. The frequency plot of this converter includes the local signal, image signal and

the IF signal respectively. (Fig. 4.)

Fig. 4.

Typical analog front end architecture of a transmitter could be a digital baseband generation where it is possible

only generate the basement signal in digital domain. After that an analog signal generated and up converted by

the IQ modulator to the intermediate frequency which is later up converted the radio frequency. The second tipical structure when the IQ modulation implemented in digital domain too and the complete

intermediate frequency signal is generated digitally and after that the IF frequency converted from digital to analog domain and later up converted the radio frequency level.

Fig. 5.

The highest level of the implementation when it is possible to generate the real airband radio frequency by the

digital to analog converter and in that case the final frequency is generated, so no more analog frequency transformation is required. (Fig. 5.)

II.3. Domain conversion

The next step of the model is the domain conversion. Domain conversion is responsible for conversion between

the analog and digital representation of the signals. The perfomance merits of this part are mainly the input and instantenous bandwidth, the noise level and dynamic range. Lot of different technologies are available today to

implement wide band-width and high-speed converters, like flash, pipeline, folding, sigma-delta and interleaved

converters.

Fig. 6.

Representing for this part of the digital radio platform the following figure (Fig. 6.) shows the Nyquist bandwidth and frequency bands of the analog digital converter and the amplitude range from the full scale to the

quatization noise of the converter. We have to note that in real wide-band converters not the quantatization noise

limits the dynamic range. In its spectrum we can find some kind of spurious signal, which is coming from the non linearity of the transfer function of the converter. These spurious signals limits the dynamic range so the

usable dynamic range so called as spurious free dynamic range (SFDR), which is the difference between the full-

scale level and the highest level of the spourious signal, which we can see on the figure too.

Fig. 7.

Analog digital converters evolution could be seen in the next figure. (Fig. 7.) This is a kind of performance plots

of the converters where we can see the sampling rate as a X scale and resolution on the Y scale. It could be seen

that it is possible to use very fast converters but we have to pay with its dynamic range represented by resolution. With the decreaseing of the resolution in bits of the converters the smapling rate could be increase. The first is a

performance profile which represents the situaton in 1990. [1] The figure contains the performance curve of the analog to digital converter based on data from 2005, 15 years later. [2]

Fig. 8.

It is interested to see that the evolution of the converters also follow the Moore’s law. It means that every second

year the performance is doubled. It is very important to mention that in a high speed wide band converter we have very tight requirements for

sampling clock. In the following figure (Fig. 8.) you can see that in the case we have a given sampling window in the sampling clock, the amplitude variation will be significantly higher when we would like to sampling high-speed wider band-width signal.

It means in the spectrum domain that in the case we will show the amplitude plot of the signal using the same

sampling clock in the case we increase the signal frequency which is sampled by this clock we can see significant noise margin around the signals mainly coused by the noisy sampling clock.

If we calculate, the signal to noise ratio depends on what is the jitter of the sampling clock signal. For instance

we can see that with one picosecond jitter signal at 100 MHz equal with a nearly a 16 bit conerter’s signal to noise ratio. In the case we have worse noise performance of the clock signal the available signal to noise ratio

mainly limited by the clock and not the converter itself. On the table below this graph shows numerically these

values. The performance limit on the required jitter performance of the clock signal, input frequency and converter resolution in bits.

It means that in the clock distribution network we have to use very high speed and low jitter distribution chips, including ECP or ECL models which shows better jitter preformance than 1 picosecond. [3]

We have some possibilities to improve the dynamic range by ditering. In the following figure (Fig. 9.) we can

see that what is the problem with dynamic range. This is the transfer function curve of the analog digital converter where it could be seen it is non linearity and it will cause some kind of spurious signal. These spurios

signals can be seen in a frequency domain too. As it was described the dynamic range is mainly limited by these spurios signals and not the quantitation noise. To overcome this problem we could add some kind of noise generator, this noise generator could produce noise signal which is not in the interested frequency range so in the

case we are able to sampling as a bandpass sampling and add external noise generator in the range does not

contain the interesting signal we could reduce the spurious level of the converter. In the figure we can see that using the ditering noise signal it is possible to increase the spurious free dynamic range more than 15dB, which

is a very good performance increasing. As you can see the ditering signal transfers the energy of the the spurious

signals on the base band so close to the zero frequency we can find very big spurious content, that is why we have to use the band pass filtering and sampling. [4]

Fig. 9.

II.4. Digital signal processing

The function specific integrated circuit (FSIC), it is not an application specific, but instead of that we have to mention the fuction specific. It means that some kind of functions like FFT, IFFT, digital down conversion or up

conversion is a very typical and common function which should be used in digital radio implemetations. This

function specific ICs best in speed performance, but they have limited configurability, altough they have some kind of configuration capability. (Fig. 10.)

The next step is programmable field arays (FPGA), in these chips could be implemented any hardver function with arbitary changed configuration. Comparing with the function specific it is slower and more expensive.

The following step is deticated signal processing (DSP). Such kind of processor has got optimized architecture for tipical processing tasks but the main drawback of this kind of processors is that in spite of they have very

optimized internal structure nearly all of them have limited data transfer cabability.

The next component is the general purpose processor (GPP) which is used in every computer on the desktop.

Mainly the performance is limited by the architecture but the very high speed of execution and paralell processing capability nearly overcome this kind of problem. They have very good data transfer capabilities.

Fig. 10.

How these chips could be used in the platform? The best is to combine function specific ICs with programmable/deticated signal processor and general purpose processor taking advantage of each other and its

characteristics.

Fig. 11.

III. Internal architecture of the SDR based device

At that point we reached the necessity of connecting different kind of platform components together. One of the basic outcome of the US DoD JTRS project, which was started to develope the SDR radio for commucation

requirements is the defined common interface which could be used for connecting the different kind of components together. This common interface is based on the common object request broker architecture. This is

CORBA, a kind of object oriented modelling to link different kind of components together. Based on that

interface it is possible to use even a commercial of the self (COTS) hardver running a common framework on that and different kind of applications on the top of the core framework. (Fig. 11.)

The following figure (Fig. 12.) shows the architecture which is used in the JTRS SDR model to define some operating environment. The basic idea behind this that based on a programmable radio hardver including

modem, radio frequency interfaces, link interfaces, we have to build an operating system and middle of this is

the part of the core framework. If this core framework is able to provide an SCA compliant interface it is possible to running different kind of applications on the top of that. Platform developers are responsible for

making radio platforms and application developers are responsible for making different kind of applications

which can run on this platform. All together this is a JTRS set.

At that point I would like to introduce the model which was developed for this SCA architecture. All of the basic

principles which were described are based on this architecture. [5]

Fig. 12.

IV. Other SDR related work in RTO In IST panel there is a research task group IST-080, which is working on to demonstrate the portability

nationally developed waveforms on different natinal SDR platforms. (Fig. 13.) The basic goal of this task group

is to prove the principle whether it is possible to transfer one waveform to the other platform etc. This is also a possible way to follow up for radar community to develop an SCA compliant passive radar receiver

demonstrator.

Fig. 13.

V. Future trends

One of them is the useage of opto electronic devices. It seems to be that optical sources have better jitter or phase noise performance, so better frequency mixers and samplers could be build based on that technology. In the

literature it is reported radio frequency front end running from 2 GHz to 18 GHz with 500 MHz instantenious

bandwidth and 3dB noise figure with high dynamic range. The layout of such a device could be seen in the figure with two different optical fibre connection. The next figure contains a photo of the lab prototype of this

kind of electro optical microwave mixer. [6]

The second is a high temperature super conducting. It seems to be that one of the limits of high level integration

is the power dissipation. Handling heating problems more compact and effective devices could be implemented.

The next figure contains a chip layout of the reported analog to digital converter with 20 GHz sampling rate and 12 bit resolution, and the laboratory version of this super conducting ADC device could be seen too. [7]

Fig. 14.

VI. Conlusions Software defined radio technology determines the developement trends in radio electronic evolution and radar

systems also will follow this general trend. Some potential technology could be seen to ensure the base of

developments in bandwith and dynamic range and based on that potentional technologies it is possible to improve the radar systems too.

VII. References and readings

[1] R.C.Hiks „A Servey of Analog to Digital Converters for Radar aplication”, Radar 92. International Conference, 12-13 Oct 1992, pp. 534 - 537

[2] Kent H. Lundberg, „High-Speed Analog-to-Digital Converter Survey”,

http://web.mit.edu/klund/www/papers [3] F. Boré, S. Bruel, M. Wingender „A 10-bit 2.2 Gsps ADC Operating Over First and Second Nyquist

Zones”, ATMEL Application journal, Number 6, Winter 2006, pp. 43-48. www.atmel.com

Analog Devices Application Note 501: Aperture Uncertainty and ADC System Performance , www.analog.com

[4] Linear Technoligy Design Note 1013: Understanding the Effect of Clock Jitter on High Speed ADCs,

www.linear.com [5] R. H. Hosking, „Building SCA-compliant software-defined radios „ DSP DesignLine , September 27,

2006, www.dspdesignline.com

[6] www.ece.drexel.edu/CMLE/index.html [7] MUKHANOV et al.: SUPERCONDUCTOR ANALOG-TO-DIGITAL CONVERTERS,

PROCEEDINGS OF THE IEEE, VOL. 92, NO. 10, OCTOBER 2004, www.hypres.com