spec_ dappro 16mb sram - 5v - qfp68

7/27/2019 Spec_ Dappro 16Mb SRAM - 5V - QFP68

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Doc. N:3DPAxxxx-1 Page 1/23

3D PLUSORIGINE: 3D PLUS S.A.

641, rue Hlne Boucher - Z.I.

78532 BUC Cedex

DETAIL SPECIFICATION

16Mbit SRAM Module 12ns Access Time 5.0V

512K x 32 QFP 68 Pitch=1.27mm

Part Number: MMSR32510804QCX

3DPAxxxx-1

Name Responsibility Date Signature

P. MAURICE General Manager 4th

June 2007

Approved Responsibility Date Signature

D.BLAIN Quality Assurance Manager

P.E.BERTHET Sales & Marketing Director

N.FIANT Test Manager

First Issue: 04/06/07 Archive : Buc

DOCUMENT REFERENCE COMPANY CLASSIFICATION PAGES

TypeDoc. Document N Issue LanguageCode Secret Reserved 23

3DPA xxxx 1 GB Confidential Not protected


2/23

Doc. N:3DPAxxxx-1 Page 2 / 23

DIFFUSION LIST

Document Management D. BLAIN Quality Assurance Manager

Distributed to Responsibility

P. MAURICE General Manager

N.FIANT Test Manager

Customers


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CHANGE RECORD

Ed./Rev. Date Approved Description Written by

1 04/06/07 DB /PEB/NF Initial Document PM


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TABLE OF CONTENTSFront Page 1Diffusion List 2

Change Record 3

Summary 4

1) GENERAL ................................................................................................................................5

1.1 Purpose and Scope .............................................................................................................51.2 Type Variants.....................................................................................................................5

1.3 Maximum Ratings..............................................................................................................5

1.4 Physical Dimensions ..........................................................................................................6

1.5 Pin Assignment Figure 2a................................................................................................6

1.6 Module Schematic Figure 2b ............................................................................... ............8

1.7 Module Capacitance Table .................................................................................................9

1.8 Electrical Performance and characteristics..........................................................................9

2) APPLICABLE DOCUMENTS ................................................................................................10

2.1 Reference Documents.......................................................................................................10

2.2 Applicables Documents....................................................................................................10

3) PACKAGING REQUIREMENTS...........................................................................................11

3.1 Mechanical Requirements ................................................................................................113.1.1 Dimension check ......................................................................................................11

3.1.2 Weight......................................................................................................................11

3.2 Case, Material and Finishes..............................................................................................11

3.2.1 Case..........................................................................................................................11

3.2.2 Lead Material and finishes... ...................................................................... ...............11

3.3 Marking ...........................................................................................................................11

3.3.1. General.....................................................................................................................11

3.3.2. Pin 1 indicator ..........................................................................................................11

3.3.3. Module Part Number ................................................................................................11

3.3.4. Module Serial Number (only for space grade models)............................................... 11

3.3.5. Date Code (WWYY) ................................................................................................12

4) MEMORY MODULE..............................................................................................................134.1 General.............................................................................................................................13

4.1.1 Procurement of EEE Components............................................................................. 13

4.1.2 Procurement of Printed Circuits Board (PCB)...........................................................13

4.1.3 SRAM TSOP Lot Acceptance Test................... ......................................... ...............13

4.1.4 Module Manufacturing .............................................................................................14

4.1.5 Module Screening.....................................................................................................14

4.1.6 Module Lot Acceptance Test (Not applicable for Industrial Grade Model)................ 21

4.2 Failure criteria..................................................................................................................21

4.2.1 Parameter Limit Failure ............................................................................................21

4.2.2 Parameter Limit Failure ............................................................................................21

4.3 Lot Rejection....................................................................................................................22

4.4 Data Documentation.........................................................................................................22

4.5 Packing, Handling, Storage and Mounting Requirements ................................................. 22

4.5.1 Packing.....................................................................................................................22

4.5.2 Handling...................................................................................................................22

4.5.3 Storage .....................................................................................................................22

4.5.4 Board Assembly .......................................................................................................23

4.5.5 Electrostatic Discharge Sensitivity....................................................... .....................23

4.6 Radiations ........................................................................................................................23


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1) GENERAL

1.1Purpose and Scope

The following document details all the activities to be performed to produce and test a 3D PLUS

memory module for space application. In particular details the ratings, physical and electrical

characteristics, tests and inspection data for the 3D PLUS Module 16Mb SRAM 512Kx32, PN :

MMSR32510804QCX and shall be read in conjunction with the applicable documents therequirements of which are supplemented herein.

1.2Type Variants

Variants of the module specified herein, which are also covered by this specification, are given in

Table 1(a).

Table 1(a) Component Type Variants

Variant Part Number Function Case Lead Material and FinishMMSR32510804QCX-IB Industrial Grade

Model

QFP 68 pins Pitch=1.27mm

(see Fig. 1a)

Kovar

Ni+Au plating

MMSR32510804QCX -IS Space Grade

Model

QFP 68 pins Pitch=1.27mm

(see Fig. 1a)

Kovar

Ni+Au plating

Note : These variants are suitable for automatic reflow assembly.

Module assembly on board must follow reflow guidelines as defined in:

http://www.3d-plus.com/PDF/Application/Assembly_recommendations_Automatic_Reflow_v2.pdf

or for hand soldering

http://www.3d-plus.com/PDF/Application/Assembly_recommendations_Manual_Reflow_v2.pdf

1.3Maximum Ratings

The maximum ratings, which shall not be exceeded at any time during use or storage, applicable to

the module specified herein, are as scheduled in Table 1.b.

Table 1(b) Absolute Maximum Ratings (Note 1)

N Characteristics Symbol Maximum

Ratings

Unit Remarks

1 Voltage on any pin relativeto VSS

VT -0.5 to VDD+0.5 V

2 Voltage on VDD supplyrelative to VSS

VDD, VDDQ -0.5 to 7.0 V

3 Storage Temperature Range Tstg -65 to +150 C

4 Operating Temperature

Range

Top -40 to +85 C Ambient temperature

5 Power Dissipation PD 1.0 W Per Byte

6 Reflow Temperature (Peak) Tsol 215 C Measured at moduleside level

9 Thermal resistance Junction

to ambient

RTH(J-A) 40 C/W Note 2

Note 1 : Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Operating Temperature

Range may be increased to +125C during dynamic Burn-in and Life test. Functional operation should be

restricted to recommended operating condition. Exposure to higher than recommended voltage for extended

periods of time could affect device reliability.

Note 2: In RTH(J-A) (Thermal resistance Junction to ambient), Ambient is defined as the temperature at the bottom of

the leads in contact with the board.


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1.4Physical Dimensions

The physical dimensions of the used package are shown in figure 1.

1.5Pin Assignment Figure 2a

PinNbr SignalName PinNbr SignalName PinNbr SignalName PinNbr SignalName PinNbr SignalName

1 Vss 15 DQ5(0) 29 A12 43 NC 57 DQ3(2)

2 #CS2 16 DQ6(0) 30 A13 44 DQ7(3) 58 DQ2(2)

3 A5 17 DQ7(0) 31 A14 45 DQ6(3) 59 DQ1(2)

4 A4 18 Vss 32 A15 46 DQ5(3) 60 DQ0(2)

5 A3 19 DQ0(1) 33 A16 47 DQ4(3) 61 Vdd

6 A2 20 DQ1(1) 34 #CS0 48 DQ3(3) 62 A10

7 A1 21 DQ2(1) 35 #OE 49 DQ2(3) 63 A9

8 A0 22 DQ3(1) 36 #CS1 50 DQ1(3) 64 A8

9 NC 23 DQ4(1) 37 A17 51 DQ0(3) 65 A7

10 DQ0(0) 24 DQ5(1) 38 #WE1 52 Vss 66 A6

11 DQ1(0) 25 DQ6(1) 39 #WE2 53 DQ7(2) 67 #WE0

12 DQ2(0) 26 DQ7(1) 40 #WE3 54 DQ6(2) 68 #CS3

13 DQ3(0) 27 Vdd 41 A18 55 DQ5(2)

14 DQ4(0) 28 A11 42 NC 56 DQ4(2)


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FIG. 1 Physical Dimensions

R=0.40


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1.6Module Schematic Figure 2b

#OE

A(18:0)

#CS3 #WE3 #CS2 #WE2 #CS1 #WE1 #CS0 #WE0


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1.7Module Capacitance Table

For the 16Mb SRAM module MMSR32510804QCX the capacitance values are:

(Ta = 25C, F = 1MHz)

Parameter Symbol Min Typ Max Unit Notes

Input Capacitance CIN - - 28 pF 1Output Capacitance (DQ0 to 31) CI/O - - 16 pF 1

Note: 1. This parameter is sampled and not 100% tested.

1.8Electrical Performance and characteristics

The table 1 below gives the different timings for both 4Mb SRAM TSOP and 16Mb SRAM

module

Table 1(c) Timings

16Mb SRAM Module

16Mb SRAM Module

K6R4008C1C-10

K6R4008C1C-10


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2) APPLICABLE DOCUMENTS

2.1 Reference Documents

MIL-STD-883 G: Tests Methods and Procedures for Microelectronics RD1

MIL-PRF-38534D : Hybrid Microcircuits, General Specifications for, - RD2

ECSS-Q-60-05A: Space Product Assurance Generic procurement Requirements for

Hybrid Microcircuits - Draft document RD3

2.2 Applicables Documents

PID 3D PLUS Ref. 3300-0546 DA1

Exigences gnrales dapprovisionnement et de contrle dentre des composants EEE Ref.3DPA0350 DA2

Dossier de Dfinition 16Mb SRAM 512Kx32 QFP68 Pitch=1.27mm Ref. TBD DA3

SAMSUNG Datasheet for 4Mb SRAM K6R4008C1C - Rev 4.0 dated Sept. 24. 2001 . DA4

EIDP Format Procedure Ref. 3DPQ0050 DA5

Exigences gnrales dapprovisionnement et de contrle dentre des Circuits Imprims Ref.

3DPA0460 DA6 Procdure de DPA module 3DPF2290 DA7


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3) PACKAGING REQUIREMENTS

3.1 Mechanical Requirements

3.1.1 Dimension check

The dimensions of the module shall be checked on a sample of 3 pieces per lot in step 9 of the

screening (see 4.1.5). They shall conform to those shown in figure 1

3.1.2 Weight

The weight of the module specified herein shall be 12g +/-0.3g

3.2 Case, Material and Finishes

3.2.1 Case

The case corresponds to 3D PLUS Package : QFP 68leads Pitch=1.27mm See Figure 1.

3.2.2 Lead Material and finishes

Lead material : FeNiCo (Kovar)

Finishes : Gold Plating (1 to 2m) over Nickel (3 to 5m)

3.3 Marking

3.3.1. General

Each component shall be marked during laser grooving manufacturing step with :a) 3D PLUS Logo

b) Pin 1 indicator

c) Part Number

d) Module Serial Number (only for space grade models)

e) Date Code

3.3.2. Pin 1 indicator

An index shall be located at the top of the package in the position defined in figure 1 to

identify pin N1. The pin numbering shall be read in a counter clockwise order starting with

pin N1.

3.3.3. Module Part Number

Each module will be marked with the Module PN as defined in the left column of Table 1 (a)

3.3.4. Module Serial Number (only for space grade models)

Each component will be serialized. Such number will not be re-affected to another part

corresponding to the same device


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3.3.5. Date Code (WWYY)

Each module will be marked with a date code corresponding to the Week (WW) and the year

(YY) of the laser grooving step.

The date code corresponds to the laser grooving operation step. The module Lot is defined by

following common elements :

Homogeneous lots of components

Screening steps performed at the same timeTherefore modules from the same lot may have different date code.

For each module the full traceability (linked to the SN of the module) is given in the EIDP


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4) MEMORY MODULE

4.1 General

4.1.1 Procurement of EEE Components

The module is made of 4 memories 4Mb (512Kx8) SRAM from SAMSUNG PN :

K6R4008C1C Package TSOPII, procured in accordance with DA2.

4Mb SRAM TSOP K6R4008C1C (Die Mask Rev. C) are from the same lot if they were

procured at the same time, shipped in the same original boxes, have the same Date Code

and Lot Number.

4.1.2 Procurement of Printed Circuits Board (PCB)

A PCB is used in the for the leads assembly. It is procured in accordance with DA6 for type 3

PCB.

4.1.3 SRAM TSOP Lot Acceptance Test

For each SRAM TSOP lot used for Flight (Space grade), 22 pcs/lot are following the belowflow :

Test Description Test Conditions Qty (Reject

allowed)

1 Component Serialization 22(0)

2 Electrical Measurements (22 Parts) Read &

Record at 25C

According to 4.1.5.1

3 Dynamic Burn In 240 hrs 125C (Note 1)(Note 2)

MIL-STD-883E

Meth.1015 cond.D

and according to

4.1.5.2

4 Electrical Measurements (22 Parts) Read &Record at 25C



Record at 40C and +85C


6 Parameter Drift Calculation at +25C According to 4.1.5.4

22(1)

7 Life Test 1000hrs. at 125C (20 parts) (Note1) (Note 2)

MIL-STD-883E

Meth.1015 cond.D

and according to

4.1.5.2


Record at 25C


9 Electrical Measurements(22 Parts) Read &

Record at 40C and -+85C


10 Parameter Drift Calculation at +25C According to 4.1.5.4

22(0) or

21(0) if 1

Failure

during steps

2,4,5 or 6.

Note 1 : If JunctionTemperature during life test or burn-in is above Max. ratings, then Burn-in or Life Test

Temperature of the oven is given by:

TLT (C) = 125 PD * RJCPD = VCCmax * ICOMP = Power dissipated during Burn-in or Life Test

RJC = Thermal Resistance junction/case of the compoenent.

Note 2: Only 20 pieces follow the steps 3 & 6. The remaining 2 pieces are used as reference.


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4.1.4 Module Manufacturing

According to 3D PLUS PID (DA1) for stacked Flex (Referenced as Flow 2 in DA3).

4.1.5 Module Screening

Each Flight Module will follow the following screening flow:

Test Description

Test Condition

1 Stabilization Bake 72hrs +125C MIL-STD-883E Meth.1008 cond.B

2 Temperature Cycling 10 Cycles 55C / +125C MIL-STD-883E Meth.1010 cond.B

3 Electrical Test at 25C with R&R According to 4.1.5.1

4 Dynamic Burn-In 168hrs +125C MIL-STD-883E Meth.1015 cond.D

and according to 4.1.5.2

5 Electrical Test at 40C,+25C and +85C with R&R According to 4.1.5.3

6 Parameter Drift Calculation According to 4.1.5.4

7 PDA Calculation According to 4.3

8 External Visual Inspection 3D PLUS Procedure ref. 3300-0776

9 Dimension check According to 3.1.1

Note : For industrial grade Models, Screening is limited to steps 5, 8 & 9

4.1.5.1 Electrical measurements at +25C

The functional sequences are executed on each couple of SRAM at a time. An individual Chip

Select pin (#CS0 to #CS3) allows the test program to access the SRAMs under test.

Static and Dynamic measurements are done according to Table 2a and 2b respectively.

Functional test

Test Conditions:

Supply : VDD = 4.5V then VDD = 5.5V

Frequency : F = 20MHz [in respect with AC parameters ]

Driver : VIL = 0.4V, VIH = 2.4V

Load : IOL = 1mA, IOH = -0.5mA


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Test Patterns:

Zeros :Write and Read the entire Module with 0x0000

2 test sequences for module test (1 per #CS pin).

Ones :Write and Read the entire Module with 0xFFFF2 test sequences for module test (1 per #CS pin).

Checkerboard :Write and Read the entire memory with a Checkerboard (0xAAAA for odd addresses- 0x5555

for even addresses) and a Checkerboard Inverted (0x5555 for odd addresses 0xAAAA for

even addresses)

2 test sequences for module test (1 per #CS pin).

Table 2a: Electrical measurements at room Temperature - Dynamic Parameters

LIMITS

TSOP MODULEPARAMETERS Symbol TEST CONDITIONS

Min Max Min Max

Address to output delay TAA 10 ns 12 ns

CS to output delay TCO 10 ns 12 ns

OE to output delay TOE

Vdd=4.5VVil=0.4V Vih=2.4V

Iol=1mA Ioh=-0.5mA

5 ns 7 ns

Note: All these parameters are recorded in the datalog file.


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Table 2b: Electrical measurements at room Temperature - Static Parameters

LIMITS

TSOP MODULEPARAMETERS Symbol TEST CONDITIONS

Min Max Min Max

Operating power supplycurrent ICC Vcc = 5.5V, Iol=0mA, Min. cycle,100% duty185mA 740mA

Operating power supply

currentICC Vcc = 5.5V, Iol=0mA, F=20Mhz,

50% duty

110

mA

440

mA

TTL Standby power supply

CurrentISB CE/ = OE/ = WE/= Vih 60 mA

240

mA

CMOS Standby power supply

CurrentISB1 CE/ = OE/ = WE/= Vcc 10 mA

40

mA

Input leakage current, low

levelILIL Vcc=5.5V, VIN=0V -4A 4A -4A 4A

Input leakage current, high

levelILIH Vcc=5.5V, VIN=5.5V -4A 4A -4A 4A

Output leakage current, low

level ILOL Vcc=5.5V, VOUT=0V -4A 4A -4A 4A

Output leakage current, high

levelILOH Vcc=5.5V, VOUT=5.5V -4A 4A -4A 4A

Output voltage low level VOL Vcc=5.5V, IOL=1mA 0.4V 0.4V

Output voltage high level VOH Vcc=5.5V, IOH=-0.5mA 2.4V 2.4V

Note: All these parameters are recorded in the datalog file.

4.1.5.2 Dynamic Burn-in

The test shall be performed according to the MIL-STD-883E, Method 1015 Condition D.

The following sequence is applied to the devices under test :

- Power up

- Continuous writing with a Checkerboard pattern- Power down

Burn-in and Life test conditions are defined in Table 3

Life test circuit for TSOP is given in figure 3

Life test circuit for module is given in figure 4


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Table-3 Conditions for Dynamic Burn-in and Life test

No. CHARACTERISTICS Symbol Condition Unit

1 Clock Frequency f 125 KHz

2 Power Supply VCC 5.5V V

3 Temperature TLT(Note 1) 125 C

4 Duration time burn-in - 168 Hrs

5 Duration time life test - 1000 Hrs

Note 1 : If JunctionTemperature during life test or burn-in is above Max. ratings, then Burn-in or Life

Test Temperature of the oven is given by:

TLT (C) = 125 PD * RJCPD = VCCmax * ICOMP = Power dissipated during Burn-in or Life Test

RJC = Thermal Resistance junction/case of the compoenent.


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Figure 3 : Dynamic Burn-in and Life Test circuit for

4 Mbit SRAM TSOP

R=10K

R=10KR=10K

R=10K

R=10K

R=10K

R=10K

R=10K

5.5V

GND

R=10K

R=10K

R=10K

R=10KR=10K

R=10K

R=10K

R=10K

NC -----

NC -----

A0 -----

A1 -----A2 -----

A3 -----

A4 -----

#CS -----

I/O1 -----

I/O2 -----

Vdd -----

Vss -----

I/O3 -----

I/O4 -----

#WE -----

A5 -----A6 -----

A7 -----

A8 -----

A9 -----

NC -----

NC -----

1

2

3

45

6

7

8

9

10

11

12

13

14

15

1617

18

19

20

21

22

44

43

42

4140

39

38

37

36

35

34

33

32

31

30

2928

27

26

25

24

23

----- NC

----- NC

----- NC

----- A18----- A17

----- A16

----- A15

----- #OE

----- I/O8

----- I/O7

----- Vss

----- Vdd

----- I/O6

----- I/O5

----- A14

----- A13----- A12

----- A11

----- A10

----- NC

----- NC

----- NC

R=10KR=10K

R=10K

R=10K

R=10K

R=10K

R=10K

GND

5.5V

R=10K

R=10K

R=10K

R=10KR=10K

R=10K

R=10K

Number of positions / Board = 20

Each signal (input or output) is connected to a 10 K resistor to ensure electrical insulationbetween the different positions

Addresses, Data and command signals are connected to the driver board for burn-in softwareoperation


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Figure 4 : Dynamic Burn-in and Life Test circuit for

16 Mbit SRAM Memory Module

Pin

Nbr

Signal

Name

Pin

Nbr

Signal

Name

Pin

Nbr

Signal

Name

Pin

Nbr

Signal

Name

Pin

Nbr

Signal

Name

1 GND 15 R=10K 29 R=10K 43 NC 57 R=10K

2 R=10K 16 R=10K 30 R=10K 44 R=10K 58 R=10K3 R=10K 17 R=10K 31 R=10K 45 R=10K 59 R=10K

4 R=10K 18 GND 32 R=10K 46 R=10K 60 R=10K

5 R=10K 19 R=10K 33 R=10K 47 R=10K 61 5.5V

6 R=10K 20 R=10K 34 R=10K 48 R=10K 62 R=10K

7 R=10K 21 R=10K 35 R=10K 49 R=10K 63 R=10K

8 R=10K 22 R=10K 36 R=10K 50 R=10K 64 R=10K

9 R=10K 23 R=10K 37 R=10K 51 R=10K 65 R=10K

10 R=10K 24 R=10K 38 R=10K 52 GND 66 R=10K

11 R=10K 25 R=10K 39 R=10K 53 R=10K 67 R=10K

12 R=10K 26 R=10K 40 R=10K 54 R=10K 68 R=10K

13 R=10K 27 5.5V 41 R=10K 55 R=10K14 R=10K 28 R=10K 42 NC 56 R=10K

Number of positions / Board = 16

Each signal (input or output) is connected to a 10 K resistor to ensure electrical insulationbetween the different positions

Addresses, Data and command signals are connected to the driver board for burn-in softwareoperation


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4.1.5.3 Electrical Test at 40C, +25C and +85C

The test, test conditions and limits are identical to those performed at 25C.

The electrical measurements shall be performed with read and record according to4.1.5.1 of this

document.

4.1.5.4 Parameter Drift Calculation

Parameter drift values between pre and post dynamic burn-in test measurements at 25C shall be

calculated and recorded in absolute values for all parameters measured, as per Table 4 of this

document.

Table 4 Parameter Drift Calculation

DRIFT LIMIT

TSOP/FLEX

DRIFT LIMIT

MODULEPARAMETERS SYMBOL

MIN MAX MIN MAX

Operating power supply current ICC -10% +10% -10% +10%

TTL Standby power supply Current ISB -10% +10% -10% +10%

CMOS Standby power supply Current ISB1 -2mA +2mA -2mA +2mA

Input leakage current, low level ILIL -1A +1A -1A +1A

Input leakage current, high level ILIH -1A +1A -1A +1A

Output leakage current, low level ILOL -1A +1A -1A +1A

Output leakage current, high level ILOH -1A +1A -1A +1A

Output voltage low level VOL -100mV +100mV -100mV +100mVOutput voltage high level VOH -100mV +100mV -100mV +100mV

Address to output delay TAA -10% +10% -10% +10%

CS to output delay TCO -10% +10% -10% +10%

OE to output delay TOE -10% +10% -10% +10%


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4.1.6 Module Lot Acceptance Test (Not applicable for Industrial Grade Model)

Some modules that passed module screening will be used for module LAT. Modules with

minor visual defects may be accepted for LAT. The table below gives the quantity of modules

D.P.A. is performed on 1 module that went through life testing.

Module lot size Sample 1 lot Sample next lots1 to 25 2 1

26 to 50 3 2

51 to 90 4 3

> 90 5 4

The following test flow shall be applied to LAT Modules:

Test Description Test Condition

1. Dynamic Life Test 1000hrs Test conditions for Life test detailed in

Table 3

Test circuit as per figure 4

2. Electrical test at 40C/+25C/+85C As per para 4.1.5.3 of this document3. Parameter Drift Calculation As per para 4.1.5.4 of this document

4. External Visual Inspection 3D PLUS Procedure ref. 3300-0776

5. DPA (1 module / LAT Lot) According to 3D PLUS procedure

3DPF2290

4.2 Failure criteria

4.2.1 Parameter Limit Failure

A component shall be counted as a limit failure if one or more parameters exceed the limits

shown in Tables 2 and Table 4 of this specification. Any component which exhibits a limit

failure prior to the burn-in sequence shall be rejected, but not counted when determining lot

rejection

4.2.2 Parameter Limit Failure

A component shall be counted as a failure in any of the following cases:

- catastrophic failure;- mechanical failure;- handling failure;- lost component.


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4.3 Lot Rejection

On the basis of the failure criteria described above (excluding handling failures and lost components)

the following criteria will be applied :

If the number of modules that do not pass the drift calculation at +25C, is above +5%, the lot isrejected.

If the cumulative number of modules that do not pass the drift calculation at +25C and theelectrical tests at Tmin, +25C, Tmax after Burn-in is above 10%; the lot is rejected.

If failures are met during LAT (See Chapter 4.1.6), the lot is rejected.

4.4 Data Documentation

The Flight modules (Space Grade) are delivered with an End Item Data Package (EIDP) , whose

format is defined in DA4. This document includes a Certificate of Conformance to this specification,

and lists all the information regarding :

- Traceability- Electrical test results- Screening test results

- Non Conformances- For industrial grade Models, modules are delivered with Certificate of Conformance only.

4.5 Packing, Handling, Storage and Mounting Requirements

4.5.1 Packing

Modules are packed in Trays

Each box is leaded with antistatic plastic under vacuum with dissequants.

Each box is marked with :

- 3D PLUS Logo- Module description : 16Mb SRAM- Module PN : See Table 1 (a)- Qty

4.5.2 Handling

3D PLUS modules must be handled with antistatic gloves and antistatic brackets.

4.5.3 Storage

In order to avoid a degradation due to humidity, components, must be handled according to

the following procedure:

Storage in sealed bag: 5~35C and 85% relative humidity (RH)

After the sealed bag is opened, devices must be stored at 30% relative humidity andtemperature 22C +/-2C.

Note: Device container cannot be subjected to temperature > 80C, so devices must be baked

on another tray.


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3 1 23/23

4.5.4 Board Assembly

Prior to mounting on PCB, the modules must be baked 24hrs at +125C +/-5C. DO not bake

modules in trays

The use of scotch tape as kapton on the side of the module during assembly is

prohibited.

Module assembly on board must follow reflow guidelines as defined in:http://www.3d-plus.com/PDF/Application/Assembly_recommendations_Automatic_Reflow_v2.pdf

or for hand solderinghttp://www.3d-plus.com/PDF/Application/Assembly_recommendations_Manual_Reflow_v2.pdf

4.5.5 Electrostatic Discharge Sensitivity

In order to avoid ESD damage and to guarantee reliable assembling of the Module, 3D PLUS

methods and instructions for ESD protections or equivalent have to be applied.

4.6 Radiations

No radiation testing specified.

For information, following radiation data may be guaranteed:

Total Dose : 50 kRad(Si)

LET Threshold : 80 Mev-cm2/mg

SEU Threshold : 2 Mev-cm2/mg