Lithographym e t r o l o g y

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Optimizing FinFET Structures with Design-based Metrology

Tom Vandeweyer, Christie Delvaux, Johan De Backer, and Monique Ercken, IMEC

Gian Lorusso, Radhika Jandhyala, Amir Azordegan, Gordon Abbott, and Zeev Kaliblotzky, KLA-Tencor Corporation

Considering the engineering challenges in developing a reliable high-k gate stack that limits leakage current for planar transistors, fin field effect transistor (FinFET) structures may actually be needed at the 65-nm node. The decreasing sizes of FinFETs make it particularly important to obtain good 2D and 3D pattern fidelity in lithography and etching. This article examines characterization of a detailed 2D layout and creation of a complete model of the lithographic process using design-based metrology (DBM). This model can be used for model-based biasing of the FinFET structure.

Introduction The characterization of fin field effect transistor (FinFET) structures, or other two-dimensional (2D) designs, becomes important with the decreasing sizes in future technologies. Robust measuring methods are therefore needed to characterize the changing shape of the structure during the different process steps. A good metrology approach is also important for the creation of robust simulation models. These models predict how a design will be patterned in resist.

Some typical concerns for FinFETs that need characterization are: the rounded corner (top-down view); fin width variation through pitch and as function of fin length; line edge roughness (LER); and sidewall roughness. They all have an impact on the performance of the FinFET device. The magnitude of the rounded corner decreases the final length (or, source-drain distance) of the FinFET (Figure 1A). One of the problems stemming from this rounding phenomenon is the significant increase in fin width W when the fin length L is decreasing (Figure 1B). Variation in fin width, due to the rounding of the fin open-ing, will impact short channel effects. This effect increases for shorter fin lengths.1

As for most structures, critical dimension (CD) variations through pitch (Figure 1C)

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and as a function of fin length are undesirable, because they render the devices non-reliable.1

Since LER and sidewall roughness have an influence on electrical behavior, it’s also important to control them and keep them as low as possible.2,3 (LER and sidewall roughness will not be addressed in this paper).

Different methods can be used to reduce some of these effects.4 For example, adding serifs in combination with a conventional illumination, or applying strong off-axis illumination settings, like annular, will reduce the rounding of the corners. But, what will happen with the proximity behavior? The annular exposure setting will deteriorate the fin width variation through pitch, while the effect of using conventional illumination on the through pitch behavior will be smaller. Many variables play a role in the optimization of a 2D pattern, some with a larger effect than others. Two simple exposure settings will be tested in this first case: a conventional one and an annular one (the latter in combination with some basic serif introduction).

Since a full characterization of the 2D structure is wanted, design-based metrology (DBM) is introduced to decrease the effort that the creation of the measurement job takes. DBM creates an automatic CD scanning electron micro-scope (SEM) job with hundreds of sites, starting from the design in GDS format. This development takes approxi-mately one hour, whereas an engineer will spend several hours behind the SEM to create the job manually. DBM is used here in combination with an an off-line measure-

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ment tool, enabling image-based measurements on SEM images, to further simplify the process. For two exposure settings, the 2D behavior of the FinFETs is studied intensively to build a resist model that will be used to optimize future reticle designs at IMEC.

Experimental setupAll exposures are performed on an ASML PAS5500/1100 step-and-scan system, interfaced with a TEL Clean Track Act8. Maximum numerical aperture (NA) is 0.75. The total system is charcoal-filtered to prevent airborne base contamination. Top-down CD SEM metrology is done using a KLA-Tencor eCD-2 CD SEM tool.

For the baseline technology integration work (front-end of line (FEOL)), a 193 nm resist from JSR, AR237J at 230 nm film thickness (FT), is used on Brewer Science ARC29a organic bottom anti-reflective coating (BARC), FT = 77 nm. The stack for FinFET patterning (or, the active layer) is 65 nm silicon on 150 nm buried oxide (or, silicon-on-insulator (SOI) stack). A 60 nm TEOS oxide hard-mask (HM) is used during the patterning process for two reasons: to provide etch resistance for the silicon etching and to enable CD (HM) trimming. A binary mask (BIM) is used to print an active pitch of 350 nm; the CD at mask level is 120 nm. The litho target is set at 100 nm. This target is chosen to have acceptable process latitudes (CD control) in litho.

Two different modules are used in the experiments. On the one hand, different actual FinFET devices are explored for a full characterization. On the other hand, regular Mentor Graphics test pattern structures are used to build the resist model. Two parameters in the FinFET device are fixed: the width of the fins and the pitch, 120 nm and 350 nm, respectively (both 1X on reticle). Three other parameters in the FinFET device are varied throughout the experiment. The first one is the length of the fin: the shortest is 180 nm and the longest is 1,45 µm (see Figure 6). The second variable is the bias-ing of the width of the outer fin in a multiple fin struc-ture (see Figure 7). The outer fin width is varied from 90 nm to 150 nm in steps of 10 nm. The last variable is the placement of the serifs (See Table 1 and Figure 8). The size of the serif is in all cases 90 nm by 90 nm. Two kinds of placements are present. In the first, the place-ment consists of the serif symmetric with respect to the corner (called OPC2), i.e. overlap in x- and y-direction is the same. The overlap is 75 nm, meaning that 15 nm of the original design is removed in both directions. In the non-symmetric case (called OPC1), the overlap in y-direction is decreased; 40 nm is removed from the original design.

Two exposure conditions are studied in more detail: a 0.63NA conventional 0.89s and a 0.75NA annular 0.89 outer s and 0.65 inner s.

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Figure1:Theeffectoftheroundedcorner:a)onthelengthoftheFinFET.Illustratedwitha0.63NA,conventional0.89sexposure(upper-left),anda0.75NA,annular0.89outer-sand0.65inner-s(upper-right);b)asafunctionofthedecreasinglengthoftheFinFET;c)duetoproximityeffects,isolatedfeaturesareprintedsmallerthanthedense.IntheFinFETstructure,thisproximityeffectisseenbetweentheinner(dense)andouter(semi-isolated)fins.

OPC0 OPC1 OPC2 No serifs 90 nm X 90 nm 90 nm X 90 nm Non-symmetric Symmetric (with (with respect to respect to the corner) the corner)

Table1:SizesandplacementofserifsontheFinFETdesign.

MethodologyDBM methodologyThe DBM tool used here was developed by KLA-Tencor.5 As input, it requires the GDS of the design and the coordinates of the measurement sites. With the coor-dinates of the sites of interest in the design, the DBM tool creates the pattern recognition templates for each site (Figure 2). The 2D pattern on the clip is compared with the 2D pattern on the wafer until an overlap between the two is found (the pattern recognition).

At this point, the DBM tool has all it needs to create the automatic CD SEM measurement: coordinates of the positions and pattern recognition templates. If a measure- ment is needed, the tool defines by itself which measur-ment algorithm is used. There is also the possibility to acquire SEM images at each site for further analysis, as an off-line measurement on SEM images is available.

The off-line measurement toolKLA-Tencor has developed an off-line measurement tool that enables indirect measurements based on the saved SEM image. Possible measurement algorithms are: minimum or maximum gap width, the rounded corner algorithm, a contact-hole algorithm, and a line-width algorithm. All algorithms can measure multiple struc-tures on an image, as shown in Figure 3. The minimum gap width algorithm is used later in the work to deter-mine the smallest fin width. This approach is preferred because the standard line-width algorithm gives an av-erage value of the line-width in the chosen measurement box. This means that any rounding along the length of the fin is not taken into account. The maximum gap width algorithm is applied to measure the fin length. The rounded corner algorithm determines the magni-tude of the rounding (top-down) of the corners in the FinFET device. Moreover, the goal is to use all these

results to build a first resist model to optimize future FinFET designs.

A useful feature in this off-line measurement tool is the ability to measure several similar sites in batch mode.

Creation of the resist modelThe software package used for the model building in this paper is Calibre WorkBENCH from Mentor Graphics. The 216 sites in the Mentor Graphics line test module are automatically measured by combining the two tools described previously. For every change in exposure set-ting, resist and/or substrate stack, new measurements are needed for the calibration of the model.

First a setup file is created, including the information of exposure setting and substrate. Then a default resist model is used to simulate the 216 sites of interest to compare them with the measured data. Immediately, the Model Flow Tool of Calibre creates a new resist model. A few iterations are needed to define the best agreement. Between two iterations, it is useful to check which sites have a good or bad correlation by using the Model Center of Calibre. The bad ones can be removed if there is doubt on the measured value. Finally, a best-fit resist model is defined.

Results and discussionIn total, 364 sites of interest are defined in the chip design to characterize the 2D behavior of the FinFET and to build the resist model. The CD SEM measurement was made by using the DBM tool since, as indicated before, it takes a lot of time to create the CD SEM measurement parameters manually.

Characterization of the FinFET structureIn this section, the FinFET will be described through discussion on: the rounded corner (top-down view), the fin width versus length, and fin width versus pitch.

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Figure3:a)minimumgap;b)maximumgap;c)roundedcorner.

Figure2:DiagramofDBMtoolcreatingaCDSEMjob.Asinput,onlyadesign

inGDSformatandcoordinatesofthemeasurementsitesareneeded.

Rounded CornerOne of the main concerns with decreasing the size of the fins is the magnitude of the rounded corner, since it has an impact on the effective length and width of the shorter fins. The rounding of the fin is characterized by the difference in area between the edge of the FinFET and the surrounding rectangle. The result for the four corners is added up. This can be done automatically by using the rounded corner algorithm on the off-line measurement tool.

By moving towards off-axis illumination settings such as annular or quasar, the corners become more squared (Figure 1A).4 As noted previously, two exposure condi-tions are used: a 0.63NA, conventional 0.89s and a 0.75NA, annular 0.89/0.65 so/sI. The magnitude of the rounded corners is smaller for the fins shorter than 750 nm when an annular exposure setting is used. This is not the case for the longer fins; both illumination settings give a similar result. The magnitude of the rounding increases with increasing fin length, indepen-dent of the exposure setting (Figure 4). The reason why a larger rounding is observed for the longer fin is that these corners are smoother. They have a longer tail compared to the shorter fins (Figure 5).

Introduction of serifs decreases the magnitude of round-ed corner. This can be seen immediately and visually in Top Down SEM (TD-SEM) (Figure 6). Analysis with the rounded corner algorithm results in the same conclusion (Figure 7). As before, the magnitude of the rounded

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Figure4:ThemagnitudeoftheroundingversusthefinlengthLforOPC0(noserifs

present).Twoexposuresettingsarecompared:a0.63NA,conventional0.89s

anda0.75NA,annular0.89/0.65so/sI.

Figure6:TheFinFETswithandwithoutserifsondesign,onreticleandprintedin

resistwitha0.75NA,annular0.89/0.65so/sIilluminationsetting.

Figure5:Roundingismorepronouncedforthelongerfinsduetoalongertail

fromoneedgecentertotheothercenter.

Figure7:ThemagnitudeoftheroundedcornerversusthefinlengthLforthe

differentOPCversions(a0.75NA,annular0.89/0.65so/sI).

Figure8:ThemagnitudeoftheroundedcornerversusthefinlengthLforOPC1.

Twoexposuresettingsarecompared(0.63NA,conventional0.89sand0.75NA,

annular0.89/0.65so/sI).ThesameeffectisobservedforOPC2.

corners is smaller for the fins shorter than 750 nm when an annular exposure setting is used (Figure 8). But for the longer fins, both exposure settings give the same result when serifs are used, as has been seen when there are no serifs used. The use of off-axis illumination settings, like annular, helps in filtering out the part of the light falling in the NA pupil that is not relevant to the imaging of the densest structures. This improves the contrast, and thus the imaging, of smaller pattern details, like corners.

Width versus length of the finAnother concern is the width variation as a function of varying fin length induced by optical proximity effects. The length and width of the fin can be measured with a standard line/space width CD measurement algorithm or with the newly developed minimum/ maximum gap width algorithm.

Fins with a length below 530 nm are chosen to be checked for fin width variation caused by varying length. The same region will be used to characterize the width variation caused by the difference in pitch, seen in FinFET devices as the width variation between inner (dense) and outer (semi-isolated) fin.

First, the influence of varying length on the width of the fins is checked. The range in width variation in the region of interest (180-530 nm length) is 60 nm for the conventional exposure and 71 nm for the annular exposure (Figure 9). Part of this difference is due to the impact of the rounded corner on the width for shorter fins. The larger range of the annular exposure setting (10 nm) is probably due to the larger proximity effect when an off-axis exposure setting is used.

Comparing the lengths of the fins for the two different exposures shows that for the annular setting the differ-ence with the designed length is smaller.

As previously shown, introduction of serifs has a positive effect on the rounded corners. But how will it influence the width variation induced by the length of the fin? The length of the fin increases when serifs are used in the design. The increase is most pronounced for OPC1 (or, the non-symmetrically placed serifs).

The influence of the serifs on the width variation induced by the length of the fin is large. For example, together with conventional exposure, the width varia-tion caused by the length has completely disappeared in the region of interest (Figure 10). So, this confirms what was stated before, “A part of this width difference is due to the impact of the rounded corner on the width for shorter fins”. In the case of OPC2 (or, symmetrical serifs) in combination with conventional exposure, the shorter fins become even smaller than the longer ones. Also, when annular exposure is used, a large improve-ment is seen (Figure 10), but a width variation of 20 nm is still observed.

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Figure9:Finwidthasfunctionofthedesignedlength(OPC0).Thechangeislarger

for0.75NA,annular0.89/0.65so/sI thanfor0.63NA,conventional0.89s.

Figure10:SmallerproximityeffectforbothOPC1andOPC2,with:a)0.63NA,

conventional0.89s;b)0.75NA,annular0.890.89/0.65so/sI.

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Width versus pitchKnown proximity effects for standard line and space patterns will also play a role here and will become larger when off-axis illumination settings are used. In this paper, the pitch of the FinFET device is fixed at 350 nm, but the proximity effect is seen as a difference between inner and outer fin (Figure 1C). This result can be presented in two ways. The first approach is to plot the fin widths versus length. If the same width on design is used for inner and outer fin, the inner fin is printed larger than the outer fin. This is more pro-nounced for the shorter fins. A second representation is to plot the ratio between inner and outer fin width (Figure 11). In this way, it’s possible to define the best bias needed for the outer fin to print all fins on target (ratio = 1). When using conventional exposure, a bias of 10 nm on the outer fin (an outer fin of 130 nm) is enough to compensate for the optical proximity. When the annular setting is used, a bias of 30 nm is needed to compensate for this effect.

For both exposure settings, the necessary bias is de-creased when serifs are placed. For the conventional exposure, no bias is needed. Also, for the annular set-ting, the bias is decreased to 20 nm bias (an outer fin of 140 nm). The effect for the non-symmetric and symmetric serifs is approximately the same.

Building a resist modelThe combination of DBM with the off-line measurement tool is powerful for characterizing 2D patterns. It is also useful in retrieving the needed measurements for the creation of a resist model. On the used chip design to pattern the FinFET devices, there is also a Mentor Graphics line test pattern available. This pattern con-sists of 216 different sites: isolated lines, dense line patterns, and end-of-line structures (Figure 12). These structures have also been used to build a resist model.

As mentioned before, it is not really user-friendly to define the CD SEM measurement needed for this type of work manually. Thus, the DBM tool is used to automate it. The sites are grouped per similar design, because for most similar sites it is possible to do the analysis with the off-line measurement tool in batch mode. The CD data together with the coordinates and specifications of the sites are put in a data file format, readable as a sample file within Calibre.

Figure11:Ratioofinnerandouterfinwidthversusthedesignedwidthoftheouter

fin:a)0.63NA,conventional0.89s;b)0.75NA,annular0.890.89/0.65so/sI.

Figure12:ExampleofthedifferentpatternsintheMentorGraphicslinetest

module:a)denselines;b)denselineends;c)anisolatedlineend;and

d)aninverselineend.

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Unfortunately, for every change in exposure setting, resist, and substrate stack, new measurements are needed for the recalibration of the model. The fitting is done using the Model Flow Tool and the Model Center Tool of Calibre WorkBENCH, as explained previously. Once a final model is defined, it is verified with the experimental data via two methods: top-down comparison of the model with the SEM image (a visual comparison) and a comparison of the actual measure-ments on wafer with measurement results retrieved from the simulated clips.

As an example, the results for 0.63NA, conventional 0.89s are shown (Figure 13). The correlation between the measured data and the model is 0.976.

The simulated 2D profiles overlap very well with the SEM images. A slight necking is observed on the simu-lated edge contour plots for the longer fins, but it is not present on the SEM images. This overlap illustrates the usefulness of this approach to check the accuracy of a resist model.

As a second check, actual top-down views on wafer are compared with simulated clips. The magnitude of the rounded corner gives similar results for both cases. For the longer fin lengths alone, the magnitude of the rounded corner is slightly smaller on the simulated clips than on the actual CD SEM images. This occurs since the tail (seen before on longer fins, Figure 5) on the simulated clips is not as long as on the real pattern in resist.

The model correlates very well with the actual data and will now be used to optimize future FinFET designs to decrease optical proximity effects.

ConclusionsThe combination of design-based metrology with off-line image-based measurements is a useful tool to describe different parameters of a 2D pattern. The capability for 2D characterization is shown using a FinFET pattern. Rounded corner, width variation, introduction of serifs, biasing, and different exposure settings are the parameters that have been varied to gain an understanding of the patterning behavior of the 2D structure.

A conventional illumination combined with serifs seems to be the best choice for the chosen design (120/350 nm - width/pitch). This exposure condition is beneficial for the decrease in width variation and to provide a less rounded corner. When smaller FinFETs are needed in the future (not only in width, but also in density), an annular setting will give better resolution and a bias will be needed to tackle the proximity effect.

The combination of DBM and off-line image-based measurements is also useful to retrieve the input needed for the creation of a resist model. It is shown that a resist model indeed can predict the patterning in resist (etch is not included in this paper).

AcknowledgmentsThe authors would like to thank Nadine Collaert (IMEC integration) and Ivan Pollentier for their useful discus-sions, as well as the algorithm group at KLA-Tencor for their support.

References1.S.XiongandJ.Bokor,Sensitivityofdouble-gateandFinFET

devices toprocess variations, IEEE Trans. ElectronDev.50(11),p2255-2261,2003.

2. J. Croon et al., Line Edge Roughness: Characterization,Modeling and Impact on Device Behavior, IEDM, ElectronDevicesMeeting,p307-310,2002

3.L.H.A. Leunissenetal.,FullSpectralAnalysisof LineWidthRoughness,SPIE,Vol5752,p499-509,2005

4.M. Ercken et al., Challenges in Patterning 45nm NodeMultiple-GateDevicesandSRAMcells,Interface2004

5.C Bevis “Design driven inspection or measurement forsemiconductorusingrecipe”US6,886,153(2005)

This paper was originally published at INTERFACE 2005, the FUJI FILM Electronic Materials Micro-lithography Symposium.

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