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IBIS Summit, DesignCon 2007

February 1, 2007(rev. 2 February 12, 2007)

Arpad MuranyiSignal Integrity Engineering

Intel Corporationarpad.muranyi@intel.com

Statistical Eye Analysis Implemented in VHDL-AMS

rev. 2

(to accommodate modifications in the code examples)

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Background• A VHDL-AMS implementation of the Peak Distortion Analysis

(PDA) algorithm was demonstrated at the October 2006 IBIS Summit in Tokyo, and at the 2006 IEEE International Behavioral Modeling and Simulation Conference (BMAS):

http://www.vhdl.org/pub/ibis/summits/oct06b/muranyi.pdfhttp://www.bmas-conf.org/2006/4.7_presentation.pdfhttp://www.bmas-conf.org/2006/4.7_project.zip

• PDA predicts the worst eye opening, but– what is the probability of getting an eye that size (or any other size)?– i.e. what is the bit error rate (BER) of a certain channel?

• Numerous statistical methods have been developed by companies– mostly in C, Matlab, or other proprietary languages– a well known and publicly available package is “StatEye”:

http://www.stateye.org/index.php– these solutions do not work in commonly used signal integrity (SI) tools– models from multiple vendors may not work together in the same channel design

• The challenge is to bring these algorithms to the familiar signal integrity (SI) tools and to make high speed SERDES driver and receiver modeling possible in a standardized format (IBIS)

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Purpose

• Show that statistical eye and BER algorithms can be implemented very well using the VHDL-AMS (or Verilog*-AMS) languages

• Some of the advantages of using *-AMS:– VHDL-AMS and Verilog*-AMS are standardized languages– the IBIS standard (v4.1 and higher) has links to both languages– there are several simulators which support them already– Tx and Rx models from different vendors would work together

• However, *-AMS modeling is not gaining popularity very fast in the SI community

• The purpose of this presentation is to encourage *-AMS modeling and to help model makers and users to get started

• Although this presentation demonstrates a working model, its goal is not to provide a complete solution

– the purpose is to show the concepts only– i.e. it may have bugs

• Currently implemented in VHDL-AMS only

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The simulation setup

• The top level test circuit is the same as the one used in the previous PDA algorithm presentation

– both implementations are based on a pulse response– the function of the top level circuit is to generate that pulse response,

consisting of:

• a Thevenin “driver” using a pulse voltage source and a resistor• an ideal T-line• a series inductor• a capacitor acting as a “receiver”

– schematics and details are shown on the next page

• For this study I didn’t care whether the channel circuit was realistic or not, as long as it gave a reasonable pulse response

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Schematics of the simulated circuit

Pulse: 1 V, 200 ps wide, 1 ps edgeR1: 100 ΩΩΩΩT-line: 100 ΩΩΩΩ, 0.5 ns, losslessL1: 10 nHC1: 1 pF

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Overview of the operation of the model

• A normal time domain simulation is started– the first 3 ns of the simulation generates the pulse response– the 3000 points of the pulse response waveform are stored in a “real_vector”– a 1 ps fixed time step is used for simplicity– a 200 ps pulse width is used which yields a 200 ps wide eye (200 points)– these are all parameters which can be changed in the top level circuit

• The simulation is continued for another 200 ps to perform the “analysis” and plot the eye

– the functions of the algorithm are executed at each of these iterations– 200 vertical eye slices (probability density function vs. voltage) are calculated– the raw data is printed into a file (in Matlab format) for 3D plotting– a family of eye contours are generated for 2D plotting in the simulator– (the innermost eye contour is identical to the worst eye obtained with PDA)

– the statistical algorithm uses only the digital engine (very fast)– the analog engine is only used to generate the pulse response and to plot the

results from the digital engine

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Flow - top level circuits

• Test bench– the circuit shown on the schematics– these are located in the files StatEye.nsx and IBIS_StatEye_library.vhd

• The receiver model, C_StatEye contains three VHDL-AMS architectures

– “ideal”, a simple capacitor model– “StatEye_on”, a capacitor model with processes to activate the algorithm– “StatEye_off”, a capacitor model with processes that pretend to activate

the algorithm but don’t (for more reasonable benchmarking)

• The two processes in C_StatEye– “GetCursorIndex”, locates the peak of the pulse response waveform

which is assumed to coincide with the center of the eye (in time)– “Ticker”, saves the points of the pulse response waveform during the first

3 ns of the TD simulation at a 1 ps time interval (a total of 3000 points)– after 3 ns, it calls the MakeEyeContours function 200 times at 1 ps

intervals (determined by the pulse width which is 200 ps in this study)– MakeEyeContours and all of its associated functions make up the statistical

eye algorithm and are located in the file “StatEye_functions.vhd”

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Flow - functions

• MakeEyeContours– partitions the pulse response waveform into windows of size BitWidth and passes an

array of one sample from each of these windows into the function called Convolve

• Convolve– convolves all of the pre/post cursor samples to generate the probability distribution

function (PDF) of the inter symbol interference (ISI) only– calls the MakeCPDF function

• MakeCPDF– combines the logic 1 and 0 cursors with the ISI PDF– generates the cumulative probability distribution functions (CPDF) by integration– generates the eye contours for 2D plotting in the simulator– calls the Make3Dfile function to save the CPDF data to a file

• Make3Dfile– generates the Matlab syntax for a cell array containing the data and writes it to a file

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Pulse response and statistical eye contours

V(PLS)V(RCV)

X1.C1.EYEWFM[1][1]X1.C1.EYEWFM[1][2]X1.C1.EYEWFM[2][1]X1.C1.EYEWFM[2][2]X1.C1.EYEWFM[3][1]X1.C1.EYEWFM[3][2]X1.C1.EYEWFM[4][1]X1.C1.EYEWFM[4][2]X1.C1.EYEWFM[5][1]X1.C1.EYEWFM[5][2]X1.C1.EYEWFM[6][1]X1.C1.EYEWFM[6][2]X1.C1.EYEWFM[7][1]X1.C1.EYEWFM[7][2]X1.C1.EYEWFM[8][1]X1.C1.EYEWFM[8][2]X1.C1.EYEWFM[9][1]X1.C1.EYEWFM[9][2]X1.C1.EYEWFM[10][1]

200p 400p 600p 800p 1n 1.2n 1.4n 1.6n 1.8n 2n 2.2n 2.4n 2.6n 2.8n 3n 3.2n

-200mV

-100mV

0V

100mV

200mV

300mV

400mV

500mV

600mV

700mV

800mV

900mV

1V

-200mV-100mV0V100mV200mV300mV400mV500mV600mV700mV800mV900mV1V1.1V1.2V

Pulse response (TD simulation)

Statistical eye contours for selected BER values

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Statistical eye contours (zoomed in)

BER:0.00.050.10.150.20.250.30.350.40.450.5

X1.C1.EYEWFM[1][1]X1.C1.EYEWFM[1][2]X1.C1.EYEWFM[2][1]X1.C1.EYEWFM[2][2]X1.C1.EYEWFM[3][1]X1.C1.EYEWFM[3][2]X1.C1.EYEWFM[4][1]X1.C1.EYEWFM[4][2]X1.C1.EYEWFM[5][1]X1.C1.EYEWFM[5][2]X1.C1.EYEWFM[6][1]X1.C1.EYEWFM[6][2]X1.C1.EYEWFM[7][1]X1.C1.EYEWFM[7][2]X1.C1.EYEWFM[8][1]X1.C1.EYEWFM[8][2]X1.C1.EYEWFM[9][1]X1.C1.EYEWFM[9][2]X1.C1.EYEWFM[10][1]X1.C1.EYEWFM[10][2]X1.C1.EYEWFM[11][1]X1.C1.EYEWFM[11][2]

2.99n 3n 3.01n 3.02n 3.03n 3.04n 3.05n 3.06n 3.07n 3.08n 3.09n 3.1n 3.11n 3.12n 3.13n 3.14n 3.15n 3.16n 3.17n 3.18n 3.19n 3.2n

-300mV

-200mV

-100mV

0V

100mV

200mV

300mV

400mV

500mV

600mV

700mV

800mV

900mV

1V

1.1V

1.2V

The Rx model has an array parameter (BERvalues) through which the user can request which and how many eye contours should be plotted.

Each contour corresponds to a certain BER.

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3D plot of the data generated by the VHDL-AMS code

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A simulation statistics example

Algorithm: ON with file write no file write OFF---------------------------------------------------------------Transient: CPU time spent in:

- device evaluations : 79.5 % (4s 983ms)- factorizations : 3.5 % (220ms)- resolutions : 0.3 % (19ms)- convergence checks : 0.5 % (29ms)- logic kernel solve : 0.2 % (9ms)- logic generated processes : 1.9 % (119ms)- logic generated memory allocations : 5.3 % (329ms)- waveform display : 1.1 % (69ms)- other routines : 7.7 % (483ms)

- total : 100.0 % (6s 268ms)---------------------------------------------------------------

---------------------------------------------------------------Transient: CPU time spent in:

- device evaluations : 76.0 % (4s 826ms)- factorizations : 2.8 % (179ms)- resolutions : 0.5 % (29ms)- convergence checks : 0.3 % (19ms)

- logic generated processes : 4.7 % (300ms)- logic generated memory allocations : 6.6 % (420ms)- waveform display : 1.4 % (89ms)- other routines : 7.6 % (479ms)

- total : 100.0 % (6s 348ms)---------------------------------------------------------------

---------------------------------------------------------------Transient: CPU time spent in:

- device evaluations : 70.0 % (5s 348ms)- factorizations : 2.6 % (200ms)- resolutions : 0.1 % (9ms)- convergence checks : 0.4 % (29ms)- logic kernel solve :- logic generated processes : 11.3 % (859ms)- logic generated memory allocations : 6.4 % (489ms)- waveform display : 1.4 % (109ms)- other routines : 7.7 % (590ms)

- total : 100.0 % (7s 640ms)---------------------------------------------------------------

analog

digital

• These numbers show that writing to the file takes the most time• The statistical eye algorithm raises the CPU time of the digital

engine, but it is very fast (adds only 181 ms)• It takes more time to simulate the analog circuit than calculating

the statistical eye probability distribution functions

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Summary and future work

• This experiment implemented only the basic algorithms of statistical eye analysis

– source: “Channel Compliance Testing Utilizing Novel Statistical Eye Methodology”, DesignCon 2004, by Anthony Sanders, Infineon Technologies

http://www.stateye.org/downloads/channel_compliance.pdf(see section “Theoretical Analysis of Receiver Pulse Response”)

– cross talk is not included• need to add coupled T-lines and do more convolutions

– jitter is not included• more sophisticated stimulus and/or processing algorithms may be needed

• A 3000 point pulse response and a 200 point pulse width– 14 sampling windows convolved and post processed 200 times in about seven

seconds (on a 1.8 GHz laptop)– additional code optimizations could probably reduce the CPU time more

• Future work may include– implement the same in Verilog-A(MS)– implement similar (equivalent) algorithms in the frequency domain

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A working VHDL-AMS code example is provided in the

WinZIP file associated with this presentation.