straw3 top page 1idlab/project_files/salt/docs/straw3schematics.pdfvin16 vin16 vref1 vref2 vref3...
TRANSCRIPT
ADC12
ANAINPUT
CLK
CLR
CMPbias D0
D1D2
D3D4
D5D6
D7D8
D9D10
D11
DACspy
EOC
FCspy
Page 50
START
Analog
Bufferin
Page 88Super
Vbias
(core storage and encoding)
ATdat0ATdat1ATdat2ATdat3ATdat4ATdat5ATdat6ATdat7ATdat8ATdat9
ATdat10ATdat11ATdat12ATdat13ATdat14ATdat15
Cena
core
DAoutDCLKDIN
Hitbus
ICbias
LLsum
nREGclr
nRUN
nSaD
OBUS
Page 2
PosNeg
RCO
RESET
ROVDDS0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S1
0
S11
S0b
S10b
S11b
S1b
S2b
S3b
S4b
S5b
S6b
S7b
S8b
S9b
SCLK
Tspy
Vbias
Vbs
Vgref1
Vgref2
Vgref3
Vgref4
Vgref5
Vgref6
Vgref7
Vgref8
Vgref9
Vgref10
Vgref11
Vgref12
Vgref13
Vgref14
Vgref15
Vgref16
Vin1
Vin2
Vin3
Vin4
Vin5
Vin6
Vin7
Vin8
Vin9
Vin10
Vin11
Vin12
Vin13
Vin14
Vin15
Vin16
VMbias
VTbias
ANALoutCAL
DAout
ESS0
GAINblock
GTMclk
GTMin
GTMout
nGTRclr
ObusPage 69
GTMclk
GTMin
GTMout
LLout
LLtrig
MLU_block
nREGclr
Page 7
Tbias
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15
B0B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MUX32:16
Page 177SEL
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadVdd
Page 204
PadVdd
Page 204
PadVdd
Page 204
PadVdd
Page 204
PadVdd
Page 204
PadVddPage 204
PadVddPage 204
PadVddPage 204
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Module:top Page:Page0
Designer:Gary S. Varner, PhD
Info:SCA designModified:Sep 7, 2003 20:28:33Created:Jun 26, 2000 17:26:36
(RCCNTR)
12-bitAddr/Sel Counter
nACrst
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
nQ10
nQ11
Page 65
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10
Q11
SPAR
Tspy
STRAW3
FCspy
DACspy
REGclr
nGTRclr
GTRclr
eTspy
xTspy
nREGclr
GTMoutADT12ADT11ADT10ADT9ADT8ADT7ADT6ADT5ADT4ADT3ADT2ADT1ADT0
GTMmid
PosNegHitbus
DAout
AObus
DAT15
DAT14
DAT13
DAT12
DAT11
DAT10
DAT9
DAT8
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
nREGclr
LLsum
LLtrig
ANALin
43
SPAR
nSPAR
eSPAR
nESS0
ESS0
eESS0
81
ESS0
Tspy
CAL
nGTRclr
83
TRGbias
GND84
84
VDD80
80
nGTMclk
GTMclk
eGTMclk
nGTMsin
GTMsin
eGTMsin
86 8587nRUN
RUN
enRUN
nADCclr
ADCclr
eADCclr
79
78
CMPbias
nADCstart
ADCstart
eADCstart
77ADCclk nA
DCclk
eADCclk
76
88
94DIN
nDIN
GND95
95
eDIN
93SCLK
nSCLK
eSCLK
92
VDD92
91DCLK
nDCLK
eDCLK
90
VDD90
eGTRclr
44
46
CAL
ISbias
Aout
VDD49
4948
47
5045
GND45
40
nCena
Cena
xRESET
RESET
eRESET
eCena
42
41
Page 8PadRing
36
VTbias
35
Vbias
34
GND34
33
ICbias
32
VMbias
nSaD
CAL
RCO
RCOROVDD
ROVDD
STRAW3 Page 1
Vbs
96979899
Vrf1
Vin1
Vrf2
Vin2
InGNDtop
82100
ACrst
nACrst
ACclk
nACclk
3938
37
eACclk
eACrst
Vrf16
Vin16
Vin15
InGNDbot
Vrf15
31
30292827
26
VDD31 GN
D41
VDD37
67
64
nDnADnA
nSaDSaD
59
58
57
eDAT15
eDAT14
eDAT13
eDAT12
eDAT11
eDAT1
eDAT0
eDAT2
65
eDAT3
eDAT4
eDAT5
eDAT6
eDAT7
eRCO
eDAT10
eDnA
eSaD
VDD60
eDAT8
eDAT9
ROVDD
53
56
55
60
51 GND51
61
6263 GND63
68
69
70
66 GND66
71
72
73
54
75
52
74VDD75
Vrf11
Vin12Vrf12
Vin13
Vin6Vrf6
Vin7Vrf7
Vin8Vrf8
InGNDmid
Vin9Vrf9
Vin10Vrf10
Vin11
Vrf3
Vrf14Vin14
Vrf13
Vin4Vrf4
Vin5Vrf5
Vin3
1718
1920
5
67
89
1011
12
1314
1516
25
2423
2221
1
23
4
top(top level sheet)
Page 1
eLLTrig
BDT15BDT14BDT13BDT12BDT11BDT10BDT9BDT8BDT7BDT6BDT5BDT4BDT3BDT2BDT1BDT0
S0 S0b
S1 S1b
S2 S2b
S3 S3b
S4 S4b
S5 S5b
S6 S6b
S7 S7b
S8 S8b
S9 S9b
S10
S10b
S11
S11b
eREGclr
89
Created:Jun 26, 2000 17:26:36Modified:Sep 7, 2003 20:28:33
Info:SCA design
Designer:Gary S. Varner, PhD
Page:Page0Module:top
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Column(Col_left_bank)
Left Bank
Page 33
Vgref1
Vgref2
Vgref3
Vgref4
Vgref5
Vgref6
Vgref7
Vgref8
Vgref9
Vgref10
Vgref11
Vgref12
Vgref13
Vgref14
Vgref15
Vgref16
Vin1Vin1
Vin2 Vin2
Vin3 Vin3
Vin4Vin4
Vin5Vin5
Vin6 Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13 Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
Vref1
Vref2
Vref3
Vref4
Vref5
Vref6
Vref7
Vref8
Vref9
Vref10
Vref11
Vref12
Vref13
Vref14
Vref15
Vref16
(Comparator Banks, LL Storage and Output Select)
Cena
CompDACS
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
DAout
DCLK
DIN Dout
HLout
ICbias
LLsum
nREGclr
Page 6
RESET
S0 S1 S2 S3 S4 S5 S6S0b
S1b
S2b
S3b
S4b
S5b
S6b
SCLK
Tspy
Vbias
Vbs
Vin1
Vin2
Vin3
Vin4
Vin5
Vin6
Vin7
Vin8
Vin9
Vin10
Vin11
Vin12
Vin13
Vin14
Vin15
Vin16
VMbias
Vref1
Vref2
Vref3
Vref4
Vref5
Vref6
Vref7
Vref8
Vref9
Vref10
Vref11
Vref12
Vref13
Vref14
Vref15
Vref16
VTbias
Include models
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15
B0B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MUX32:16
Page 177SEL
CS0
CS1
CS2
CS3
CS0b
CS1b
CS2b
CS3b
Iout1
Iout2
Iout3
Iout4
Iout5
Iout6
Iout7
Iout8
Iout9
Iout10
Iout11
Iout12
Iout13
Iout14
Iout15
Iout16
Obus
out_blockPage 45
Vin1Vin1
Vin2 Vin2
Vin3Vin3
Vin4 Vin4
Vin5Vin5
Vin6 Vin6
Vin7Vin7
Vin8 Vin8
Vin9Vin9
Vin10 Vin10
Vin11Vin11
Vin12 Vin12
Vin13Vin13
Vin14 Vin14
Vin15Vin15
Vin16 Vin16
Vref1Vref1
Vref2Vref2
Vref3Vref3
Vref4Vref4
Vref5Vref5
Vref6Vref6
Vref7Vref7
Vref8Vref8
Vref9Vref9
Vref10Vref10
Vref11Vref11
Vref12Vref12
Vref13Vref13
Vref14Vref14
Vref15Vref15
Vref16Vref16
Created:May 5, 1993 21:36:43
Designer:Gary S. Varner, PhD
Info:Core Logic buildModified:Sep 5, 2003 13:14:14
Module:core Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
1 1
2 2
3 3
4 4
5 5
6 6
77
8 8
99
1010
11 11
12 12
1313
1414
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: B
Column
(sca_bank256_col)
Bank of 256
Hitbus
Iout1
Iout2
Iout3
Iout4
Iout5
Iout6
Iout7
Iout8
Iout9
Iout10
Iout11
Iout12
Iout13
Iout14
Iout15
Iout16
nRUN
Page 18
PosNeg
RCO
ROVDD
S0
S1
S2
S3
S4
S5
S6
S7
S0b
S1b
S2b
S3b
S4b
S5b
S6b
S7b
Storage
Vin1Vin1
Vin2 Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
Vref1Vref1
Vref2Vref2
Vref3Vref3
Vref4Vref4
Vref5Vref5
Vref6Vref6
Vref7Vref7
Vref8Vref8
Vref9Vref9
Vref10Vref10
Vref11Vref11
Vref12Vref12
Vref13Vref13
Vref14Vref14
Vref15Vref15
Vref16Vref16
Tspy
HLout
HLout
nREGclr
Hitbus
PosNeg
nSaD
S11S10S9S8S7S6S5S4S3
Dout
S2S1S0
Dout
Hitbus
S9S9b
S8bS8
S11S11b
S10bS10
S5 S5b
S4bS4 S6bS6S1 S1b
S0bS0 S3 S3b
S2bS2
RESET
Cena
DCLKSCLK
DAout
Vbs
DIN
PosNeg
Vgref2
Vgref1
Vgref3
Vgref4
Vgref5
Vgref6
Vgref7
Vgref8
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
RCOROVDD
Vbias
ICbias
VMbias
VTbias
LLsum
ATdat15
ATdat14
ATdat13
ATdat12
ATdat11
ATdat10
ATdat9
ATdat8
ATdat7
ATdat6
ATdat5
ATdat4
ATdat3
ATdat2
Vin1
ATdat1
ATdat0
CORE block (core)
Page 2
nRUN
Obus
S5S5b
S4bS4
S7S7b
S6bS6 S1
S1b
S0bS0
S3S3b
S2bS2
Vgref13
Vgref12
Vgref11
Vgref10
Vgref9
Vgref16
Vgref15
Vgref14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin16
Vin15
Vin14
.param l=0.12u
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:core
Modified:Sep 5, 2003 13:14:14Info:Core Logic build
Designer:Gary S. Varner, PhD
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: B
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
AObus
CS0 CS1 CS2 CS3 CS4 CS5CS0b CS1b CS2b CS3b CS4b CS5b
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
DAC8
DAC9
DAC10
DAC11
DAC12
DAC13
DAC14
DAC15
DAC16
DAC17
DAC18
DAC19
DAC20
DAC21
DAC22
DAC23
DAC24
DAC25
DAC26
DAC27
DAC28
DAC29
DAC30
DAC31
DAC32
DAC33
DAC34
DAC35
DAC36
DAC37
DAC38
DAC39
DAC40
DAC41
DAC42
DAC43
DAC44
DAC45
DAC46
DAC47
DAC48
DAC49
DAC50
DAC51
DAC52
DAC53
DAC54
DAC55
DAC56
DAC57
DAC58
DAC59
DAC60
DAC61
DAC62
DAC63
DAC64
DACAMUX_Block
Page 9
(Discrim_hl_oct
An octal of Disrim. Ch.
HHH1
HHH2
HHH3
HHH4
HHH5
HHH6
HHH7
HHH8
HHL1
HHL2
HHL3
HHL4
HHL5
HHL6
HHL7
HHL8
HHT1HHT2HHT3HHT4
HHT5HHT6HHT7HHT8
HLH1
HLH2
HLH3
HLH4
HLH5
HLH6
HLH7
HLH8
HLL1
HLL2
HLL3
HLL4
HLL5
HLL6
HLL7
HLL8
HLout
HLT1HLT2HLT3HLT4
HLT5HLT6HLT7HLT8
ICbias
ICbias
LHT1LHT2LHT3LHT4
LHT5LHT6LHT7LHT8
LLsum
LLsum
LLT1LLT2LLT3LLT4
LLT5LLT6LLT7LLT8
Page 199
Vbias
Vbias Vbs
Vbs
Vin1
Vin2
Vin3
Vin4
Vin5
Vin6
Vin7
Vin8
Vref1
Vref2
Vref3
Vref4
Vref5
Vref6
Vref7
Vref8
VTbias
VTbias
(Discrim_hl_oct
An octal of Disrim. Ch.
HHH1
HHH2
HHH3
HHH4
HHH5
HHH6
HHH7
HHH8
HHL1
HHL2
HHL3
HHL4
HHL5
HHL6
HHL7
HHL8
HHT1HHT2HHT3HHT4
HHT5HHT6HHT7HHT8
HLH1
HLH2
HLH3
HLH4
HLH5
HLH6
HLH7
HLH8
HLL1
HLL2
HLL3
HLL4
HLL5
HLL6
HLL7
HLL8
HLout
HLT1HLT2HLT3HLT4
HLT5HLT6HLT7HLT8
ICbias
ICbias
LHT1LHT2LHT3LHT4
LHT5LHT6LHT7LHT8
LLsum
LLsum
LLT1LLT2LLT3LLT4
LLT5LLT6LLT7LLT8
Page 199
Vbias
Vbias Vbs
Vbs
Vin1
Vin2
Vin3
Vin4
Vin5
Vin6
Vin7
Vin8
Vref1
Vref2
Vref3
Vref4
Vref5
Vref6
Vref7
Vref8
VTbias
VTbias
Include models
pg.101
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15
B0B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MUX32:16
Page 177SEL
Page 103
L='12*l'T1W='30*l'
L='12*l'T2W='30*l'
L='12*l'T3 W='30*l'
L='12*l'T4 W='30*l'
Created:May 5, 1993 21:36:43
Designer:Gary S. Varner
Info:Single I-measure channel (ichannel)Modified:Sep 4, 2003 14:18:05
Module:CompDACS Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
1 1
2 2
3 3
4 4
5 5
6 6
77
8 8
99
1010
11 11
12 12
1313
1414
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: B
Cena
CenaCLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
CLK16
Page 49
Q0Q0 Q1
Q1 Q2Q2 Q3
Q3 Q4Q4 Q5
Q5 Q6Q6 Q7
Q7 Q8Q8 Q9
Q9 Q10
Q10
Q11
Q11
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
RESET
RESET
S0S0S0S0
S1S1
S2S2 S3
S3
S4S4
S0b
S0b
S0b
S0b
S1b
S1b
S2b
S2b
S3b
S3b
S4b
S4b
Scaler_Block16SELA
SELB
Cena
CenaCLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
CLK16
Page 49
Q0Q0 Q1
Q1 Q2Q2 Q3
Q3 Q4Q4 Q5
Q5 Q6Q6 Q7
Q7 Q8Q8 Q9
Q9 Q10
Q10
Q11
Q11
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
RESET
RESET
S0S0S0S0
S1S1
S2S2 S3
S3
S4S4
S0b
S0b
S0b
S0b
S1b
S1b
S2b
S2b
S3b
S3b
S4b
S4b
Scaler_Block16SELA
SELB
Cena
CenaCLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
CLK16
Page 49
Q0Q0 Q1
Q1 Q2Q2 Q3
Q3 Q4Q4 Q5
Q5 Q6Q6 Q7
Q7 Q8Q8 Q9
Q9 Q10
Q10
Q11
Q11
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
RESET
RESET
S0S0S0S0
S1S1
S2S2 S3
S3
S4S4
S0b
S0b
S0b
S0b
S1b
S1b
S2b
S2b
S3b
S3b
S4b
S4b
Scaler_Block16SELA
SELB
Cena
CenaCLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
CLK16
Page 49
Q0Q0 Q1
Q1 Q2Q2 Q3
Q3 Q4Q4 Q5
Q5 Q6Q6 Q7
Q7 Q8Q8 Q9
Q9 Q10
Q10
Q11
Q11
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
RESET
RESET
S0S0S0S0
S1S1
S2S2 S3
S3
S4S4
S0b
S0b
S0b
S0b
S1b
S1b
S2b
S2b
S3b
S3b
S4b
S4b
Scaler_Block16SELA
SELB
DCLK
DCLK
DIN
Dout
nREGclr
nREGclr
Page 78
SCLK
SCLK
Serial Super DAC 16
SS_DAC16
Vbias
Vbias Vout1
Vout2Vout3Vout4
Vout5Vout6Vout7Vout8
Vout9Vout10Vout11Vout12
Vout13Vout14Vout15Vout16
DCLK
DCLK
DIN
Dout
nREGclr
nREGclr
Page 78
SCLK
SCLK
Serial Super DAC 16
SS_DAC16
Vbias
Vbias Vout1
Vout2Vout3Vout4
Vout5Vout6Vout7Vout8
Vout9Vout10Vout11Vout12
Vout13Vout14Vout15Vout16
DCLK
DCLK
DIN
Dout
nREGclr
nREGclr
Page 78
SCLK
SCLK
Serial Super DAC 16
SS_DAC16
Vbias
Vbias Vout1
Vout2Vout3Vout4
Vout5Vout6Vout7Vout8
Vout9Vout10Vout11Vout12
Vout13Vout14Vout15Vout16
DCLK
DCLK
DIN
Dout
nREGclr
nREGclr
Page 78
SCLK
SCLK
Serial Super DAC 16
SS_DAC16
Vbias
Vbias Vout1
Vout2Vout3Vout4
Vout5Vout6Vout7Vout8
Vout9Vout10Vout11Vout12
Vout13Vout14Vout15Vout16
TM16TM15TM14TM13TM12TM11TM10TM9TM8TM7TM6TM5TM4TM3TM2TM1
Tspy
SD15SD14SD13SD12SD11SD10SD9SD8SD7SD6SD5SD4SD3SD2SD1SD0
DAC4
DAC3
DAC2
DAC1
LLsum
VTbiasVbs
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
RESET
VTbias
DAout
Vbias
Vbs
ICbias Vbias
VMbias
DCLK
SCLK
Cena
RESET S0 S0b S1 S1b S2 S2b S3 S3b S4
Dout
ICbias
DCLK
SCLK
DIN
S4b
S6
S5
S6
S5b
S6b
S5
S6b
S5b
S5bS5S4bS4S3bS3S2bS2S1bS1S0bS0
S4b
S4S3b
S3S2b
S2S1b
S1S0b
S0
Comparator+DAC+Scalers (CompDACS)
HLout
Vin1 Cena
LLsum
VMbias
Vref1
Vin2Vref2
Vin3Vref3
Vin4Vref4
Vin5Vref5
Vin6Vref6
Vin7Vref7
Vin8Vref8
Vin9Vref9
Vin10Vref10
Vin11Vref11
Vin12Vref12
Vin13Vref13
Vin14Vref14
Vin15Vref15
Vin16Vref16
DAC9
DAC8
DAC7
DAC6
DAC5
DAC10
DAC11
DAC12
DAC13
DAC14
DAC15
DAC16
DAC17
DAC18
DAC19
DAC20
DAC21
DAC22
DAC23
DAC24
DAC25
DAC26
DAC27
DAC28
DAC29
DAC30
DAC31
DAC32
DAC33
DAC34
DAC35
DAC36
DAC37
DAC38
DAC39
DAC40
DAC41
DAC42
DAC43
DAC44
DAC45
DAC46
DAC47
DAC48
DAC49
DAC50
DAC51
DAC52
DAC53
DAC54
DAC55
DAC56
DAC57
DAC58
DAC59
DAC60
DAC61
DAC62
DAC63
DAC64
Dmid
HLout1
HLout2
scc1scc2scc3scc4
scc5scc6scc7scc8
scc9scc10scc11scc12
scc13scc14scc15scc16
scc17TM1scc19TM2
scc21TM3scc23TM4
scc25TM5scc27TM6
scc29TM7scc31TM8
scc33scc34scc35scc36
scc37scc38scc39scc40
scc41scc42scc43scc44
scc45scc46scc47scc48
scc49TM9scc51TM10
scc53TM11scc55TM12
scc57TM13scc59TM14
scc61TM15scc63TM16
nREGclr
nREGclr
SCA Page 6
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D13
D14
D15
.param l=0.12u
W='30*l' T1L='12*l'
W='30*l' T2L='12*l'
W='30*l'T3L='12*l'
W='30*l'T4L='12*l'
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:CompDACS
Modified:Sep 4, 2003 14:18:05Info:Single I-measure channel (ichannel)
Designer:Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: B
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
Include models
IRou
t
LLou
t
LLtr
ig MLU
Page 67Tb
ias
IRou
t
MLU0
MLU1
MLU2
MLU3
MLU4
MLU_R Page 66
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner, PhD
Path:C:\CustomIC\STRAW3\STRAW3
Rev AInfo:MLU Trigger
Module:MLU_block Page:Page0
Modified:Sep 4, 2003 11:20:25Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
nREGclr
G3G2G1G0LL
trig
LLou
tTb
ias
Majority Logic Unit (MLU) Block
STRAW3 Page 7
GTMout
GTMoutG4b
G3G0 G2 G3G3b
G2G2b
G1G0b
GTMin
GTMclk
G1G1b
G0
.param l=0.12u
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 4, 2003 11:20:25
Page:Page0Module:MLU_block
Info:MLU Trigger Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner, PhD
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadARef
Page 201
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndNCPage 213
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadGndPage 203
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadHFpair
Page 208
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadInC_SCMOS
Page 202
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadOut
Page 205
PadVdd
Page 204
PadVdd
Page 204
PadVdd
Page 204
PadVdd
Page 204
PadVddPage 204
PadVdd
Page 204
PadVddPage 204
PadVddPage 204
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Module:PadRing Page:Page0
Designer:Gary S. Varner
Info:STRAW2 Bonding Pad SchematicModified:Sep 6, 2003 08:00:08Created:Jun 26, 2000 17:26:36
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
REGclr
nREGclr
eREGclr
89
96979899
Vrf1
Vin1
Vrf2
Vin2
Vrf16
Vin16
Vin15
Vrf15 30292827
nGTRclr
GTRclr
eTspy
xTspy
Tspy
CAL
eGTRclr
44
46
CAL
ISbias
Aout
VDD49
4948
47
5045
GND45
ADCclr
GTMsin
43
SPAR
nSPAR
eSPAR
40
nCena
Cena
nRESET
RESET
eRESET
eCena
42
41
GND41
ESS084
nADCclr
eADCclr
79
nESS0
eESS0
81
83
TRGbias
GND84
VDD80
nGTMclk
eGTMclk
85
Vbs
82
nGTMsin
GTMclk
eGTMsin
8687nRUN
RUN
enRUN
78
CMPbias
nADCstart
ADCstart
eADCstart
77ADCclk
nADCclk
eADCclk
76
88
94DIN
nDIN
GND95
95
eDIN
93SCLK
nSCLK
eSCLK
92
VDD92
91DCLK
nDCLK
eDCLK
90
VDD90
36
VTbias
35
Vbias
34
GND34
33
ICbias
32
VMbias
RCO
ROVDD
InGNDtop
100
ACrst
nACrst
ACclk
nACclk
3938
37
eACclk
eACrst
InGNDbot
3126
VDD31 VD
D37
67
64
nDnADnA
nSaDSaD
59
58
57
eDAT15
eDAT14
eDAT13
eDAT12
eDAT11
eDAT1
eDAT0
eDAT2
65
eDAT3
eDAT4
eDAT5
eDAT6
eDAT7
eRCO
eDAT10
eDnA
eSaD
VDD60
eDAT8
eDAT9
ROVDD
53
56
55
60
51 GND51
61
6263 GND63
68
69
70
66 GND66
71
72
73
54
75
52
74VDD75
Vrf11
Vin12Vrf12
Vin13
Vin6Vrf6
Vin7Vrf7
Vin8Vrf8
InGNDmid
Vin9Vrf9
Vin10Vrf10
Vin11
Vrf3
Vrf14Vin14
Vrf13
Vin4Vrf4
Vin5Vrf5
Vin3
1718
1920
5
67
89
1011
12
1314
1516
25
2423
2221
1
23
4
eLLTrig
Page 8(Pad Ring definition)
PadRingSTRAW2
.param l=0.12u
Created:Jun 26, 2000 17:26:36Modified:Sep 6, 2003 08:00:08
Info:STRAW2 Bonding Pad Schematic
Designer:Gary S. Varner
Page:Page0Module:PadRing
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
CS0 CS1 CS2 CS3 CS4CS0b CS1b CS2b CS3b CS4b
DACAMUX_32
DACin1
DACin2
DACin3
DACin4
DACin5
DACin6
DACin7
DACin8
DACin9
DACin10
DACin11
DACin12
DACin13
DACin14
DACin15
DACin16
DACin17
DACin18
DACin19
DACin20
DACin21
DACin22
DACin23
DACin24
DACin25
DACin26
DACin27
DACin28
DACin29
DACin30
DACin31
DACin32
Obus
Page 145
CS0 CS1 CS2 CS3 CS4CS0b CS1b CS2b CS3b CS4b
DACAMUX_32
DACin1
DACin2
DACin3
DACin4
DACin5
DACin6
DACin7
DACin8
DACin9
DACin10
DACin11
DACin12
DACin13
DACin14
DACin15
DACin16
DACin17
DACin18
DACin19
DACin20
DACin21
DACin22
DACin23
DACin24
DACin25
DACin26
DACin27
DACin28
DACin29
DACin30
DACin31
DACin32
Obus
Page 145
DACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0b
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:Analog MUX for DAC monitoringModified:Oct 23, 2002 06:54:50
Module:DACAMUX_block Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
DACin4DACin3DACin2DACin1
STRAW2 Page 9
DAC Analog Mux Block [64-Ch.] (DACAMUX_Block)
AObus
DACin8DACin7DACin6DACin5
CS5bCS5
DACin12DACin11
CS0bCS0
DACin10DACin9
DACin16DACin15DACin14DACin13
CS1bCS1
CS2bCS2
CS3bCS3
DACin20DACin19DACin18DACin17
DACin24DACin23DACin22DACin21
DACin28DACin27DACin26DACin25
DACin32DACin31DACin30DACin29
CS4bCS4
DACin36DACin35DACin34DACin33
DACin40DACin39DACin38DACin37
DACin44DACin43
CS0bCS0
DACin42DACin41
DACin48DACin47DACin46DACin45
CS1bCS1
CS2bCS2
CS3bCS3
DACin52DACin51DACin50DACin49
DACin56DACin55DACin54DACin53
DACin60DACin59DACin58DACin57
DACin64DACin63DACin62DACin61
CS4bCS4
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:DACAMUX_block
Modified:Oct 23, 2002 06:54:50Info:Analog MUX for DAC monitoring
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
BOut0bot
BOut0top
BOut1bot
BOut1top
DPFB1DPFB1DPFB2 DPFB2
DPFT1 DPFT1DPFT2DPFT2
DPin1
DPin2
DPO1
DPO2
Dual RingBuff
in
nRUN
Page 81
RFB RFB
ROVDD
select select
Include models
Page
106
Page
106
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, ManoaTel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4Iout4
Iout5 Iout5
Iout6 Iout6
Iout7Iout7
Iout8Iout8
Page 23
RO
RO ROb
ROb
sca_col_8SnH
SnH
SnHb
SnHb
Vin1Vin1
Vin2 Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6 Vin6
Vin7 Vin7
Vin8 Vin8
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4Iout4
Iout5 Iout5
Iout6 Iout6
Iout7Iout7
Iout8Iout8
Page 23
RO
RO ROb
ROb
sca_col_8SnH
SnH
SnHb
SnHb
Vin1Vin1
Vin2 Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6 Vin6
Vin7 Vin7
Vin8 Vin8
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4Iout4
Iout5 Iout5
Iout6 Iout6
Iout7Iout7
Iout8Iout8
Page 23
RO
RO ROb
ROb
sca_col_8SnH
SnH
SnHb
SnHb
Vin1Vin1
Vin2 Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6 Vin6
Vin7 Vin7
Vin8 Vin8
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4Iout4
Iout5 Iout5
Iout6 Iout6
Iout7Iout7
Iout8Iout8
Page 23
RO
RO ROb
ROb
sca_col_8SnH
SnH
SnHb
SnHb
Vin1Vin1
Vin2 Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6 Vin6
Vin7 Vin7
Vin8 Vin8
Page 91
sca_gatePage 91
sca_gate
C1hit
C0hit
SELF
0
SELF
0 S0S0b
Hitbus
DPFB2
DPFB1
DPFT1
DPFT2
RFB
DPin2DPin1Rin
DPO1DPO2
SCA Page 11
Iout16
Iout15
Iout14
Iout13
Iout12
Iout11
Iout10
Iout9
Iout8
Iout7
Iout6
Iout5
Iout4
Iout3
Iout2
Iout1
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
SCA Dual Column (sca_dual_col)
nRUN
ROVDD
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page
106
Page
106
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
Column
(sca_dual_col)
(sca_dual_col) DPFB1DPFB1DPFB2DPFB2
DPFT1DPFT1DPFT2DPFT2
DPin1
DPin2
DPO1
DPO2Dual
Dual Storage Column
Hitbus Hitbus
Iout1Iout1
Iout2Iout2
Iout3Iout3
Iout4 Iout4
Iout5Iout5
Iout6Iout6
Iout7Iout7
Iout8 Iout8
Iout9Iout9
Iout10Iout10
Iout11Iout11
Iout12 Iout12
Iout13Iout13
Iout14Iout14
Iout15Iout15
Iout16 Iout16
nRUNnRUN
Page 11
Page 11
RFB RFB
Rin
ROVDD ROVDD
S0 S0
S0b S0bSELF0
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
Column
(sca_dual_col)
(sca_dual_col) DPFB1DPFB1DPFB2DPFB2
DPFT1DPFT1DPFT2DPFT2
DPin1
DPin2
DPO1
DPO2Dual
Dual Storage Column
Hitbus Hitbus
Iout1Iout1
Iout2Iout2
Iout3Iout3
Iout4 Iout4
Iout5Iout5
Iout6Iout6
Iout7Iout7
Iout8 Iout8
Iout9Iout9
Iout10Iout10
Iout11Iout11
Iout12 Iout12
Iout13Iout13
Iout14Iout14
Iout15Iout15
Iout16 Iout16
nRUNnRUN
Page 11
Page 11
RFB RFB
Rin
ROVDD ROVDD
S0 S0
S0b S0bSELF0
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
DPin4
DFO3
DFO4
DPin4DPin3
S0S0b
S0S0b
SELF
1
SELF
1 S1S1b
Hitbus
DPFB2
DPFB1
DPFT1
DPFT2
RFB
DPin2DPin1
DFO1
DFO2
SCA Page 12
Iout16
Iout15
Iout14
Iout13
Iout12
Iout11
Iout10
Iout9
Iout8
Iout7
Iout6
Iout5
Iout4
Iout3
Iout2
Iout1
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
SCA Quad Column (sca_quad_col)
nRUN
ROVDD
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page
106
Page
106
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, ManoaTel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
Column
(sca_dual_col)
(sca_quad_col)
DFO1
DFO2
DFO3
DFO4
DPFB1DPFB1DPFB2 DPFB2
DPFT1 DPFT1DPFT2DPFT2
DPin1
DPin2
DPin3
DPin4
Dual Storage Column
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8 Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16 Iout16
nRUNnRUN
Page 11
Page 12
QuadRFB RFB
ROVDD ROVDD
S0S0
S1 S1
S0bS0b
S1b S1bSELF1
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
Column
(sca_dual_col)
(sca_quad_col)
DFO1
DFO2
DFO3
DFO4
DPFB1DPFB1DPFB2 DPFB2
DPFT1 DPFT1DPFT2DPFT2
DPin1
DPin2
DPin3
DPin4
Dual Storage Column
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8 Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16 Iout16
nRUNnRUN
Page 11
Page 12
QuadRFB RFB
ROVDD ROVDD
S0S0
S1 S1
S0bS0b
S1b S1bSELF1
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
ROVDD
nRUN
Iout1
Iout2
Iout3
Iout4
Iout5
Iout6
Iout7
Iout8
Iout9
Iout10
Iout11
Iout12
Iout13
Iout14
Iout15
Iout16
DFO2DFO1
RFB
DPFT2
DPFT1
DPFB1
DPFB2
Hitbus
S0bS0
DFO4DFO3
S1bS1
SCA Page 13
SELF
2
SELF
2 S2S2b
SCA Bank of 8 Column (sca_bank8_col)
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
DPin4DPin3DPin2DPin1
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page 106
Page 106
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
Column
(sca_bank8_col)
(sca_dual_col)
Bank of 8
DFO1
DFO2
DFO3
DFO4
DPFB1DPFB1DPFB2 DPFB2
DPFT1 DPFT1DPFT2DPFT2
DPin1
DPin2
DPin3
DPin4
Dual Storage Column
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4 Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16Iout16
nRUNnRUN
Page 11
Page 13
RFB RFB
ROVDD ROVDD
S0S0
S1 S1
S2 S2
S0bS0b
S1b S1b
S2b S2b
SELF2
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
Column
(sca_bank8_col)
(sca_dual_col)
Bank of 8
DFO1
DFO2
DFO3
DFO4
DPFB1DPFB1DPFB2 DPFB2
DPFT1 DPFT1DPFT2DPFT2
DPin1
DPin2
DPin3
DPin4
Dual Storage Column
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4 Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16Iout16
nRUNnRUN
Page 11
Page 13
RFB RFB
ROVDD ROVDD
S0S0
S1 S1
S2 S2
S0bS0b
S1b S1b
S2b S2b
SELF2
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
S2S2b
S1S1b
DPin4DFO3DFO4
DPin3
S0S0b
SELF
3
SELF
3 S3S3b
Hitbus
DPFB2
DPFB1
DPFT1
DPFT2
RFB
DPin2DPin1 DFO1
DFO2
SCA Page 14
Iout16
Iout15
Iout14
Iout13
Iout12
Iout11
Iout10
Iout9
Iout8
Iout7
Iout6
Iout5
Iout4
Iout3
Iout2
Iout1
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
SCA Bank of 16 Column (sca_bank16_col)
nRUN
ROVDD
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page
106
Page
106
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
Column(sca_bank16_col)
(sca_dual_col)
Bank of 16
DFO1
DFO2
DFO3
DFO4
DPFB1DPFB1DPFB2 DPFB2
DPFT1 DPFT1DPFT2DPFT2
DPin1
DPin2
DPin3
DPin4
Dual Storage Column
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4 Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8 Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16 Iout16
nRUNnRUN
Page 11
Page 14
RFB RFB
ROVDD ROVDD
S0S0
S1 S1
S2 S2
S3S3
S0bS0b
S1b S1b
S2b S2b
S3bS3bSELF3
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16 Column
(sca_bank16_col)
(sca_dual_col)
Bank of 16
DFO1
DFO2
DFO3
DFO4
DPFB1DPFB1DPFB2 DPFB2
DPFT1 DPFT1DPFT2DPFT2
DPin1
DPin2
DPin3
DPin4
Dual Storage Column
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4 Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8 Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16 Iout16
nRUNnRUN
Page 11
Page 14
RFB RFB
ROVDD ROVDD
S0S0
S1 S1
S2 S2
S3S3
S0bS0b
S1b S1b
S2b S2b
S3bS3bSELF3
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
S3bS3
S2S2b
S1S1b
DPin4DFO3DFO4
DPin3
S0S0b
SELF
4
SELF
4 S4S4b
Hitbus
DPFB2
DPFB1
DPFT1
DPFT2
RFB
DPin2DPin1 DFO1
DFO2
SCA Page 15
Iout16
Iout15
Iout14
Iout13
Iout12
Iout11
Iout10
Iout9
Iout8
Iout7
Iout6
Iout5
Iout4
Iout3
Iout2
Iout1
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
SCA Bank of 32 Column (sca_bank32_col)
nRUN
ROVDD
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page
106
Page
106
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, ManoaTel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
Column
(sca_bank32_col)
Bank of 32
DFO1
DFO2
DFO3
DFO4
DPFB1 DPFB1DPFB2DPFB2
DPFT1DPFT1DPFT2 DPFT2
DPin1
DPin2
DPin3
DPin4
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12 Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16Iout16
nRUNnRUN
Page 15
RFB RFB
ROVDD ROVDD
S0S0
S1 S1
S2 S2
S3S3
S4 S4
S0bS0b
S1b S1b
S2b S2b
S3bS3b
S4b S4b
SELF4
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16 Column
(sca_bank32_col)
Bank of 32
DFO1
DFO2
DFO3
DFO4
DPFB1 DPFB1DPFB2DPFB2
DPFT1DPFT1DPFT2 DPFT2
DPin1
DPin2
DPin3
DPin4
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12 Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16Iout16
nRUNnRUN
Page 15
RFB RFB
ROVDD ROVDD
S0S0
S1 S1
S2 S2
S3S3
S4 S4
S0bS0b
S1b S1b
S2b S2b
S3bS3b
S4b S4b
SELF4
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
S4bS4
S3bS3
S2S2b
S1S1b
DPin4DFO3DFO4
DPin3
S0S0b
SELF
5
SELF
5 S5S5b
Hitbus
DPFB2
DPFB1
DPFT1
DPFT2
RFB
DPin2DPin1 DFO1
DFO2
SCA Page 16
Iout16
Iout15
Iout14
Iout13
Iout12
Iout11
Iout10
Iout9
Iout8
Iout7
Iout6
Iout5
Iout4
Iout3
Iout2
Iout1
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
SCA Bank of 64 Column (sca_bank64_col)
nRUN
ROVDD
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page
106
Page
106
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, ManoaTel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
Column Column Column Column Column
(sca_bank64_col)
Bank of 64Bank of 64Bank of 64Bank of 64Bank of 64
DFO1DFO1DFO1DFO1DFO1
DFO2DFO2DFO2DFO2DFO2
DFO3DFO3DFO3DFO3DFO3
DFO4DFO4DFO4DFO4DFO4
DPFB1DPFB1DPFB1 DPFB1DPFB1DPFB1DPFB1DPFB1 DPFB1DPFB1DPFB2 DPFB2DPFB2DPFB2 DPFB2DPFB2 DPFB2DPFB2DPFB2 DPFB2
DPFT1DPFT1DPFT1 DPFT1DPFT1 DPFT1DPFT1DPFT1 DPFT1DPFT1DPFT2 DPFT2DPFT2DPFT2 DPFT2DPFT2DPFT2DPFT2 DPFT2DPFT2
DPin1DPin1DPin1DPin1DPin1
DPin2DPin2DPin2DPin2DPin2
DPin3DPin3DPin3DPin3DPin3
DPin4DPin4DPin4DPin4DPin4
Hitbus Hitbus
Iout1Iout1
Iout2 Iout2
Iout3Iout3
Iout4 Iout4
Iout5Iout5
Iout6 Iout6
Iout7Iout7
Iout8Iout8
Iout9Iout9
Iout10 Iout10
Iout11Iout11
Iout12Iout12
Iout13Iout13
Iout14 Iout14
Iout15Iout15
Iout16Iout16
nRUNnRUNnRUNnRUN nRUNnRUN nRUNnRUN nRUNnRUN
Page 16
RFB RFBRFBRFBRFB RFBRFBRFBRFB RFB
ROVDDROVDDROVDD ROVDDROVDDROVDDROVDDROVDDROVDDROVDD
S0S0
S1 S1
S2 S2
S3S3
S4 S4
S5 S5
S0bS0b
S1b S1b
S2b S2b
S3bS3b
S4b S4b
S5b S5bSELF5
StorageStorageStorageStorageStorage
Vin1Vin1
Vin2 Vin2
Vin3Vin3
Vin4 Vin4
Vin5 Vin5
Vin6 Vin6
Vin7Vin7
Vin8 Vin8
Vin9 Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
Column Column Column Column Column
(sca_bank64_col)
Bank of 64Bank of 64Bank of 64Bank of 64Bank of 64
DFO1DFO1DFO1DFO1DFO1
DFO2DFO2DFO2DFO2DFO2
DFO3DFO3DFO3DFO3DFO3
DFO4DFO4DFO4DFO4DFO4
DPFB1DPFB1DPFB1 DPFB1DPFB1DPFB1DPFB1DPFB1 DPFB1DPFB1DPFB2 DPFB2DPFB2DPFB2 DPFB2DPFB2 DPFB2DPFB2DPFB2 DPFB2
DPFT1DPFT1DPFT1 DPFT1DPFT1 DPFT1DPFT1DPFT1 DPFT1DPFT1DPFT2 DPFT2DPFT2DPFT2 DPFT2DPFT2DPFT2DPFT2 DPFT2DPFT2
DPin1DPin1DPin1DPin1DPin1
DPin2DPin2DPin2DPin2DPin2
DPin3DPin3DPin3DPin3DPin3
DPin4DPin4DPin4DPin4DPin4
Hitbus Hitbus
Iout1Iout1
Iout2 Iout2
Iout3Iout3
Iout4 Iout4
Iout5Iout5
Iout6 Iout6
Iout7Iout7
Iout8Iout8
Iout9Iout9
Iout10 Iout10
Iout11Iout11
Iout12Iout12
Iout13Iout13
Iout14 Iout14
Iout15Iout15
Iout16Iout16
nRUNnRUNnRUNnRUN nRUNnRUN nRUNnRUN nRUNnRUN
Page 16
RFB RFBRFBRFBRFB RFBRFBRFBRFB RFB
ROVDDROVDDROVDD ROVDDROVDDROVDDROVDDROVDDROVDDROVDD
S0S0
S1 S1
S2 S2
S3S3
S4 S4
S5 S5
S0bS0b
S1b S1b
S2b S2b
S3bS3b
S4b S4b
S5b S5bSELF5
StorageStorageStorageStorageStorage
Vin1Vin1
Vin2 Vin2
Vin3Vin3
Vin4 Vin4
Vin5 Vin5
Vin6 Vin6
Vin7Vin7
Vin8 Vin8
Vin9 Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
S5bS5
S4bS4
S3bS3
S2S2b
S1S1b
DPin4DFO3DFO4
DPin3
S0S0b
SELF
6
SELF
6 S6S6b
Hitbus
DPFB2
DPFB1
DPFT1
DPFT2
RFB
DPin2DPin1 DFO1
DFO2
SCA Page 17
Iout16
Iout15
Iout14
Iout13
Iout12
Iout11
Iout10
Iout9
Iout8
Iout7
Iout6
Iout5
Iout4
Iout3
Iout2
Iout1
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
SCA Bank of 128 Column (sca_bank128_col)
nRUN
ROVDD
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
pg.100
Include models
pg.101
pg.101
pg.101
pg.101
pg.101
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
CLK
CLK
IN OUT
Page 55
REG
Column
(sca_bank128_col)
Bank of 128
DFO1
DFO2
DFO3
DFO4
DPFB1 DPFB1DPFB2DPFB2
DPFT1DPFT1DPFT2 DPFT2
DPin1
DPin2
DPin3
DPin4
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4 Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12 Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16Iout16
nRUNnRUN
Page 17
RFB RFB
ROVDDROVDD
S0S0
S1 S1
S2 S2
S3S3
S4 S4
S5 S5
S6 S6
S0bS0b
S1b S1b
S2b S2b
S3bS3b
S4b S4b
S5b S5b
S6b S6bSELF6
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16 Column
(sca_bank128_col)
Bank of 128
DFO1
DFO2
DFO3
DFO4
DPFB1 DPFB1DPFB2DPFB2
DPFT1DPFT1DPFT2 DPFT2
DPin1
DPin2
DPin3
DPin4
HitbusHitbus
Iout1 Iout1
Iout2Iout2
Iout3 Iout3
Iout4 Iout4
Iout5 Iout5
Iout6Iout6
Iout7 Iout7
Iout8Iout8
Iout9 Iout9
Iout10Iout10
Iout11 Iout11
Iout12 Iout12
Iout13 Iout13
Iout14Iout14
Iout15 Iout15
Iout16Iout16
nRUNnRUN
Page 17
RFB RFB
ROVDDROVDD
S0S0
S1 S1
S2 S2
S3S3
S4 S4
S5 S5
S6 S6
S0bS0b
S1b S1b
S2b S2b
S3bS3b
S4b S4b
S5b S5b
S6b S6bSELF6
Storage
Vin1Vin1
Vin2Vin2
Vin3Vin3
Vin4Vin4
Vin5Vin5
Vin6Vin6
Vin7Vin7
Vin8Vin8
Vin9Vin9
Vin10Vin10
Vin11Vin11
Vin12Vin12
Vin13Vin13
Vin14Vin14
Vin15Vin15
Vin16Vin16
Added sampling of ripple phase
nRUN
PosNeg
50 Ohm pass-through
Vref16
Vref15
Vref14
Vref13
Vref12
Vref11
Vref10
Vref9
Vref8
Vref7
Vref6
Vref5
Vref4
Vref3
Vref2
Vref1
RFB RCORFB
DFO4
DFO2
DFO4
DFO3
DFO1
DFO4DFO3DFO2DFO1
S6S6b
S5bS5
S4bS4
S3bS3
S2S2b
S1S1b
S0S0b
S7S7b
Hitbus
SCA Page 18
Iout16
Iout15
Iout14
Iout13
Iout12
Iout11
Iout10
Iout9
Iout8
Iout7
Iout6
Iout5
Iout4
Iout3
Iout2
Iout1
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
SCA Bank of 256 Column (sca_bank256_col)
nRUN
ROVDD
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='1
2*l'
T1W=
'6*l
'
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW2\straw2_23oct02
Rev AInfo:Big Pass Transistor for mirror select
Module:big_passt Page:Page0
Modified:Oct 23, 2002 08:27:57Created:May 5, 1993 21:36:43
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
L='1
2*l'
T2W=
'6*l
'Include models
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
PASSb
IN
[NETTRAN OUTPUT=<# SCMOS_NOR2 %{A} %{B} %{Out}]Big Pass Transistor (big_passt)
Out
PASS
Page 22
PASS
bPA
SS
Page 22
OutIN
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='6
*l'
T1L=
'12*
l'
Created:May 5, 1993 21:36:43Modified:Oct 23, 2002 08:27:57
Page:Page0Module:big_passt
Info:Big Pass Transistor for mirror select Rev A
Path:C:\CustomIC\STRAW2\straw2_23oct02
Designer:Gary S. Varner
Size: 5x7
W='6
*l'
T2L=
'12*
l'
.param l=0.12u
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
IoutIoutPage 22
RO
RO ROb
ROb
sca_base_cell
SnH
SnH
SnHb
SnHb
Vin Vin
IoutIoutPage 22
RO
RO ROb
ROb
sca_base_cell
SnH
SnH
SnHb
SnHb
Vin Vin
IoutIoutPage 22
RO
RO ROb
ROb
sca_base_cell
SnH
SnH
SnHb
SnHb
Vin Vin
IoutIoutPage 22
RO
RO ROb
ROb
sca_base_cell
SnH
SnH
SnHb
SnHb
Vin Vin
IoutIoutPage 22
RO
RO ROb
ROb
sca_base_cell
SnH
SnH
SnHb
SnHb
Vin Vin
IoutIoutPage 22
RO
RO ROb
ROb
sca_base_cell
SnH
SnH
SnHb
SnHb
Vin Vin
IoutIoutPage 22
RO
RO ROb
ROb
sca_base_cell
SnH
SnH
SnHb
SnHb
Vin Vin
IoutIoutPage 22
RO
RO ROb
ROb
sca_base_cell
SnH
SnH
SnHb
SnHb
Vin Vin
Iout1
SCA Half_column of 8 (sca_col_8)
Vin1Sn
HbSn
H
ROb
RO
Iout2
Vin2
Vin3
Vin4
Vin5
Vin6
Iout3
Iout4
Iout5
Iout6
Iout7
Vin7
SnHb
SnH
ROb
ROIout8
Vin8
SCA Page 23
.param l=0.12u
Size: 5x7
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:Col_left_basecell Page:Page0
Info:Input cell left colModified:Sep 24, 2002 13:26:02Created:May 5, 1993 21:36:41
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
R=19.872k
R=19.872k
VgrefVgref
Col_left_basecell
pg.31VgrefVgref
VinVinVinVin
Vin
Vgref
n.c. pulldown/shutdown and input protect
50 Ohm nom. impedance
Vgref
SCA Page 31
Column Left Basecell (Col_left_basecell)
Vin
.param l=0.12u
Size: 5x7Created:May 5, 1993 21:36:41Modified:Sep 24, 2002 13:26:02
Info:Input cell left col
Page:Page0Module:Col_left_basecell
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
R=19.872k
R=19.872k
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Col_left_basecell
pg.31VgrefVgref
VinVin
Col_left_basecell
pg.31VgrefVgref
VinVin
Col_left_basecell
pg.31VgrefVgref
VinVin
Col_left_basecell
pg.31VgrefVgref
VinVin
Col_left_basecell
pg.31VgrefVgref
VinVin
Col_left_basecell
pg.31VgrefVgref
VinVin
Col_left_basecell
pg.31VgrefVgref
VinVin
Col_left_basecell
pg.31VgrefVgref
VinVin
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:Col_left_8 Page:Page0
Info:Left input cellsModified:Oct 23, 2002 05:28:06Created:May 5, 1993 21:36:41
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Vgref8
Vgref7
Vgref6
Vgref5
Vgref4
Vgref3
Vgref2
Vgref1
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
Col_left_8
pg.32
Vin1 Vin1
Vin2 Vin2
Vin3 Vin3
Vin4 Vin4
Vin5 Vin5
Vin6 Vin6
Vin7 Vin7
Vin8 Vin8
Vgref1 Vgref1
Vgref2 Vgref2
Vgref3 Vgref3
Vgref4 Vgref4
Vgref5 Vgref5
Vgref6 Vgref6
Vgref7 Vgref7
Vgref8 Vgref8
Pass-through Trigger signals are No Connect
Vgref8
Vgref7
Vgref6
Vgref5
Vgref4
Vgref3
Vgref2
Vgref1
Vin8
Bank of 8 Col Left cells (Col_left_8)
SCA Page 32
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
.param l=0.12u
Size: 5x7Created:May 5, 1993 21:36:41Modified:Oct 23, 2002 05:28:06
Info:Left input cells
Page:Page0Module:Col_left_8
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Col_left_8
pg.32
Vgref1
Vgref2
Vgref3
Vgref4
Vgref5
Vgref6
Vgref7
Vgref8
Vin1
Vin2
Vin3
Vin4
Vin5
Vin6
Vin7
Vin8
Col_left_8
pg.32
Vgref1
Vgref2
Vgref3
Vgref4
Vgref5
Vgref6
Vgref7
Vgref8
Vin1
Vin2
Vin3
Vin4
Vin5
Vin6
Vin7
Vin8
Include models
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Module:Col_left_bank Page:Page0
Designer:Dr. Gary S. Varner
Info:Left bank compilationModified:Sep 24, 2002 14:05:03Created:Mar 14, 2002 10:47:07
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
Vgref16
Vgref15
Vgref14
Vgref13
Vgref12
Vgref11
Vgref10
Vgref9
Vgref8
Vgref7
Vgref6
Vgref5
Vgref4
Vgref3
Vgref2
Vgref1
SCA Page 33
Vin16
Vin15
Vin14
Vin13
Vin12
Vin11
Vin10
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
Left Bank (Col_left_bank)
.param l=0.12u
Created:Mar 14, 2002 10:47:07Modified:Sep 24, 2002 14:05:03
Info:Left bank compilation
Designer:Dr. Gary S. Varner
Page:Page0Module:Col_left_bank
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page 106
Page 106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:A/M 12-bit Bus selectModified:Oct 14, 2002 08:57:20
Module:out_dualbase_cell Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Page 91
sca_gate
Page 91
sca_gate
Obus Obus
Iout2Iout2
Page 41
CS0
CS0
CS0b
CS0b
out_dualbase_cell
CSELF0
CSEL
F0
Iout1 Iout1
CSELF0
nSB
nSBCS0
Iout2 Obus
CSELF0
nSA
nSACS0b
Iout1
SCA Page 41
Output Dual Base Cell (out_dualbase_cell)
Obus
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:out_dualbase_cell
Modified:Oct 14, 2002 08:57:20Info:A/M 12-bit Bus select
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page 106
Page 106
CS0 CS0bCSELF0
Iout1
Iout2
Obus
out_dualbase_cell
Page 41
CS0 CS0bCSELF0
Iout1
Iout2
Obus
out_dualbase_cell
Page 41
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:A/M 12-bit Bus selectModified:Sep 23, 2002 16:05:45
Module:out_quadbase_cell Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
CS1
CS1b
CS1 CS1b
Iout4Iout4
Iout3Iout3
Obus Obus
Iout2Iout2
Page 42
CS0 CS0
CS0b CS0b
out_quadbase_cell
CSELF1
CSEL
F1
Iout1 Iout1
CS0bCS0
Iout4
CSELF1CS1
Iout3 Obus
CS0bCS0
Iout2
CSELF1CS1b
Iout1
SCA Page 42
Output Quad Base Cell (out_quadbase_cell)
Obus
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:out_quadbase_cell
Modified:Sep 23, 2002 16:05:45Info:A/M 12-bit Bus select
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Page 106
Page 106
CS0
CS1
CS0b
CS1bCSELF1
Iout1
Iout2
Iout3
Iout4
Obus
out_quadbase_cell
Page 42
CS0
CS1
CS0b
CS1bCSELF1
Iout1
Iout2
Iout3
Iout4
Obus
out_quadbase_cell
Page 42
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:A/M 12-bit Bus selectModified:Sep 23, 2002 16:05:06
Module:out_octbase_cell Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
CS1 CS1
CS1b CS1bIout8Iout8
Iout7Iout7
Iout6Iout6
Iout5 Iout5
CS2
CS2b
CS2 CS2b
Iout4Iout4
Iout3Iout3
Obus ObusIout2Iout2
Page 43
CS0 CS0
CS0b CS0b
out_octbase_cell
CSELF2
CSEL
F2
Iout1 Iout1
CS1bCS1
Iout8Iout7
CS0bCS0
Iout6
CSELF2CS2
Iout5 Obus
CS1bCS1
Iout4Iout3
CS0bCS0
Iout2
CSELF2CS2b
Iout1
SCA Page 43
Output Octal Base Cell (out_octbase_cell)
Obus
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:out_octbase_cell
Modified:Sep 23, 2002 16:05:06Info:A/M 12-bit Bus select
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
CS0
CS1
CS2
CS0b
CS1b
CS2bCSELF2
Iout1
Iout2
Iout3
Iout4
Iout5
Iout6
Iout7
Iout8
Obus
out_octbase_cellPage 43
CS0
CS1
CS2
CS0b
CS1b
CS2bCSELF2
Iout1
Iout2
Iout3
Iout4
Iout5
Iout6
Iout7
Iout8
Obus
out_octbase_cellPage 43
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:A/M 12-bit Bus selectModified:Sep 1, 2003 10:20:51
Module:out_block Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Vref16
Vin16
Vref15
Vin15
Vref14
Vin14
Vref13
Vin13
Vref12
Vin12
Vref11
Vin11
Vref10
Vin10
Vref9
Vin9
Pass through signals
Vref8
Vin8
Vref7
Vin7
Vref6
Vin6
Vref5
Vin5
Vref4
Vin4
Vref3
Vin3
Vref2
Vin2
Vref1
Vin1
CS2bCS2
CS1bCS1
CS0bCS0
ObusCS
3b
Iout16Iout15Iout14Iout13Iout12Iout11Iout10
CS3
Iout9
CS1bCS1
Iout8Iout7Iout6Iout5
CS2bCS2
Iout4Iout3
CS0bCS0
Iout2Iout1
SCA Page 45
Output Block w/Select (out_block)
Obus
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:out_block
Modified:Sep 1, 2003 10:20:51Info:A/M 12-bit Bus select
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
pg.101
Page 106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Cena
Q12 Q12
Q13 Q13
Q14 Q14
Q15 Q15
Clk
Page 46
Q0 Q0
Q1 Q1
Q2 Q2
Q3 Q3
Q4 Q4
Q5 Q5
Q6 Q6
Q7 Q7
Q8 Q8
Q9 Q9
Q10 Q10
Q11 Q11
scaler16
RESET
RESE
T
Cena Q12
Q13
Q14
Q15
nRESET
nRESET
nRESET
nRESETPage 46
nRESET
Q4
Q5
Q6
Q7
RESET
nRESET
nRESET
nRESET
nRESET
Q8
Q9
Q10
Q11
nRESET
nRESET
nRESET
nRESET
16-bit scaler [15+overflow bit] (scaler16)
nRESET
nRESET
nRESET
nRESET
Q3
Q2
Q1
Q0Clk
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Page 106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
D15
D14
D12 D12
D13 D13
D14
D15
Q12 Q12
Q13 Q13
Q14 Q14
Q15 Q15
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
D8 D8
D9 D9
D10 D10
D11 D11
OE
OE
Page 47
Q0 Q0
Q1 Q1
Q2 Q2
Q3 Q3
Q4 Q4
Q5 Q5
Q6 Q6
Q7 Q7
Q8 Q8
Q9 Q9
Q10 Q10
Q11 Q11
ROE16
OEC
nOEC
OEC
nOEC
OEC
nOEC
OEC
nOEC
D12
D13
D15
D14
Q12
Q13
Q14
Q15
OEC
nOEC
OEC
nOEC
OEC
nOEC
OEC
nOEC
OEC
nOEC
OEC
nOEC
OEC
nOEC
OEC
nOECnOEC
nOEC
nOEC
nOEC
nOEC
OEC
OEC
OEC
OEC
OEC
D8
D9
D11
D10
D4
D5
D7
D6
Register Output Enable [16-bit reg] (ROE16)
Page 47
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
OE
Q0D0
D1
D3
D2
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
OE
Page 47
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
ROE16
Page 46
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
RESET
scaler16
CPFCPF
Cena Cena
Clk
Count Ena
OE
OE
Page 48
Q0Q0Q0 Q0
Q1Q1 Q1Q1
Q2Q2Q2 Q2
Q3 Q3 Q3Q3
Q4Q4 Q4 Q4
Q5 Q5Q5Q5
Q6Q6 Q6Q6
Q7 Q7Q7 Q7
Q8 Q8Q8 Q8
Q9 Q9Q9Q9
Q10Q10 Q10Q10
Q11Q11Q11 Q11
Q12Q12 Q12Q12
Q13 Q13Q13 Q13
Q14Q14Q14 Q14
Q15 Q15 Q15Q15
RESETRESET RESET
Scaler_Block
Q2Q1Q0
16-bit Scaler+Output Enable (Scaler_Block)
Page 48
Q7Q6Q5Q4Q3
Q12Q13Q14Q15
Q8Q9Q10Q11
OERESE
T
ClkCena
CPF
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Page
106
Page
106
Page 106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Clk1
Clk2
Clk3
Clk4
Clk5
Clk6
Clk7
Clk8
Count Ena
Page 163
Q0 Q0
Q1Q1
Q2 Q2
Q3Q3
Q4Q4
Q5Q5
Q6 Q6
Q7Q7
Q8 Q8
Q9Q9
Q10Q10
Q11Q11
Q12 Q12
Q13 Q13
Q14Q14
Q15Q15
RESET
S0S0
S1 S1
S2S2
S3 S3
S0b S0b
S1b S1b
S2b S2b
S3bS3b
Scaler_Block8
SELF4
Clk1
Clk2
Clk3
Clk4
Clk5
Clk6
Clk7
Clk8
Count Ena
Page 163
Q0 Q0
Q1Q1
Q2 Q2
Q3Q3
Q4Q4
Q5Q5
Q6 Q6
Q7Q7
Q8 Q8
Q9Q9
Q10Q10
Q11Q11
Q12 Q12
Q13 Q13
Q14Q14
Q15Q15
RESET
S0S0
S1 S1
S2S2
S3 S3
S0b S0b
S1b S1b
S2b S2b
S3bS3b
Scaler_Block8
SELF4
SELF5SELB
S3S3b
Clk15Clk16
Clk13Clk14
Clk7Clk8
Clk5Clk6
Clk11Clk12
Clk9Clk10
S2S2b
Clk3Clk4
S1S1bS0S0b
RESETCena
Clk1Clk2
S4S4bSELA
Q2Q1Q0
Block of 16 Scalers (Scaler_Block16)
Page 49Q7Q6Q5Q4Q3
Q12Q13Q14Q15
Q8Q9Q10Q11
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
+
-
biasComp
Fast
Page 54
ADCC
TRL
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
CLK
CLR
COMPARE
D0D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11EOC
HOLD
Page 56
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
DAC12
Page 83VOUT
Include modelsPage 106
Page 103
L='3*l'T1 W='9*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:ADC12 Page:Page0
Info:12-bit Successive Approximation ADCModified:Sep 6, 2003 11:12:23Created:Nov 3, 1999 09:33:45
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
CLK
CLK
IN OUT
Page 55
REG Wimp
DACspy
FCsp
y
DACs
py
plug
Comparator bias
Cbias
FCsp
y
Cbia
s
B11 D11
B8 D8B9 D9B10 D10
B7 D7
B4 D4B5 D5B6 D6
B3 D3
B2 D2
B1 D1
B0
B11B10B9B8
Page 50
CLRB
EOC
ADC12
ANAINPUT
B0 B1 B2 B3 B4 B5 B6 B7
CLKSTART
CLR
D0
.param l=0.12u
W='9*l'T1L='3*l' Size: 5x7Created:Nov 3, 1999 09:33:45
Modified:Sep 6, 2003 11:12:23Info:12-bit Successive Approximation ADC
Page:Page0Module:ADC12
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:DAC_IN Page:Page0
Info:DAC trimModified:Nov 1, 2002 05:55:47Created:Aug 25, 1995 10:21:16
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
R=13.518K
(DAC_IN)
ADJADJUST_IN
DAC_IN
Page 52
VOUT VOUT
Page 52
VOUTADJUST_IN
Size: 5x7Created:Aug 25, 1995 10:21:16Modified:Nov 1, 2002 05:55:47
Info:DAC trim
Page:Page0Module:DAC_IN
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
R=13.518K
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T2 W='21.0*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:DAC_BIT Page:Page0
Info:R-2R DAC bitModified:Sep 2, 2003 18:49:50Created:Aug 25, 1995 10:33:23
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='85.5*l'
R=13.518k
R=26.496K
DAC_BIT
wonk
DAC_BIT
BIT_
IN
BITVOUTVREFM
VREFPVIN
VREFM
VREFPVIN VOUTVREFM
VREFP
R2
BIT_
IN
R1VOUTVIN
VREFM
VREFP
Page 53
Page 53
.param l=0.12u
W='21.0*l'T2L='3*l'
Size: 5x7Created:Aug 25, 1995 10:33:23Modified:Sep 2, 2003 18:49:50
Info:R-2R DAC bit
Page:Page0Module:DAC_BIT
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='85.5*l'T1L='3*l'
R=13.518k
R=26.496K
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T24 W='11*l'
L='3*l'T4W='31.5*l'
L='3*l'T12 W='60*l'
L='3*l'T13W='60*l'
L='3*l'T15 W='9*l'
L='3*l'T14 W='9*l'
L='3*l'T16 W='9*l'
L='3*l'T3 W='31.5*l' L='3*l'
T20 W='31.5*l'L='3*l'
T21W='31.5*l'
L='3*l'T22 W='31.5*l'
L='3*l'T5 W='9*l'
L='3*l'T33 W='31.5*l'
L='3*l'T34W='31.5*l'
L='3*l'T43 W='31.5*l'
L='3*l'T44W='31.5*l'
L='3*l'T53 W='31.5*l'
L='3*l'T54W='31.5*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev AInfo:Fast 2-stage comparator for LC Pix timing
Module:Comparator2 Page:Page0
Modified:Aug 30, 2003 13:55:21Created:Jun 15, 1994 16:30:25
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T23 W='17*l'
L='3*l'T6 W='9*l'
L='3*l'T2W='9*l'
L='3*l'T7 W='9*l'
L='3*l'T18 W='31.5*l'
L='3*l'T19W='31.5*l'
L='3*l'T1W='9*l'
L='3*l'T17 W='31.5*l'
L='18*l'T8 W='9*l'
L='18*l'T9W='9*l'
L='18*l'T10 W='9*l'
L='18*l'T11W='9*l'
(Comparator2)
VnVp
VnVp
VnVp
+
-
bias
CMPb
ias
Comp
Fast
Page 54
VhsVn
Vp
CMPbias
CMPbias
Vhs
Two-stage Fast Comparator
VnVp
Page 54
.param l=0.12u
W='11*l'T24L='3*l'
W='31.5*l' T4L='3*l'
W='60*l'T12L='3*l'
W='60*l' T13L='3*l'
W='9*l'T15L='3*l'
W='9*l'T14L='3*l'
W='9*l'T16L='3*l'
W='31.5*l'T3L='3*l'
W='31.5*l'T20L='3*l'
W='31.5*l' T21L='3*l'
W='31.5*l'T22L='3*l'
W='9*l'T5L='3*l'
W='31.5*l'T33L='3*l'
W='31.5*l' T34L='3*l'
W='31.5*l'T43L='3*l'
W='31.5*l' T44L='3*l'
W='31.5*l'T53L='3*l'
W='31.5*l' T54L='3*l'
Size: 5x7Created:Jun 15, 1994 16:30:25Modified:Aug 30, 2003 13:55:21
Page:Page0Module:Comparator2
Info:Fast 2-stage comparator for LC Pix timing Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T23L='3*l'
W='9*l'T6L='3*l'
W='9*l' T2L='3*l'
W='9*l'T7L='3*l' W='31.5*l'T18
L='3*l'W='31.5*l' T19
L='3*l'
W='9*l' T1L='3*l' W='31.5*l'T17
L='3*l'
W='9*l'T8L='18*l'
W='9*l' T9L='18*l'
W='9*l'T10L='18*l'
W='9*l' T11L='18*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
pg.101 pg.101
L='3*l'T2 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev A
Module:${Module} Page:${Page}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='17*l'
Din
CLK
CLK
Page 55
CLK
CLK
ININ OUT OUTREG
SCA Page 55
REG
OUT
IN
CLK
.param l=0.12u
W='11*l'T2L='3*l'
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Page:${Page}Module:${Module}
Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T1L='3*l'
pg.1
00
pg.1
00pg.1
00
pg.1
00
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
CLKCLR
D
DFFECE
Page 58
Q
QB
Page 106
Page 106
Page 106
Page 106
Page 106
Page 106
Page 106
Page 106
Page 106
Page 106
Page 106
Page 106
Page 106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:ADCCTRL Page:Page0
Info:ADC Control BlockModified:Aug 30, 2003 13:55:22Created:Nov 1, 1999 15:57:55
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REGCL
KCL
K
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
CLK
CLR
HOLD
Page 57
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
QB0
QB1
QB2
QB3
QB4
QB5
QB6
QB7
QB8
QB9
QB10
QB11
QB12
SHIF
T12
simp
11si
mp10
simp
9si
mp8
simp
7si
mp6
simp
5si
mp4
simp
3si
mp2
simp
1
simp0
plug2HOLD
EOC
S7
S6
S5
S4
S3
S2
S1
S0
S8
S7
S6
S5
S4
S3
S2
S1
S0
ADCCTRLCLR
HOLD
B7
B6
B5
B4
B3
B2
B1
D11
CLRCLK
COMPARE
Page 56S9
S10
S11
S12
S8
B10
S9
B9
S10
B8
S11
B0
B11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Page 56
HOLD HOLD
EOC EOC
COMPARE COMPARE
CLRCLR
CLK CLK
B11 B11
B10 B10
B9B9
B8B8
B7B7
B6B6
B5 B5
B4 B4
B3B3
B2B2
B1 B1
B0 B0
ADCC
TRL
D0D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0D0
Size: 5x7Created:Nov 1, 1999 15:57:55Modified:Aug 30, 2003 13:55:22
Info:ADC Control Block
Page:Page0Module:ADCCTRL
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
pg.100
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
CLR
D
DFFEC
E
Page 58
Q QB
CLK
D
DFFE
PE
Page 59
PRB
Q QB
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev A
Module:${Module} Page:${Page}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Quack
SRbogus
CLKCLK
CLR
CLR
HOLD
HOLD
Q0Q0
Q1Q1
Q2Q2 Q3
Q3
Q4Q4
Q5Q5
Q6Q6 Q7
Q7
Q8Q8
Q9Q9
QB0
QB0
QB1
QB1
QB2
QB2
QB3
QB3
QB4
QB4
QB5
QB5
QB6
QB6
QB7
QB7
QB8
QB8
QB9
QB9
Page 57
Q10
Q10
QB10
QB10
Q11
QB11
Q12
QB12
Q11
QB11 Q12
QB12
SHIFT12
QB11
Q11
QB10
Q10
QB9
Q9
SHIFT12
Page 57
QB12
QB8
QB7
QB6
QB5
QB4
QB3
QB2
QB1
QB0
Q12
Q8Q7Q6Q5Q4Q3Q2Q1Q0
CLR
CLKHOLD
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Page:${Page}Module:${Module}
Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
ClD
Page 111
Q
QbA
B
Page 114
S0
Y
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:DFFEC Page:Page0
Info:DFF w/Ena & ClearModified:Aug 30, 2003 13:55:22Created:Nov 1, 1999 14:50:00
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
D
E
CLK
Q
QB
CLR
DFFEC CLRCLK
ED
QB
QDECLKCLR
Q
QBDFFECPage 58
Page 58
NAD
Size: 5x7Created:Nov 1, 1999 14:50:00Modified:Aug 30, 2003 13:55:22
Info:DFF w/Ena & Clear
Page:Page0Module:DFFEC
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
ClD
Page 111
Q
Qb
pg.101A
B
Page 114
S0
Y
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:DFFEP Page:Page0
Info:presetable D Flip-flopModified:Aug 30, 2003 13:55:22Created:Nov 1, 1999 15:07:45
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
NERDNAD
Page 59
Page 59
CLK CLKDD
DFFEPEE
PRBPRB
QB QBDFFEP
PRB
CLK
E
DQB
Q
Size: 5x7Created:Nov 1, 1999 15:07:45Modified:Aug 30, 2003 13:55:22
Info:presetable D Flip-flop
Page:Page0Module:DFFEP
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
Page 106
Page 106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930iQ11
inQ11
nACrstnACrstnACrst
nACrstnACrstnACrst
nACrstnACrstnACrst
nACrstnACrst
bogus11
nbogus11
Clk
12-bit Ripple Counter (RCCNTR)nACrst
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
nACrst
nACrst
Q8
Q9
Q10
Q11
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
nQ10
nQ11
nQ0
Q11 Q11
Q10 Q10
Q9 Q9
Q8Q8
Q7 Q7
Q6 Q6
Q5 Q5
Q4Q4
Q3 Q3
Q2Q2
Q1Q1
Q0Q0
Page
65
nACrst nACrstnQ11 nQ11
nQ10 nQ10
nQ9nQ9
nQ8 nQ8
nQ7 nQ7
nQ6 nQ6
nQ5 nQ5
nQ4 nQ4
nQ3nQ3
nQ2nQ2
nQ1nQ1
Clk
12-b
it
(RCC
NTR)
nQ0 nQ0
Addr
/Sel
Cou
nter
SPAR
SPARset high to activate column select
SPAR
SPAR
Page 65
disabled when SPAR low
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner, PhD
Path:C:\CustomIC\STRAW3\STRAW3
Rev AInfo:MLU Trigger Reference
Module:MLU_R Page:Page0
Modified:Oct 23, 2002 08:06:33Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
23.184k
Page 117
Rswitched
IRout
MLU Select Level (MLU_R)ML
U4
STRAW3 Page 66
MLU3
MLU2
MLU1
MLU0
Page 66
IRou
t
MLU0
MLU0
MLU1
MLU1
MLU2
MLU2
MLU3
MLU3
MLU4
MLU4
IRou
t
MLU_R
.param l=0.12u
Size: 5x7Created:May 5, 1993 21:36:43Modified:Oct 23, 2002 08:06:33
Page:Page0Module:MLU_R
Info:MLU Trigger Reference Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner, PhD
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='12*l'T4W='30*l'
L='3*l'T0 W='11*l'
+
-
bias
Fast
OTAPage 99
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner, PhD
Path:C:\CustomIC\STRAW3\STRAW3
Rev AInfo:MLU Trigger
Module:MLU Page:Page0
Modified:Sep 4, 2003 11:21:53Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
R=23.184k
R=23.184k
R=2k
R=2k
Tbia
s
IRout
LLout
LLtrig
Majority Logic Unit (MLU)
STRAW3 Page 67Tbia
sPage 67
LLtr
ig
Tbia
sTb
ias
LLou
tLL
out
IRou
tIR
out
LLtr
ig MLU
.param l=0.12u
W='30*l' T4L='12*l'
W='11*l'T0L='3*l'
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 4, 2003 11:21:53
Page:Page0Module:MLU
Info:MLU Trigger Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner, PhD
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
R=23.184k
R=23.184k
R=2k
R=2k
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
DACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0bDACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0b
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
QbInclude models
Page 106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:GAINblock Page:Page0
Info:Gain Adjust select blockModified:Sep 1, 2003 14:09:00Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
R=23.184k
R=23.184k
R=23.184k
R=23.184k
R=23.184k
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
Page 91
sca_gate
nGTRclr
ibis
G5b
GTMo
ut
ESS0
GTMout
G4
G5bG4
G4bG3G0 G1 G2 G3
G3b
G3
G2b
G2
G1b
G1
G0
G0b
G3bG2
G2bG1
G1bG0
G0b
GTMclk
GTMin
SS0
nSS0
SS0
nSS0
G4 G4b
nSS0SS0
DAout
CAL
Page 69
Output Gain/Select (GAINblock)
ANALout
Obus
.param l=0.12u
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 1, 2003 14:09:00
Info:Gain Adjust select block
Page:Page0Module:GAINblock
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
R=23.184k
R=23.184k
R=23.184k
R=23.184k
R=23.184k
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:DAC8a Page:Page0
Info:8-bit adjust offset DACModified:Aug 27, 2002 12:37:26Created:Aug 8, 1995 16:28:28
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
R=270
R=26.496K
VREF VOUT
Vref
B0
B0 B1
B1
B2
B2 B3
B3
B4
B4 B5
B5
B6
B6
B7
B7
Page 73DAC8a
VOUT VOUTVREF
B0 B2B1 B6B3 B4 B5 B7
DAC8a (8-bit DAC adjust)
Page 73
Size: 5x7Created:Aug 8, 1995 16:28:28Modified:Aug 27, 2002 12:37:26
Info:8-bit adjust offset DAC
Page:Page0Module:DAC8a
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
R=270
R=26.496K
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
DAC12
Page 83VOUT
B0 B1 B2 B3 B4 B5 B6 B7
DAC8a Page 73VOUTVref
Include models
+
-
bias
Fast
OTAPage 99
+
-
bias
Fast
OTAPage 99
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev A
Module:${Module} Page:${Page}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
D11
D10D9D8
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0D7D6D5D4D3D2D1D0
Vbia
s
Vbia
s
Vout
20 bit composite DAC (superDAC)
SCA Page 76.param l=0.12u
Size: 5x7Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Page:${Page}Module:${Module}
Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Clb
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
DREG20Page 84
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb6
Qb7
Qb8
Qb9
Qb10
Qb11
Qb12
Qb13
Qb14
Qb15
Qb16
Qb17
Qb18
Qb19
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Clb
DIN
Page 85
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
Q18
Q19
SDOT
SREG20D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Page 76
SuperDAC
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TD7
Vbias
Vout
nREG
clr
nREGclr
Dout
DCLKSCLKVoutVbias
DIN
SCA Page 77
Serial-load SuperDAC [20-bit] (SS_DAC) .param l=0.12u
Size: 5x7
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, ManoaTel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
11
2 2
33
4 4
55
6 6
77
A
A B
B C
C D
D E
E F
F G
G H
H I
I J
J
Size: A
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
VoutDC
LKDC
LKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
DCLK
DCLKDIN
Dout
nREG
clr
nREG
clrPage 77
SCLK
SCLK
Serial Super DACSS_DAC Vb
ias
Vbia
s
Vout
nREG
clr
nREG
clr
nREG
clr
nREG
clr
SCA Page 78
16 Ch. Serial SuperDAC [20-bit] (SS_DAC16)
Vout4
Vout3
Vout2
DCLK
SCLK
Vout1
Vbia
s
DIN
Vout8
Vout7
Vout6
DCLK
SCLK
Vout5
Vbia
s
Vout12
Vout11
Vout10
DCLK
SCLK
Vout9
Vbia
s
Dout
Vout16
Vout15
Vout14
DCLK
SCLK
Vout13
Vbia
s
.param l=0.12u
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Size: A
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
pg.101
pg.101
Page 106
Page 106
Page 106
Page 106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev AInfo:Dual Ring oscillator/fanout
Module:dual_ring_buff Page:Page0
Modified:May 20, 2002 15:05:25Created:Jun 15, 1994 16:30:25
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
CLK
CLK
IN OUT
Page 55
REG
CLK
CLK
IN OUT
Page 55
REG
d_outin
outPage 82
RingCell
ROVDD
d_outin
outPage 82
RingCell
ROVDD
BufferPage 121
Super
BufferPage 121
Super
BufferPage 121
Super
BufferPage 121
Super
BufferPage 121
Super
BufferPage 121
Super
BufferPage 121
Super
BufferPage 121
Super
Page 105
Page 105
bot1
bot1b
bot0
bot0b
top1
top1b
top0
top0b
DPO2
Rin
SCA Page 81
dual_ring_buffer
nRUN
nRUN
DPin1DPO1
DPin2
ROVDD
ROVDD
top1
b
top0
b
top1
top0
Rin
Page 81
nRUNnRUN
in
Dual RingBuff
DPO2DPO2
DPO1 DPO1
DPin2 DPin2
DPin1 DPin1
BOut1top
BOut1bot
BOut0top
BOut0bot
bot1
b
bot0
b
bot1
bot0
ROVDDROVDD
ROb_
0
RO_0
select
ROb_
0
RO_0
ROb_
1
RO_1
ROb_
1
RO_1
select
DPFT1 DPFT1DPFT2 DPFT2
RFB RFBDPFB1 DPFB1DPFB2 DPFB2
DPFT1DPFT2RFBDPFB1DPFB2
DPFT1DPFT2RFBDPFB1DPFB2
.param l=0.12u.param l=0.12u
Size: 5x7Size: 5x7Created:Jun 15, 1994 16:30:25Modified:May 20, 2002 15:05:25
Page:Page0Module:dual_ring_buff
Info:Dual Ring oscillator/fanout Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev AInfo:${Info}
Module:${Module} Page:${Page}
Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
pg.109 pg.109
ROVDDROVDDDoutd_out
inout
Page 82Rin
RingCellRout
ROVD
D
RoutRin
SCA Page 82
ring_cell
Dout
ROVD
D
.param l=0.12u.param l=0.12u
Size: 5x7Size: 5x7Created:${Created}Modified:${Modified}
Page:${Page}Module:${Module}
Info:${Info} Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
BIT
DAC_BITPage 53
VINVOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BIT Page 53
VIN VOUTVREFM
VREFP
BIT
DAC_BITPage 53
VINVOUTVREFM
VREFP
BIT
DAC_BITPage 53
VINVOUTVREFM
VREFP
BIT
DAC_BITPage 53
VINVOUTVREFM
VREFP
BIT
DAC_BITPage 53
VINVOUTVREFM
VREFP
BIT
DAC_BITPage 53
VINVOUTVREFM
VREFP
ADJ
DAC_IN
Page 52
VOUT
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:DAC12 Page:Page0
Info:TSMC 0.25u 12-bit DACModified:Oct 1, 2002 12:22:49Created:Aug 8, 1995 16:28:28
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
B0
B0 B1
B1
B2
B2 B3
B3
B4
B4 B5
B5
B6
B6
B7
B7
B8
B8
B9
B9
B10
B10
B11
B11
Page 83DAC12 VOUT VOUT
B11
B10 B9 B8
Page 83
DAC12
B7
B5B4B3
B6
B1 B2B0
VOUT
Size: 5x7Created:Aug 8, 1995 16:28:28Modified:Oct 1, 2002 12:22:49
Info:TSMC 0.25u 12-bit DAC
Page:Page0Module:DAC12
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
pg.100
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Module:DREG20 Page:Page0
Designer:Dr. Gary S. Varner
Info:D Flip-flop registersModified:Sep 1, 2003 14:55:16Created:May 5, 1993 21:36:41
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Qb19D19
CK
Qb18D18
CK
Qb17D17
CK
Qb16D16
CK
Qb15D15
CK
Qb14D14
CK
Qb13D13
CK
Qb12D12
CK
special superDAC version (w/inv. outputs)
Qb11D11
CK
Qb10D10
CK
Qb9D9
CK
Qb8D8
CK
Qb7D7
CK
Qb6D6
CK
Qb5D5
CK
Qb4D4
CK
Qb3D3
CK
Qb2D2
CK
Qb1D1
CK
Qb0D0
CK
CK
Page 84
20-bit Data Register (DREG20)Clk
Size: 5x7Created:May 5, 1993 21:36:41Modified:Sep 1, 2003 14:55:16
Info:D Flip-flop registers
Designer:Dr. Gary S. Varner
Page:Page0Module:DREG20
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
pg.100
pg.100
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
ClD
Page 111
Q
Qb
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
Clb
SDOT
Q19
CK
Q18
CK
Q17
CK
Q16
CK
Q15
CK
Q14
CK
Q13
CK
Q12
CK
special superDAC version (reset not meaningful)
Q11
CK
Q10
CK
Q9
CK
Q8
CK
Q7
CK
Q6
CK
Q5
CK
Q4
CK
Q3
CK
Q2
CK
Q1
CK
Q0DIN
CK
CK
Page 85
20-bit Shift Register (SREG20)Clk
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='12*l'T4W='30*l'
+
-
bias
Fast
OTAPage 99
+
-
bias
Fast
OTAPage 99
+
-
bias
Fast
OTAPage 99
+
-
bias
Fast
OTAPage 99
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev AInfo:Analog Output Buffer (ao_buff)
Module:ao_superbuff Page:Page0
Modified:Sep 4, 2003 11:24:40Created:Jun 15, 1994 16:30:25
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Vbia
s
Input
Analog Output Super Buffer (ao_superbuff)
Page 88
Vout
Vbia
sInput VoutVb
ias
Input Vout
Vbia
s
Input VoutVbia
sVout
Vbias
Vbia
s
Super
Page 88
Input in
Buffer
Analog
.param l=0.12u
W='30*l' T4L='12*l'
Size: 5x7Created:Jun 15, 1994 16:30:25Modified:Sep 4, 2003 11:24:40
Page:Page0Module:ao_superbuff
Info:Analog Output Buffer (ao_buff) Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3
*l'
T2W=
'11*
l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev AInfo:${Info}
Module:${Module} Page:${Page}
Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3
*l'
T1W=
'17*
l'
sca_gatebus store
Page 91
PASS
PASS
b
SCA Page 91
PASS
store
SCA Pass Transistor (sca_gate)
bus
PASSb
.param l=0.12u
W='1
1*l'
T2L=
'3*l
'
Size: 5x7Created:${Created}Modified:${Modified}
Page:${Page}Module:${Module}
Info:${Info} Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='1
7*l'
T1L=
'3*l
'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
pg.100
ClD
Page 111
Q
Qb
Include models
Page 106
L='1
29*l
'T1
02W=
'144
*l'
L='12*l'T103W='30*l'
options
+
-
bias
Fast
OTAPage 99
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:discrim_adj Page:Page0
Info:32-chan SCA/Trigger chipModified:Oct 23, 2002 07:02:38Created:Nov 3, 1999 09:33:45
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T0W='68*l'
Page 91
sca_gate
ICbiasVthreshVT
bias
Vin
Page 94
Out
Discrim_adj
Wadj
ICbias
Out
Vin
VTbi
as
Vthresh
fbr
shout
17.3 x 20.8um ~ 1.58pF (4.8fF/um^2 but 1.58pF extracted)
STRAW3 Page 94
Adj. Width Discriminator (discrim_adj)
.param l=0.12u
W='1
44*l
'T1
02L=
'129
*l'
W='30*l' T103L='12*l'
Size: 5x7Size: 5x7Created:Nov 3, 1999 09:33:45Modified:Oct 23, 2002 07:02:38
Info:32-chan SCA/Trigger chip
Page:Page0Module:discrim_adj
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='68*l' T0L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Discrim_adj
Page 94
Wadj
Discrim_adj
Page 94
Wadj
Include models
pg.101Page 103
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:discrim_pair Page:Page0
Info:Similation for trigger on Bi-polar pulsesModified:Oct 23, 2002 07:00:59Created:Nov 3, 1999 09:33:45
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
ICbi
as
Out
HitL
HitH
Vthresh_hi
Vthresh_lo
Vin
Vbia
sVb
ias
upper and lower disrim pair (discrim_pair)
STRAW3 Page 95.param l=0.12u
Size: 5x7Size: 5x7Created:Nov 3, 1999 09:33:45Modified:Oct 23, 2002 07:00:59
Info:Similation for trigger on Bi-polar pulses
Page:Page0Module:discrim_pair
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Discr. pair
HHHL
OR
Page 95Discr. pair
HHHL
OR
Page 95
Include models
L='3*l'T0 W='11*l'
+
-
bias
Fast
OTAPage 99
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner, PhD
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:discrim_hl Page:Page0
Info:High & Low bi-level Disrim. block Modified:Sep 4, 2003 10:52:04Created:Nov 3, 1999 09:33:45
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
R=37.058
R=23.184k
R=1k R=10k
Aout
inn
ICbi
as
ICbi
as
LLsum
HLhighHHhigh
HLlowHHlow
TrigHigh
HHthrHLthr
LHthrLLthr
Vbia
sVb
s
Vgref
Vin
STRAW3 Page 96
VTbi
as
VTbi
as
disrim high-low block (discrim_hl)
.param l=0.12u
W='11*l'T0L='3*l'
Size: 5x7Size: 5x7Created:Nov 3, 1999 09:33:45Modified:Sep 4, 2003 10:52:04
Info:High & Low bi-level Disrim. block
Page:Page0Module:discrim_hl
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner, PhD
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
R=37.058
R=23.184k
R=1k R=10k
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
(discrim_hl)
Disrim. H/L
HHhigh
HHlow
HHthr HLhigh
HLlow
HLthr
ICbi
asIC
bias
LHthr
LLsum
LLsum
LLthr
Page 96
Single ChannelTrigHighVb
ias
Vbia
s
Vbs
Vbs
VgrefVin
VTbias
VTbias
(discrim_hl)
Disrim. H/L
HHhigh
HHlow
HHthr HLhigh
HLlow
HLthr
ICbi
asIC
bias
LHthr
LLsum
LLsum
LLthr
Page 96
Single ChannelTrigHighVb
ias
Vbia
s
Vbs
Vbs
VgrefVin
VTbias
VTbias
Include models
pg.101Page 103
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev A
Module:${Module} Page:${Page}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
ICbi
as
Vbia
s
HLT2HHT2
LLT2LHT2
HLH2HHH2
HLL2HHL2
HLH1HHH1
HLT1HHT1
LLT1
Vref2
HLL1HHL1
Vref1
LLsu
m
LHT1
Vin1
Vbs
Vin2
SCA Page 97
Pair of Comp Pairs (PairCompPair)
VTbi
as
HLout
.param l=0.12u
Size: 5x7Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Page:${Page}Module:${Module}
Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
pg.101Page 103
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner, PhD
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:Discrim_hl_quad Page:Page0
Info:A quad of Discrim. channelsModified:Oct 21, 2002 19:24:24Created:Nov 3, 1999 09:33:45
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
(PairCompPair)
HHH1
HHH2
HHL1
HHL2
HHT1
HHT2
HLH1
HLH2
HLL1
HLL2
HLout
HLT1
HLT2
ICbias
ICbias
LHT1
LHT2
LLsum
LLsum
LLT1
LLT2 Page 97
Pair of Comp Pairs
Vbias
Vbias
Vbs
VbsVin1
Vin2
Vref1
Vref2
VTbias
VTbias
(PairCompPair)
HHH1
HHH2
HHL1
HHL2
HHT1
HHT2
HLH1
HLH2
HLL1
HLL2
HLout
HLT1
HLT2
ICbias
ICbias
LHT1
LHT2
LLsum
LLsum
LLT1
LLT2 Page 97
Pair of Comp Pairs
Vbias
Vbias
Vbs
VbsVin1
Vin2
Vref1
Vref2
VTbias
VTbias
ICbi
as
HLH4HHH4HLL4HHL4
HLH3HHH3HLL3HHL3
HLT4HHT4LLT4LHT4
HLT3HHT3LLT3
Vref4
Vref3LHT3
Vin3
Vin4
Vbia
s
HLT2HHT2LLT2LHT2
HLH2HHH2HLL2HHL2
HLH1HHH1
HLT1HHT1LLT1
Vref2
HLL1HHL1
Vref1
LLsu
m
LHT1
Vin1
Vbs
Vin2
SCA Page 98
Set of 4 Discrim blocks (Discrim_hl_quad)
VTbi
as
HLout
.param l=0.12u
Size: 5x7Size: 5x7Created:Nov 3, 1999 09:33:45Modified:Oct 21, 2002 19:24:24
Info:A quad of Discrim. channels
Page:Page0Module:Discrim_hl_quad
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner, PhD
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='12*l'T4W='30*l'
L='3*l'T8W='30*l'
L='12*l'T6 W='30*l' L='12*l'
T12 W='30*l'
L='3*l'T5 W='30*l'
L='12*l'T11W='30*l'
L='3*l'T16 W='30*l'
L='12*l'T15W='30*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Gary S. Varner
Info:Fast Operational Transimp AmpModified:Oct 23, 2002 06:43:53
Module:OTA Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='12*l'T10 W='90*l'
L='12*l'T1W='90*l'
L='3*l'T3 W='90*l'
L='12*l'T2 W='90*l'
L='3*l'T7 W='90*l'
L='12*l'T9W='90*l'
L='3*l'T14 W='90*l'
L='12*l'T13W='90*l'
M=3!!
M=3!!
+
-
bias
OPbi
as
OTA
Fast
Page 99
OutINn
INp
Out
OPbias
INn
INp
OTA for Fast performance (OTA)
Page 99
.param l=0.12u
W='30*l' T4L='12*l'
W='30*l' T8L='3*l'
W='30*l'T6L='12*l'
W='30*l'T12L='12*l'
W='30*l'T5L='3*l'
W='30*l' T11L='12*l'
W='30*l'T16L='3*l'
W='30*l' T15L='12*l'
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:OTA
Modified:Oct 23, 2002 06:43:53Info:Fast Operational Transimp Amp
Designer:Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='90*l'T10L='12*l'
W='90*l' T1L='12*l'
W='90*l'T3L='3*l'
W='90*l'T2L='12*l'
W='90*l'T7L='3*l'
W='90*l' T9L='12*l'
W='90*l'T14L='3*l'
W='90*l' T13L='12*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T2 W='11*l'
L='3*l'T4 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:Buf1 Page:Page0
Info:Std. min. Digital bufferModified:Aug 30, 2003 13:55:22Created:May 5, 1993 21:36:41
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='17*l'
L='3*l'T3 W='17*l'
SCA Page 100
pg.100
1
Buf1
A OUT
OUTA
.param l=0.12u
W='11*l'T2L='3*l'
W='11*l'T4L='3*l'
Size: 5x7Created:May 5, 1993 21:36:41Modified:Aug 30, 2003 13:55:22
Info:Std. min. Digital buffer
Page:Page0Module:Buf1
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T1L='3*l'
W='17*l'T3L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T2 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:Inv Page:Page0
Info:Deep sub-micron Standard cell INV.Modified:Aug 30, 2003 13:55:22Created:May 5, 1993 21:36:41
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='17*l'
pg.101
SCA Page 101
[NETTRAN OUTPUT=<# SCMOS_INV %{A} %{Out} VDD GND]
Inv
A OUT
A OUT
.param l=0.12u
W='11*l'T2L='3*l'
Size: 5x7Created:May 5, 1993 21:36:41Modified:Aug 30, 2003 13:55:22
Info:Deep sub-micron Standard cell INV.
Page:Page0Module:Inv
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T1L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T4 W='11*l'
L='3*l'T3 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev AInfo:Deep sub-micron Standard Cell NOR2
Module:NOR2 Page:Page0
Modified:Aug 30, 2003 13:55:22Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T2 W='17*l'
L='3*l'T1 W='17*l'
Page 103
Page 103
B
A
[NETTRAN OUTPUT=<# SCMOS_NOR2 %{A} %{B} %{Out}]
1
NOR2
A
BOut
B
Out
.param l=0.12u
W='11*l'T4L='3*l'
W='11*l'T3L='3*l'
Size: 5x7Created:May 5, 1993 21:36:43Modified:Aug 30, 2003 13:55:22
Page:Page0Module:NOR2
Info:Deep sub-micron Standard Cell NOR2 Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T2L='3*l'
W='17*l'T1L='3*l'
Page 106
Page 103
Page 103
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:${Created}
Designer:${Author}
Info:${Info}Modified:${Modified}
Module:${Module} Page:${Page}
Path:${File}
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Page 105
Page 105
[NETTRAN OUTPUT=<# SCMOS_XOR2 %{A} %{B} %{Out}]
Out
B
A
XOR2
A
BOut
Size: 5x7
Rev A
Path:${File}
Page:${Page}Module:${Module}
Modified:${Modified}Info:${Info}
Designer:${Author}
Created:${Created}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T3 W='11*l'
L='3*l'T4 W='11*l'
L='3*l'T6 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev AInfo:Deep sub-micron Standard cell NAND2C
Module:NAND2C Page:Page0
Modified:Sep 3, 2003 11:56:05Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='17*l'
L='3*l'T2 W='17*l'
L='3*l'T5 W='17*l'
Page 106
Page 106
[NETTRAN OUTPUT=<# SCMOS_NAND2C %{A} %{B} %{Out1} %{Out2}]
NAND2C
A
BOut1
Out2
Out2
Out1
A
B
BA
.param l=0.12u
W='11*l'T3L='3*l'
W='11*l'T4L='3*l'
W='11*l'T6L='3*l'
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 3, 2003 11:56:05
Page:Page0Module:NAND2C
Info:Deep sub-micron Standard cell NAND2C Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T1L='3*l'
W='17*l'T2L='3*l'
W='17*l'T5L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T2 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev A
Module:${Module} Page:${Page}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='17*l'
ROVD
D
A OUTpg.109
ROVD
D
SCA Page 109
Ring Oscillator Inverter (ring_osc_inv)
A OUT
.param l=0.12u
W='11*l'T2L='3*l'
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Page:${Page}Module:${Module}
Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T1L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T2 W='11*l'
L='3*l'T7 W='11*l'
L='3*l'T8 W='11*l'
L='3*l'T9 W='11*l'
L='3*l'T10 W='11*l'
L='3*l'T12 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:Mux2 Page:Page0
Info:2-input MUXModified:Oct 23, 2002 07:22:29Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='17*l'
L='3*l'T3 W='17*l'
L='3*l'T4 W='17*l'
L='3*l'T5 W='17*l'
L='3*l'T6 W='17*l'
L='3*l'T11 W='17*l'
AA
B BOUT
Page 110
S0
SEL
Y
Page 110
6
5
4
3
2
G
G
G
Mux2
OUT
B
B
SEL
SEL
A
A
SEL
.param l=0.12u
W='11*l'T2L='3*l' W='11*l'T7
L='3*l'
W='11*l'T8L='3*l'
W='11*l'T9L='3*l'
W='11*l'T10L='3*l'
W='11*l'T12L='3*l'
Size: 5x7Created:May 5, 1993 21:36:43Modified:Oct 23, 2002 07:22:29
Info:2-input MUX
Page:Page0Module:Mux2
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T1L='3*l'
W='17*l'T3L='3*l'
W='17*l'T4L='3*l'
W='17*l'T5L='3*l'
W='17*l'T6L='3*l'
W='17*l'T11L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T8 W='11*l'
L='3*l'T7 W='11*l'
L='3*l'T12 W='11*l'
L='3*l'T11 W='11*l'
L='3*l'T21 W='11*l'
L='3*l'T20 W='11*l'
L='3*l'T26 W='11*l'
L='3*l'T24 W='11*l' L='3*l'
T29 W='11*l'
L='3*l'T27 W='11*l'
L='3*l'T2 W='11*l'
L='3*l'T4 W='11*l'
L='3*l'T13 W='11*l'
L='3*l'T17 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Module:DFFC Page:Page0
Designer:Dr. Gary S. Varner
Info:D Flip-Flop with ClearModified:Aug 30, 2003 15:33:40Created:May 5, 1993 21:36:41
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T6 W='17*l'
L='3*l'T5 W='17*l'
L='3*l'T10 W='17*l'
L='3*l'T9 W='17*l'
L='3*l'T19 W='17*l'
L='3*l'T18 W='17*l'
L='3*l'T23 W='17*l'
L='3*l'T22 W='17*l'
L='3*l'T14 W='17*l'
L='3*l'T28 W='17*l'
L='3*l'T1 W='17*l'
L='3*l'T3 W='17*l'
L='3*l'T15 W='17*l'
L='3*l'T16 W='17*l'
L='3*l'T25 W='17*l'
fb
x1 x2
Page 111
Page 111
14
13
x2
119
8
7
6
fb
5
x1
3
CB
CCB
C
CB
C
CB
CB
C
CCB
DFFC Cl
ClB
Clk
Data D QQ
Qb QB
ClB
ClB
ClB
Clk
Data
Q
QB
ClBData
.param l=0.12u
W='11*l'T8L='3*l'
W='11*l'T7L='3*l'
W='11*l'T12L='3*l'
W='11*l'T11L='3*l'
W='11*l'T21L='3*l'
W='11*l'T20L='3*l'
W='11*l'T26L='3*l'
W='11*l'T24L='3*l'
W='11*l'T29L='3*l'
W='11*l'T27L='3*l'
W='11*l'T2L='3*l'
W='11*l'T4L='3*l'
W='11*l'T13L='3*l'
W='11*l'T17L='3*l'
Size: 5x7Created:May 5, 1993 21:36:41Modified:Aug 30, 2003 15:33:40
Info:D Flip-Flop with Clear
Designer:Dr. Gary S. Varner
Page:Page0Module:DFFC
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T6L='3*l'
W='17*l'T5L='3*l'
W='17*l'T10L='3*l'
W='17*l'T9L='3*l'
W='17*l'T19L='3*l'
W='17*l'T18L='3*l'
W='17*l'T23L='3*l'
W='17*l'T22L='3*l'W='17*l'T14
L='3*l'
W='17*l'T28L='3*l'
W='17*l'T1L='3*l'
W='17*l'T3L='3*l'
W='17*l'T15L='3*l'
W='17*l'T16L='3*l'
W='17*l'T25L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T2 W='11*l'
L='3*l'T7 W='11*l'
L='3*l'T8 W='11*l'
L='3*l'T9 W='11*l'
L='3*l'T10 W='11*l'
L='3*l'T12 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:Mux2ADC Page:Page0
Info:2-input MUXModified:Sep 4, 2003 11:56:08Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='17*l'
L='3*l'T3 W='17*l'
L='3*l'T4 W='17*l'
L='3*l'T5 W='17*l'
L='3*l'T6 W='17*l'
L='3*l'T11 W='17*l'
opposite definition for ADC!!N.B.!!
Page 114
6
5
4
3
2
G
G
G
Mux2ADC
OUT
B
B
SEL
SEL
A
A
SEL
.param l=0.12u
W='11*l'T2L='3*l' W='11*l'T7
L='3*l'
W='11*l'T8L='3*l'
W='11*l'T9L='3*l'
W='11*l'T10L='3*l'
W='11*l'T12L='3*l'
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 4, 2003 11:56:08
Info:2-input MUX
Page:Page0Module:Mux2ADC
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='17*l'T1L='3*l'
W='17*l'T3L='3*l'
W='17*l'T4L='3*l'
W='17*l'T5L='3*l'
W='17*l'T6L='3*l'
W='17*l'T11L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T0 W='11*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev AInfo:${Info}
Module:${Module} Page:${Page}
Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
R=23.184k
Page 11723.184k
RswitchedIn Out
STRAW3 Page 117
In
Switched R (Rsw)
Out
.param l=0.12u
W='11*l'T0L='3*l'
Size: 5x7Created:${Created}Modified:${Modified}
Page:${Page}Module:${Module}
Info:${Info} Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
R=23.184k
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3*l'T4 W='44*l'
L='3*l'T3 W='22*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev AInfo:${Info}
Module:${Module} Page:${Page}
Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T2 W='68*l'
L='3*l'T1 W='34*l'
SCA Page 121
Page 121
A Abuff
Buffer
Super
[NETTRAN OUTPUT=<# SCMOS_DFF %{Data} %{Clk} %{Q} %{QB}]
Super Buffer (super_buff)
AbuffA
.param l=0.12u
W='44*l'T4L='3*l'
W='22*l'T3L='3*l'
Size: 5x7Created:${Created}Modified:${Modified}
Page:${Page}Module:${Module}
Info:${Info} Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='68*l'T2L='3*l'
W='34*l'T1L='3*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:dual Analog MUXModified:Oct 23, 2002 06:53:23
Module:DACAMUX_dual Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Page 91
sca_gate
Page 91
sca_gate
S0
S0
S0b
S0b
DACAMUX_dual
DACin1 DACin1
DACin2DACin2
Obus Obus
Page 141
S0b
S0S0
DACin2 ObusS0
b
DACin1
SCA Page 141
DAC Analog MUX 2-Ch. (DACAMUX_dual)
Obus
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:DACAMUX_dual
Modified:Oct 23, 2002 06:53:23Info:dual Analog MUX
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
DACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0b
DACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0b
DACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0b
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:Analog MUX elementModified:Oct 23, 2002 06:52:31
Module:DACAMUX_quad Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
CS0 CS0
CS1
CS1
CS0b CS0b
CS1b
CS1b
DACin1DACin1
DACin2 DACin2
DACin3 DACin3
DACin4 DACin4
ObusObus
DACAMUX_quad
Page 142
CS1
CS1b
Obus
DAC Analog Mux 4-Ch. (DACAMUX_quad)
SCA Page 142
DACin1
DACin2
CS0
CS0b
DACin3
DACin4
CS0
CS0b
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:DACAMUX_quad
Modified:Oct 23, 2002 06:52:31Info:Analog MUX element
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
DACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0b
CS0
CS1
CS0b
CS1b
DACAMUX_quad
DACin1
DACin2
DACin3
DACin4
Obus
Page 142
CS0
CS1
CS0b
CS1b
DACAMUX_quad
DACin1
DACin2
DACin3
DACin4
Obus
Page 142
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:A/M 12-bit Bus selectModified:Oct 15, 2002 07:37:33
Module:DACAMUX_octal Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
DACin1DACin1
DACin2 DACin2
DACin3 DACin3
DACin4 DACin4
CS2
CS2b
CS2b
CS2CS0
CS0
CS0b
CS0b
CS1
CS1
CS1b
CS1b
DACin5DACin5
DACin6 DACin6
DACin7 DACin7
DACin8 DACin8
ObusObus
DACAMUX_octal
Page 143
CS2
CS2b
CS0CS0b
CS1
CS1b
DACin5DACin6DACin7DACin8
CS1
CS1b
Obus
DAC Analog Mux 8-Ch. (DACAMUX_octal)
SCA Page 143
DACin1DACin2
CS0CS0b
DACin3DACin4
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:DACAMUX_octal
Modified:Oct 15, 2002 07:37:33Info:A/M 12-bit Bus select
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
DACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0b
CS0 CS1 CS2CS0b CS1b CS2b
DACAMUX_octalDACin1
DACin2
DACin3
DACin4
DACin5
DACin6
DACin7
DACin8
Obus
Page 143
CS0 CS1 CS2CS0b CS1b CS2b
DACAMUX_octalDACin1
DACin2
DACin3
DACin4
DACin5
DACin6
DACin7
DACin8
Obus
Page 143
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:A/M 12-bit Bus selectModified:Oct 15, 2002 07:37:33
Module:DACAMUX_hex Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
CS3
CS3b
CS3b
CS3
DACin1DACin1
DACin2 DACin2
DACin3 DACin3
DACin4 DACin4
DACin5DACin5
DACin6 DACin6
DACin7 DACin7
DACin8 DACin8
DACin9DACin9
DACin10 DACin10
DACin11 DACin11
DACin12 DACin12
CS2
CS2b
CS2b
CS2CS0
CS0
CS0b
CS0b
CS1
CS1
CS1b
CS1b
DACin13DACin13
DACin14 DACin14
DACin15 DACin15
DACin16 DACin16
ObusObus
DACAMUX_hex
Page 144CS
2CS
2bCS1
CS1b
DACin13DACin14DACin15DACin16
DACin9DACin10
CS0
CS0b
DACin11DACin12
CS2
CS2b
CS3
CS3b
CS1
CS1b
DACin5DACin6DACin7DACin8
Obus
DAC Analog Mux 16-Ch. (DACAMUX_octal)
SCA Page 144
DACin1DACin2
CS0
CS0b
DACin3DACin4
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:DACAMUX_hex
Modified:Oct 15, 2002 07:37:33Info:A/M 12-bit Bus select
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
DACAMUX_dual
DACin1
DACin2
Obus
Page 141
S0 S0b
CS0 CS1 CS2 CS3CS0b CS1b CS2b CS3b
DACAMUX_hexDACin1
DACin2
DACin3
DACin4
DACin5
DACin6
DACin7
DACin8
DACin9
DACin10
DACin11
DACin12
DACin13
DACin14
DACin15
DACin16
Obus
Page 144
CS0 CS1 CS2 CS3CS0b CS1b CS2b CS3b
DACAMUX_hexDACin1
DACin2
DACin3
DACin4
DACin5
DACin6
DACin7
DACin8
DACin9
DACin10
DACin11
DACin12
DACin13
DACin14
DACin15
DACin16
Obus
Page 144
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:A/M 12-bit Bus selectModified:Oct 15, 2002 06:58:29
Module:DACAMUX_32 Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
CS3
CS3bCS2
CS2bCS1
CS1b
DACin29DACin30DACin31DACin32
DACin25DACin26
CS0
CS0b
DACin27DACin28
DACin21DACin22DACin23DACin24
DACin17DACin18DACin19DACin20CS3
CS3bCS2
CS2bCS1
CS1b
DACin13DACin14DACin15DACin16
DACin9DACin10
CS0
CS0b
DACin11DACin12
CS4
CS4b
DACin5DACin6DACin7DACin8
Obus
DAC Analog Mux 32-Ch. (DACAMUX_32)
SCA Page 145
DACin1DACin2DACin3DACin4
.param l=0.12u
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:DACAMUX_32
Modified:Oct 15, 2002 06:58:29Info:A/M 12-bit Bus select
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Page
106
Page
106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Count Ena
CPFOE
Page 48
Q0 Q0
Q1 Q1
Q2Q2
Q3 Q3
Q4 Q4
Q5Q5
Q6Q6
Q7 Q7
Q8 Q8
Q9Q9
Q10Q10
Q11 Q11
Q12Q12
Q13 Q13
Q14Q14
Q15 Q15
RESET
Scaler_Block
Count Ena
CPFOE
Page 48
Q0 Q0
Q1 Q1
Q2Q2
Q3 Q3
Q4 Q4
Q5Q5
Q6Q6
Q7 Q7
Q8 Q8
Q9Q9
Q10Q10
Q11 Q11
Q12Q12
Q13 Q13
Q14Q14
Q15 Q15
RESET
Scaler_Block
is in low address positionClk
RESET
Q2Q1Q0
Q7Q6Q5Q4Q3
Q12Q13Q14Q15
Q8Q9Q10Q11
A pair of 16-bit Scalers (Scaler_Block_multi)
Page 160
SELF1
Cena
{forms 31 bit combined scaler count}
SELF
1
SELF1
Scaler_Block_multi
S0b S0bS0b S0b
S0S0 S0S0
RESETRESET RESET
Q15 Q15Q15 Q15
Q14 Q14Q14 Q14
Q13 Q13Q13Q13
Q12Q12 Q12Q12
Q11 Q11Q11 Q11
Q10Q10Q10Q10
Q9Q9Q9 Q9
Q8Q8 Q8Q8
Q7 Q7Q7 Q7
Q6Q6Q6Q6
Q5Q5Q5 Q5
Q4Q4Q4 Q4
Q3Q3 Q3 Q3
Q2Q2Q2 Q2
Q1Q1 Q1 Q1
Q0Q0Q0Q0
Page 160
Count Ena
ClkClk
CenaCena
S0 S0b
NOTE!!!
For consistency, High count
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Page
106
Page
106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Clk
Count Ena
Page 160
Q0 Q0
Q1Q1
Q2 Q2
Q3Q3
Q4 Q4
Q5Q5
Q6 Q6
Q7Q7
Q8 Q8
Q9Q9
Q10 Q10
Q11Q11
Q12 Q12
Q13Q13
Q14Q14
Q15Q15
RESET
S0 S0
S0bS0b
Scaler_Block_multi
SELF1
Clk
Count Ena
Page 160
Q0 Q0
Q1Q1
Q2 Q2
Q3Q3
Q4 Q4
Q5Q5
Q6 Q6
Q7Q7
Q8 Q8
Q9Q9
Q10 Q10
Q11Q11
Q12 Q12
Q13Q13
Q14Q14
Q15Q15
RESET
S0 S0
S0bS0b
Scaler_Block_multi
SELF1
S1 S1S1 S1
S1b S1b S1b S1b
Cena Cena
Clk1 Clk1
Clk2 Clk2
Count Ena
Page 161
Q0 Q0 Q0 Q0
Q1Q1Q1 Q1
Q2Q2 Q2 Q2
Q3Q3Q3 Q3
Q4Q4 Q4 Q4
Q5Q5 Q5 Q5
Q6 Q6 Q6 Q6
Q7Q7 Q7Q7
Q8 Q8Q8 Q8
Q9Q9 Q9 Q9
Q10 Q10 Q10 Q10
Q11Q11 Q11Q11
Q12 Q12Q12 Q12
Q13 Q13 Q13Q13
Q14Q14 Q14Q14
Q15Q15 Q15Q15
RESETRESET RESET
S0 S0S0 S0
S0bS0b S0bS0b
Scaler_Block2
SELF2
SELF
2
S0S0b
S1S1b
SELF2
Page 161
A pair of 32-bit Scalers (Scaler_Block2)
Q11Q10Q9Q8
Q15Q14Q13Q12
Q3Q4Q5Q6Q7
Q0Q1Q2
RESETCena
Clk1 Clk2
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Page
106
Page
106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Clk1
Clk2
Count Ena
Page 161
Q0 Q0
Q1 Q1
Q2Q2
Q3 Q3
Q4Q4
Q5 Q5
Q6 Q6
Q7 Q7
Q8Q8
Q9 Q9
Q10 Q10
Q11 Q11
Q12Q12
Q13 Q13
Q14 Q14
Q15 Q15
RESET
S0 S0
S1S1
S0bS0b
S1b S1b
Scaler_Block2
SELF2
Clk1
Clk2
Count Ena
Page 161
Q0 Q0
Q1 Q1
Q2Q2
Q3 Q3
Q4Q4
Q5 Q5
Q6 Q6
Q7 Q7
Q8Q8
Q9 Q9
Q10 Q10
Q11 Q11
Q12Q12
Q13 Q13
Q14 Q14
Q15 Q15
RESET
S0 S0
S1S1
S0bS0b
S1b S1b
Scaler_Block2
SELF2
S1S1bS0S0b
Clk3Clk4
S2S2b
SELF3
Page 162
A quad of 16-bit Scalers (Scaler_Block4)
Q11Q10Q9Q8
Q15Q14Q13Q12
Q3Q4Q5Q6Q7
Q0Q1Q2
RESETCena
Clk1Clk2
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
Page
106
Page
106
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:${File}
Module:${Module} Page:${Page}
Designer:${Author}
Info:${Info}Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Clk1
Clk2
Clk3
Clk4
Count Ena
Page 162
Q0Q0
Q1 Q1
Q2 Q2
Q3 Q3
Q4 Q4
Q5 Q5
Q6 Q6
Q7 Q7
Q8Q8
Q9 Q9
Q10Q10
Q11 Q11
Q12 Q12
Q13 Q13
Q14 Q14
Q15Q15
RESET
S0 S0
S1S1
S2 S2
S0b S0b
S1b S1b
S2b S2b
Scaler_Block4
SELF3
Clk1
Clk2
Clk3
Clk4
Count Ena
Page 162
Q0Q0
Q1 Q1
Q2 Q2
Q3 Q3
Q4 Q4
Q5 Q5
Q6 Q6
Q7 Q7
Q8Q8
Q9 Q9
Q10Q10
Q11 Q11
Q12 Q12
Q13 Q13
Q14 Q14
Q15Q15
RESET
S0 S0
S1S1
S2 S2
S0b S0b
S1b S1b
S2b S2b
Scaler_Block4
SELF3
S2S2b
Clk3Clk4
S1S1b
Clk5Clk6
S0S0b
Clk7Clk8
S3S3b
SELF4
Page 163
An octal of 16-bit Scalers (Scaler_Block8)
Q11Q10Q9Q8
Q15Q14Q13Q12
Q3Q4Q5Q6Q7
Q0Q1Q2
RESETCena
Clk1Clk2
Size: 5x7Created:${Created}Modified:${Modified}
Info:${Info}
Designer:${Author}
Page:${Page}Module:${Module}
Path:${File}
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
YA
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
B
Page 110
S0
Y
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:May 5, 1993 21:36:43
Designer:Dr. Gary S. Varner
Info:A/M 12-bit Bus selectModified:Sep 4, 2003 11:13:45
Module:mux16 Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
D14
D15
D12
D13
D12
D13
D14
D15
A14
A15
A12
A13
A12
A13
A14
A15
B14
B15
B12
B13
B12
B13
B14
B15
SEL
A10
A11
A8
A9
A6
A7
A4
A5
A2
A3
A0
A1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B10
B11
B8
B9
B6
B7
B4
B5
B2
B3
D10
D11
D8
D9
D8
D9
D10
D11
D6
D7
D4
D5
D4
D5
D6
D7
D2
D3
D0
D1
D0
MUX32:16
SEL
B0
B1
Page 177
B0
B1
D1
B2
B3
D2
B4
B5
D3
B6
B7
B8
B9
B10
B11
SEL
SEL
SEL
SEL
SEL
SEL
SEL
SEL
D0
16-bit bus select (mux16)
STRAW3 Page 177
SEL
D1
D2
D3
D4
D5
D6
D7
D8
A9 D9B9
D10
A11
A10B10
D11B11
S=0 ==> B; S=1 ==> A
D12
A13
A12B12
D13B13
D14
A15
A14B14
D15B15
A0B0
A1B1
SEL
SEL
SEL
A2B2
A3B3
SEL
SEL
SEL
SEL
A4B4
A5B5
A6B6
A7B7
A8B8
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:mux16
Modified:Sep 4, 2003 11:13:45Info:A/M 12-bit Bus select
Designer:Dr. Gary S. Varner
Created:May 5, 1993 21:36:43
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='3
*l'
T2W=
'22*
l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:${Author}
Path:${File}
Rev AInfo:${Info}
Module:${Module} Page:${Page}
Modified:${Modified}Created:${Created}
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3
*l'
T1W=
'34*
l'
bus
Page 191
PASS
PASS
b
sca_gate1store
STRAW3 HF version
SCA Page 191
PASS
store
SCA Pass Transistor (sca_gate1)
bus
PASSb
.param l=0.12u
W='2
2*l'
T2L=
'3*l
'
Size: 5x7Created:${Created}Modified:${Modified}
Page:${Page}Module:${Module}
Info:${Info} Rev A
Path:${File}
Designer:${Author}
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='3
4*l'
T1L=
'3*l
'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u(Discrim_hl_quad)
A quad of Disrim. Ch.
HHH1
HHH2
HHH3
HHH4
HHL1
HHL2
HHL3
HHL4
HHT1
HHT2
HHT3
HHT4
HLH1
HLH2
HLH3
HLH4
HLL1
HLL2
HLL3
HLL4
HLout
HLT1
HLT2
HLT3
HLT4
ICbias
ICbias
LHT1
LHT2
LHT3
LHT4
LLsum
LLsum
LLT1
LLT2
LLT3
LLT4 Page 98
Vbias
Vbias
Vbs
VbsVin1
Vin2
Vin3
Vin4
Vref1
Vref2
Vref3
Vref4
VTbias
VTbias
(Discrim_hl_quad)
A quad of Disrim. Ch.
HHH1
HHH2
HHH3
HHH4
HHL1
HHL2
HHL3
HHL4
HHT1
HHT2
HHT3
HHT4
HLH1
HLH2
HLH3
HLH4
HLL1
HLL2
HLL3
HLL4
HLout
HLT1
HLT2
HLT3
HLT4
ICbias
ICbias
LHT1
LHT2
LHT3
LHT4
LLsum
LLsum
LLT1
LLT2
LLT3
LLT4 Page 98
Vbias
Vbias
Vbs
VbsVin1
Vin2
Vin3
Vin4
Vref1
Vref2
Vref3
Vref4
VTbias
VTbias
Include models
pg.101Page 103
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Gary S. Varner, PhD
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:Discrim_hl_oct Page:Page0
Info:A octal of Discrim. channelsModified:Oct 23, 2002 06:56:26Created:Nov 3, 1999 09:33:45
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
ICbi
as
ICbi
as
HLH8HHH8HLL8HHL8
HLH7HHH7HLL7HHL7
HLT8HHT8LLT8LHT8
HLT7HHT7LLT7
Vref8
Vref7LHT7
Vin7
Vin8Vb
ias
HLT6HHT6LLT6LHT6
HLH6HHH6HLL6HHL6
HLH5HHH5
HLT5HHT5LLT5
Vref6
HLL5HHL5
Vref5
LLsu
m
LHT5
Vin5
Vbs
Vin6
VTbi
asHLH4HHH4HLL4HHL4
HLH3HHH3HLL3HHL3
HLT4HHT4LLT4LHT4
HLT3HHT3LLT3
Vref4
Vref3LHT3
Vin3
Vin4
Vbia
s
HLT2HHT2LLT2LHT2
HLH2HHH2HLL2HHL2
HLH1HHH1
HLT1HHT1LLT1
Vref2
HLL1HHL1
Vref1
LLsu
mLHT1
Vin1Vb
s
Vin2
SCA Page 199
Set of 8 Discrim blocks (Discrim_hl_oct)
VTbi
as
HLout
.param l=0.12u
Size: 5x7Size: 5x7Created:Nov 3, 1999 09:33:45Modified:Oct 23, 2002 06:56:26
Info:A octal of Discrim. channels
Page:Page0Module:Discrim_hl_oct
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner, PhD
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='4*l'M=16
TESDN W='297*l'
BONDING
p.301PAD
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Info:Modified MOSIS AMI/HP 0.5um Hi-ESD Pad Lib
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:PadARef Page:Page0
Modified:Sep 6, 2003 08:31:22Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='4*l'M=16
TESDP W='297*l'
Page 201
Page 201
PadARef SIGNALSIGNALPadARef
SIGNAL SIGNAL.param l=0.12u
W='297*l'TESDN
M=16L='4*l'
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 6, 2003 08:31:22
Page:Page0Module:PadARef
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Info:Modified MOSIS AMI/HP 0.5um Hi-ESD Pad Lib
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='297*l'TESDP
M=16L='4*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
PadBidirHE_SCMOS
Page 210
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Info:MOSIS AMI/HP 0.5um Hi-ESD Pad Lib
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:PadInC Page:Page0
Modified:Sep 6, 2003 09:16:09Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
RawDataIn
RawDataInPage 202
Page 202
Pad
DataIn
DataInB
PadInC DataInBPadInC_SCMOS
DataInPad
.param l=0.12u
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 6, 2003 09:16:09
Page:Page0Module:PadInC
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Info:MOSIS AMI/HP 0.5um Hi-ESD Pad Lib
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
BONDING
p.301PAD
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Module:PadGnd Page:Page0
Designer:Gary S. Varner
Info:MOSIS AMI/HP 0.5um Hi-ESD Pad LibModified:Sep 6, 2003 09:16:09Created:Sep 19, 1995 11:30:18
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='4*l'M=16
TESDP W='297*l'
Page 203
PadGnd
Page 203
Pad
PadGnd
.param l=0.12u
Size: 5x7Created:Sep 19, 1995 11:30:18Modified:Sep 6, 2003 09:16:09
Info:MOSIS AMI/HP 0.5um Hi-ESD Pad Lib
Designer:Gary S. Varner
Page:Page0Module:PadGnd
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='297*l'TESDP
M=16L='4*l'
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
L='4*l'M=16
TESDN W='297*l'
BONDING
p.301PAD
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Module:PadVdd Page:Page0
Designer:Gary S. Varner
Info:MOSIS AMI/HP 0.5um Hi-ESD Pad LibModified:Sep 6, 2003 09:16:09Created:Sep 19, 1995 11:35:20
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Page 204
PadVdd
Page 204
Pad
PadVdd
.param l=0.12u
W='297*l'TESDN
M=16L='4*l'
Size: 5x7Created:Sep 19, 1995 11:35:20Modified:Sep 6, 2003 09:16:09
Info:MOSIS AMI/HP 0.5um Hi-ESD Pad Lib
Designer:Gary S. Varner
Page:Page0Module:PadVdd
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
PadBidirHE_SCMOS
Page 210
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Info:MOSIS AMI/HP 0.5um Hi-ESD Pad Lib
Designer:Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:PadOut Page:Page0
Modified:Sep 6, 2003 08:11:05Created:Sep 15, 1995 09:05:31
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
Page 205
Page 205
DataOut PadPadOut
Pad
DataOut
PadOut
.param l=0.12u
Size: 5x7Created:Sep 15, 1995 09:05:31Modified:Sep 6, 2003 08:11:05
Page:Page0Module:PadOut
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Gary S. Varner
Info:MOSIS AMI/HP 0.5um Hi-ESD Pad Lib
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
BONDING
p.301PAD
BONDING
p.301PAD
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Info:High Frequency (microstrip) 50 Ohm input
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:PadHFpair Page:Page0
Modified:Sep 6, 2003 08:31:22Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
HFREFHFREF
PadHFpair
Page 208
SIGNAL SIGNAL
HFREF
SIGNALSIGNAL
PadHFpair
Page 208
HFREF.param l=0.12u
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 6, 2003 08:31:22
Page:Page0Module:PadHFpair
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Info:High Frequency (microstrip) 50 Ohm input
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
PadBidirHE_0.25umPage 211
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Info:MOSIS AMI/HP Hi-ESD Pad Lib
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:PadBidirHE Page:Page0
Modified:Sep 6, 2003 09:16:09Created:May 5, 1993 21:36:43
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
RawDataIn
RawDataIn
Page 210
Page 210
PadBidirHE below.
no information for exporting to Spice.It can be used for TPR, however it contains
to Spice, instance the appropriateIn order to specify a technology for exporting
implementation of the Bidirectional Pad.This module is the technology independent
Pad
DataIn
DataInB
DataOut
OE
DataIn
DataInB
DataOut
OE Pad
PadBidirHE_SCMOS
Bidirectional Pad
.param l=0.12u
Size: 5x7Created:May 5, 1993 21:36:43Modified:Sep 6, 2003 09:16:09
Page:Page0Module:PadBidirHE
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Info:MOSIS AMI/HP Hi-ESD Pad Lib
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
p.302 p.302
p.302 p.302
L='3*l'T13b W='30*l'
L='3*l'M=5
T3 W='30*l'
L='3*l'M=4
T5 W='30*l'
L='3*l'M=5
T6 W='30*l'L='4*l'M=15
TESDN2 W='297*l'L='3*l'M=6
T10 W='30*l'L='3*l'M=6
T12 W='30*l'
L='3*l'T14b W='30*l'
L='4*l'M=1
TESDN1 W='297*l'
BONDING
p.301PAD
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Created:May 5, 1993 21:36:43
Info:0.25um Bi-directional digital padModified:Sep 6, 2003 09:16:09
Module:Pad_BidirHE_0.25u Page:Page0
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T13a W='52*l'
L='3*l'M=5
T1 W='52*l'
L='3*l'M=4
T2 W='52*l'
L='3*l'M=5
T4 W='52*l'L='4*l'M=12
TESDP2 W='297*l'L='3*l'M=6
T9 W='52*l'L='3*l'M=6
T11 W='52*l'
L='3*l'T14a W='52*l'
L='4*l'M=4
TESDP1 W='297*l'
R=231
OE
export or for Spice export.This pad can be used either for TPR DataIn
DataInB
DataOut
Pad
PadBidirHE_0.25um
OEB
OEB
OEB
OE
OE
TSMC 0.25u MOSIS TechnologyHi-ESD Bidirectional Pad
Data
In
Data
InB
Pad
DataOut
EN
EN
RawD
ataI
n
Page 211
Page 211
RawDataIn
W='30*l'T13bL='3*l'
W='30*l'T3
M=5L='3*l'
W='30*l'T5
M=4L='3*l'
W='30*l'T6
M=5L='3*l'
W='297*l'TESDN2
M=15L='4*l'
W='30*l'T10
M=6L='3*l'
W='30*l'T12
M=6L='3*l'
W='30*l'T14bL='3*l'
W='297*l'TESDN1
M=1L='4*l'
Size: 5x7
Page:Page0Module:Pad_BidirHE_0.25u
Modified:Sep 6, 2003 09:16:09Info:0.25um Bi-directional digital pad
Created:May 5, 1993 21:36:43
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='52*l'T13aL='3*l'
W='52*l'T1
M=5L='3*l'
W='52*l'T2
M=4L='3*l'
W='52*l'T4
M=5L='3*l'
W='297*l'TESDP2
M=12L='4*l'
W='52*l'T9
M=6L='3*l'
W='52*l'T11
M=6L='3*l'
W='52*l'T14aL='3*l'
W='297*l'TESDP1
M=4L='4*l'
R=231
P_4 / N_4: P / N-channel MOSFET
L: Gate Length (l).AS / AD: Source/Drain Area A=W*L*l*l (l)
A: Area (squm).
P: parameter (um).PS /PD: Source/Drain parameter P=(W+L)*2*l (l)
W: Gate Width (l).
<< Devices and Process Parameters >>
be placed on top level of the design hierarchy.For SPICE Export, this .param statement must
l: the layout unit / scale factor (um).
.param l=0.12u
Include models
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Module:PadGndNC Page:Page0
Designer:Gary S. Varner
Info:Synthesized padless spacerModified:Sep 6, 2003 08:31:22Created:Sep 19, 1995 11:30:18
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='4*l'M=16
TESDP W='297*l'
PadGndNCPage 213
Padless Ground Connect Spacer
Page 213
PadGndNC
.param l=0.12u
Size: 5x7Created:Sep 19, 1995 11:30:18Modified:Sep 6, 2003 08:31:22
Info:Synthesized padless spacer
Designer:Gary S. Varner
Page:Page0Module:PadGndNC
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='297*l'TESDP
M=16L='4*l'
Page 401
C=0.1866pF
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7Created:Aug 15, 1996 10:36:13
Designer:Dr. Gary S. Varner
Info:Bonding pad physical definitionModified:Sep 6, 2003 09:16:09
Module:Pad_Bond Page:Page0
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
p.301
Page 301
Pad_BondBONDING
PADSIGNALSIGNAL
SIGNAL
C=0.1866pF
Size: 5x7
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Page:Page0Module:Pad_Bond
Modified:Sep 6, 2003 09:16:09Info:Bonding pad physical definition
Designer:Dr. Gary S. Varner
Created:Aug 15, 1996 10:36:13
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
L='3*l'T2 W='30*l'
A
A B
B C
C D
D E
E F
F
1 1
22
3 3
44
5 5
G
G
Size: 5x7
Designer:Dr. Gary S. Varner
Path:C:\CustomIC\STRAW3\STRAW3
Rev A
Module:PadBidir_Inv Page:Page0
Info:Inverter (TIB) for IO PadModified:Sep 6, 2003 09:16:09Created:May 5, 1993 21:36:41
Instrument Development Lab (IDL)University of Hawai'i, Manoa Tel: (808)956-2920
2505 Correa Road, Honolulu, HI 96822Fax: (808)956-2930
L='3*l'T1 W='52*l'
p.302
Page 302
Generic digital IO InverterInv
A Out
A Out
W='30*l'T2L='3*l'
Size: 5x7Created:May 5, 1993 21:36:41Modified:Sep 6, 2003 09:16:09
Info:Inverter (TIB) for IO Pad
Page:Page0Module:PadBidir_Inv
Rev A
Path:C:\CustomIC\STRAW3\STRAW3
Designer:Dr. Gary S. Varner
Fax: (808)956-29302505 Correa Road, Honolulu, HI 96822
Tel: (808)956-2920
W='52*l'T1L='3*l'