Subnano Time to Digital Converter implemented in PARISROC for PMm² R&D

program

IPN Orsay: IN2P3-CNRS-Université Paris Sud 11 http://ipnweb.in2p3.fr

S. Drouet, B. Genolini, B.Y. Ky, T. Nguyen Trung, J. Peyré, J. Pouthas, P. Rosier, E.Wanlin

ANR-06-BLAN-0186LAPP Annecy: IN2P3-CNRS-Université de Haute Savoiehttp://lappweb.in2p3.fr

D. Duchesneau, N. Dumont-Dayot, J. Favier, R. Hermel, J. Tassan-Viol, A. Zghiche

Université Libre de Bruxelleshttp://www.ulb.ac.be

K. Hanson

LAL Orsay: IN2P3-CNRS-Université Paris Sud 11 http://www.lal.in2p3.fr

J.-E. Campagne, S. Conforti, F. Dulucq, M. El BerniC. de La Taille, G. Martin-Chassard

Special Cares

Design: Ramp generator linearity Charge injection in memory cells: Optimization of switch sizes Immunity of a cell relative to switching neighbour cells

Layout: Centroid layout for the amplifier input pairs Mirroring of the 2 TDC ramp generators Dedicated power suppliesThe goal of these special cares is to minimize mismatching and obtain the same charateristics on each ramp. And as the ramps work in opposition phase, the reset zone of one ramp must have the lowest possible impact on the other.

Tests and ResultsRamps reconstruction, noise and INL measurements:

Mean of 10 000 data each ns Max.Noise = 322 ps RMS INL = 2 ch 450 ps

Time measurement of 10 kHz signal Visualization of Ramps with oscilloscope

TDC Ramp Generator Architecture: a simple current source and an integrator. Loads: 16 channels 32 T&H cells with independent switching (1 T&H = 500 fF) Load variation: from 0 to 16 pF on each ramp generator Constraint: Charge variation do not have to perturb the linear zone of a ramp Ramp Slope: 10 mV / ns Ramp Dynamic: 1.4 V / 140 ns Usable Ramp Dynamic: 1 V / 100 ns Target resolution: 100 ps

http://pmm2.in2p3.fr

Topical Workshop on Electronics for Particle Physics 2010 — Aachen, Germany, 20-24 September, 2010

S. Drouet on behalf of the PMm2 collaboration

0 1 2 3 4 5 6 7 8 9 100

2

4

6

8

10

12

Scale Factor (Wn = 0.4 µm and Wp = 0.8 µm)

Err

or

Vari

ati

on in

mV

Simulation of the error variation due to charge injections in a T&H cell over the voltage dynamic

Optimisation

PARISROCPARISROC_v2 is a dedicated front-end ASIC for photomultiplier tubes designed by LAL/OMEGA group and by IPNO for the analog TDC.

AMS SiGe 0.35µm, size: 5 mm x 3.4 mm 16 independent channels Independent gain adjustment by channel Charge and time digitization Serial readout @ 40 MHz Charge: 0 to 300x106 electrons Efficiency from 106 e- input charge Virtual 12-bit ADC @ 40 MHz (10-bit Wilkinson ADC + 2 gains with automatic selection) Time measurement:

• Analog TDC: Dyn. = 100 ns, step 220 ps, resolution 425 ps RMS• Digital TDC: Dyn. = 1.67 s, step 100 ns (24 bits / 10 MHz)

Mirror sourcesIntegrators Dual-Ramp Generator Layout

0 20 40 60 80 100 120 140

-0.10%

-0.05%

0.00%

0.05%

0.10%

0.15%

Ramp INL(Gene Out)

Time in ns

INL<0.1 % FS (<100 ps) for 134 ns over 140 ns ramp

Analog TDC Principle2 ramps working in phase opposition with overlap zones. When one is in the reset zone, the other is in the linear zone. Therefore, the time measurement is possible without blind zone because, at least, always one of the two ramps is in a linear zone. A digital module, implemented in each channel, selects the valid TDC ramp.

When an event occurs, the 2 ramps are sampled at the same time in the Track&Hold cells and a logic module tags the valid one. Only the sample of the selected ramp is converted.

Functionnal Chronograms

Reset zone Non-linear zones

StartRampTDC from digital part

RampTDC 1

RampTDC 2

SelectTDCStartRampTDC delayed

Usable Ramp(Virtual view)

100ns

1V

140ns

16 Inputs

Variable GainPre-Amplifier

(2.5-40)High Gain

Gain Correction(8bits)

Variable GainPre-Amplifier

(0.25-4)Low Gain

CRRC2Slow Shaper

(25 , 50,100 ns)

CRRC2Slow Shaper

(25 , 50,100 ns)

Time constant(3bits)

Fast Shaper(15ns)

Depth 2 SCA Low Gain

Depth 2 SCA High Gain

OR

External Trigger

Trigger Output

Variable Delay6 bits

MUX

MUX

Discri

Gain Selection

10 bits DAC

10 bits DAC

TDC Ramp 1

TDC Ramp 2

Hold

Common to 16 channels

Depth 2 SCA Fine Time

Depth 2 SCA Fine Time

Ramp Selection

Discri

Serial data 51 bits

24 bits Timestamp Counter

10MHz

Wilkinson 10 BitsADC

40MHz

Read-out40MHz

Digital part

SCA management

Slow Control

4bits Channel24b Timestamp1b Counter1b Gain10b Fine Time1b Ramp10b Charge

Synoptic of PARISROC ASIC

0 50 100 150 200 250 300 350 400

300

350

400

450

500

550

600

650

700

750

Time in ns

AD

C C

hannel

Ramp1 & Ramp2 reconstruction

120 130 140 150 160 170 180 190 200 2100

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Time in ns

AD

C C

hannel

Ramp Noise

Noise.Cap1.Ramp1Noise.Cap2.Ramp1

99.9375 99.938 99.9385 99.939 99.9395 99.940 99.9405 99.941 99.94150

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2x 10

4CH0 Time Measurement

With TimeStamp and Ramp Corrections

Time in µs

Count

Mean = 99 939.340 nsStd = 425.00 ps

Injection:Periodical signal = 100 µs

0 10 20 30 40 50 60 70 80 90 100-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5CH0 Time - INL Ramp1 Cap2

AD

C C

hannel

Time in ns

Reset impact of Ramp2

StartRamp

I=5µA

C=500fF

ResetCMOS

Vslope

R=200kΩ

Vref

NMOS

Load 32 T&H cells

Ramp Slope = 5 µA / 500 fF = 10 mV / ns Bandgap provides Vref and Vslope

One Ramp Generator Schema

Discriminator

Principle

Track & Hold X2

Track & Hold X2

Mult

iple

xor

1 channel

To ADC

Event

RampTDC1

RampTDC2

Read

SC

Hold

Select good TDCD Q

Rst

StartRamp

Delay

Hold

Select good TDCstored

-10 -8 -6 -4 -2 0 20

1

2

3

4

5

6

Memorization error in a referred cell with 31 cells switching at the same

time

Self+Cbias+Cc4pF+Cload4pF+4W Orignal TDC

Time in ns

Err

or

in m

V

PARISROC Layout