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Tessent® Scan & ATPG

Student Workbook

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Table of Contents

Tessent Scan and ATPG I

Module 1: Basic Concepts ....................................................................................... 2

Objectives ............................................................................................................................................. 2

Why Test? ............................................................................................................................................ 2

Manufacturing Defects ......................................................................................................................... 2

Types of Test ........................................................................................................................................ 2

What Is Test? ........................................................................................................................................ 2

Fault Models ......................................................................................................................................... 2

Fault Models and Test Patterns ............................................................................................................ 2

Automatic Test Pattern Generation (ATPG) ........................................................................................ 2

Additional Fault Models ....................................................................................................................... 2

Layout-Aware Bridge Fault Model ...................................................................................................... 2

Bridge Fault: Multiple Detection ......................................................................................................... 2

Bridge Fault: N-Detect ......................................................................................................................... 2

Bridge Fault: Embedded Multi-Detect ................................................................................................. 2

Comparison – Multiple detection ......................................................................................................... 2

At-Speed Fault Models: Transition ...................................................................................................... 2

At-Speed Fault Models: Path Delay ..................................................................................................... 2

User-Defined Fault Models (UDFM)/Cell-Aware UDFM .................................................................. 2

IDDQ Fault Model ............................................................................................................................... 2

Scan Test .............................................................................................................................................. 2

Scan Flip-Flops/Scan Cells .................................................................................................................. 2

Basic Scan Test — Overview ............................................................................................................... 2

Basic Scan Test .................................................................................................................................... 2

Basic Scan Test Review ....................................................................................................................... 2

Table of Contents

Tessent Scan and ATPG II

Overview: Tessent Shell ....................................................................................................................... 2

Tessent Shell: Contexts and Modes ..................................................................................................... 2

Invocation, System Modes and Contexts ............................................................................................. 2

Contexts ................................................................................................................................................ 2

Command Syntax and Structure ........................................................................................................... 2

Invoking FastScan Inside of Tessent Shell .......................................................................................... 2

Getting Help With Tessent Tools ......................................................................................................... 2

Accessing UNIX Commands From the Tool Command Line ............................................................. 2

Getting Help: Useful Tool and System Commands ............................................................................. 2

Review .................................................................................................................................................. 2

Lab 1: Exploring the Help System ....................................................................................................... 2

Module 2: ATPG Flow ............................................................................................ 2

Objectives ............................................................................................................................................. 2

Full DFT Flow in Tessent Shell ........................................................................................................... 2

DFT Library ......................................................................................................................................... 2

Creating a DFT Library ........................................................................................................................ 2

Automatic Generation of DFT Libraries .............................................................................................. 2

Black Boxes .......................................................................................................................................... 2

Auto Black Boxing for Incomplete Netlists ......................................................................................... 2

Black Box Examples ............................................................................................................................ 2

ATPG Setup ......................................................................................................................................... 2

Test Procedure File ............................................................................................................................... 2

Test Procedure File: Timeplates ........................................................................................................... 2

Test Procedure Example File: Setup, Load_Unload ............................................................................ 2

Test Procedure File: force_sci and measure_sco ................................................................................. 2

Table of Contents

Tessent Scan and ATPG III

Dofile .................................................................................................................................................... 2

Dofile: Scan Chain Definition .............................................................................................................. 2

Dofile: Clock/Control Signal Definition .............................................................................................. 2

DC Scan Insertion Flow ....................................................................................................................... 2

DC Scan Insertion ................................................................................................................................ 2

ATPG Process ...................................................................................................................................... 2

ATPG Process: Setup ........................................................................................................................... 2

ATPG Process: DRCs .......................................................................................................................... 2

DRCs .................................................................................................................................................... 2

ATPG Process: Configuring ATPG ..................................................................................................... 2

ATPG Process: Generate Patterns ........................................................................................................ 2

ATPG Process: Save Results ................................................................................................................ 2

Lab 2: Generating Test Patterns ........................................................................................................... 2

Module 3: Fault Grouping, Coverage, and Transcripts ...................................... 2

Objectives ............................................................................................................................................. 2

Faults .................................................................................................................................................... 2

Fault Locations ..................................................................................................................................... 2

Specifying the Fault Universe: Add Faults .......................................................................................... 2

Specifying the Fault Universe: Excluding Faults ................................................................................. 2

Specifying the Fault Universe: Fault Sampling ................................................................................... 2

Fault Classes ......................................................................................................................................... 2

Fault Class(TE): Detect By Implication (DI) ....................................................................................... 2

Fault Class(TE): Detected By Simulation (DS) ................................................................................... 2

Fault Class(TE): Possible Detected Faults (PT, PU) ............................................................................ 2

Fault Class(TE): ATPG Untestable (AU) ............................................................................................ 2

Table of Contents

Tessent Scan and ATPG IV

Fault Class(TE): Uncontrolled (UC) and Unobserved(UO) ................................................................ 2

Fault Class(TE): UC, UO and Aborted Faults ..................................................................................... 2

Fault Class(UT): Untestable Faults ...................................................................................................... 2

Fault Class(UT): Unused (UU) ............................................................................................................ 2

Fault Class(UT): Tied (TI) ................................................................................................................... 2

Fault Class(UT): Blocked (BL) ............................................................................................................ 2

Fault Class(UT): Redundant (RE) ........................................................................................................ 2

Fault Class: Review .............................................................................................................................. 2

Test Coverage Reporting: Metrics ....................................................................................................... 2

Calculating Testability ......................................................................................................................... 2

Transcript/Logfile Overview ................................................................................................................ 2

Understanding the Logfile .................................................................................................................... 2

Logfile Review, ATPG Warnings, and Auto Adjustment ................................................................... 2

Lab 3: Understanding ATPG Messaging ............................................................................................. 2

Module 4: Additional Test Pattern Types ............................................................. 2

Objectives ............................................................................................................................................. 2

ATPG Test Pattern Types .................................................................................................................... 2

Basic Scan Patterns — Review ............................................................................................................ 2

Clock Sequential Patterns ..................................................................................................................... 2

Clock Sequential Pattern Operation ..................................................................................................... 2

Clock PO Patterns ................................................................................................................................ 2

Traditional: Testing Around RAMs ..................................................................................................... 2

Structured Test With RAMs ................................................................................................................. 2

Elements of a RAM .............................................................................................................................. 2

Control Signals for RAMs .................................................................................................................... 2

Table of Contents

Tessent Scan and ATPG V

RAM Sequential Patterns ..................................................................................................................... 2

Example: Using RAM Sequential Patterns to Test RAMs .................................................................. 2

Example2: Using RAM Sequential Patterns for Test ........................................................................... 2

Generating Optimum Test Patterns ...................................................................................................... 2

Report Patterns ..................................................................................................................................... 2

Report Scan Cells ................................................................................................................................. 2

Labeling Memory Elements in report_scan_cells ................................................................................ 2

Scan Cell Inversion Flags ..................................................................................................................... 2

Writing Patterns .................................................................................................................................... 2

Reuse and Debugging ........................................................................................................................... 2

Reuse and Debugging: ASCII and Binary Formats ............................................................................. 2

Reuse and Debugging: Reading Pattern Files ...................................................................................... 2

Overview: Time-Based Verification .................................................................................................... 2

Time-Based Verification: TestBench Creation .................................................................................... 2

Time-Based Verification (Change Pattern Timing) ............................................................................. 2

Manufacturing Test Patterns ................................................................................................................ 2

Lab 4: Understanding Test Pattern Generation .................................................................................... 2

Module 5: At-Speed Patterns and On-Chip Clock Controllers .......................... 2

Objectives ............................................................................................................................................. 2

Review: Fault Models .......................................................................................................................... 2

At-Speed: Transition and Path Delay Faults ........................................................................................ 2

Transition Fault Model ......................................................................................................................... 2

Default Observation of Transition Faults ............................................................................................. 2

False Paths ............................................................................................................................................ 2

Multicycle Paths ................................................................................................................................... 2

Table of Contents

Tessent Scan and ATPG VI

Path Delay Fault Model ........................................................................................................................ 2

Path Definition Files ............................................................................................................................. 2

Path Delay Pattern Flow ....................................................................................................................... 2

At-Speed Pattern Generation ................................................................................................................ 2

Launch-Off-Capture or Broadside ....................................................................................................... 2

Launch-Off-Shift: Basic Combinational .............................................................................................. 2

Launch-Off-Shift .................................................................................................................................. 2

At-Speed Test: Generating Internal Clocks ......................................................................................... 2

Controlling Clocks During Shift and Capture ...................................................................................... 2

Defining OCC functionality for ATPG ................................................................................................ 2

Clock Control Definitions (CCD) ........................................................................................................ 2

Per-Cycle and Sequence Clock Control Support ................................................................................. 2

Example: ATPG_CYCLE .................................................................................................................... 2

Example: ATPG_SEQUENCE ............................................................................................................ 2

Keywords (Clock Control Definitions) ................................................................................................ 2

Procedure to use CCD for ATPG ......................................................................................................... 2

Pattern Verification .............................................................................................................................. 2

write_procedure_testbench ................................................................................................................... 2

Named Capture Procedure (NCP) ........................................................................................................ 2

What are Named Capture Procedures (NCP)? ..................................................................................... 2

NCP Links External With Internal Signals .......................................................................................... 2

Components of NCP With External and Internal Modes ..................................................................... 2

Details of External and Internal Modes: Timeplates ............................................................................ 2

Details of External and Internal Modes: External ................................................................................ 2

Details of External and Internal Modes: Internal ................................................................................. 2

Table of Contents

Tessent Scan and ATPG VII

Selection With Condition Statements .................................................................................................. 2

NCP With Condition Statements .......................................................................................................... 2

Use ATPG Engine to Define NCP ....................................................................................................... 2

Named Capture Procedure Rules ......................................................................................................... 2

IDDQ Patterns ...................................................................................................................................... 2

Creating a Single Test Pattern File ....................................................................................................... 2

Lab 5: Testing for High Quality .......................................................................................................... 2

Module 6: Design Rule Overview .......................................................................... 2

Objectives ............................................................................................................................................. 2

ATPG: Flat Model Creation ................................................................................................................. 2

ATPG: Learning Analysis .................................................................................................................... 2

ATPG Design Rule Checking (DRC) .................................................................................................. 2

Review: Clocks .................................................................................................................................... 2

Clock Cones ......................................................................................................................................... 2

C1 DRC ................................................................................................................................................ 2

C1 DRC Investigation .......................................................................................................................... 2

Handling C1 Violations ........................................................................................................................ 2

C3/C4 DRC .......................................................................................................................................... 2

Handling C3 and C4 Violations ........................................................................................................... 2

C6 DRC ................................................................................................................................................ 2

C6 Investigation ................................................................................................................................... 2

Handling C6 Violations ........................................................................................................................ 2

C3/C4/C6 Recap ................................................................................................................................... 2

D1 DRC: Data Disturbed ..................................................................................................................... 2

D5 DRC ................................................................................................................................................ 2

Table of Contents

Tessent Scan and ATPG VIII

D5 DRC: Reporting Options ................................................................................................................ 2

D5 DRC: Summary .............................................................................................................................. 2

D6 DRC: Non-Scan Latches ................................................................................................................ 2

E4 DRC: Contention Check During Load_Unload .............................................................................. 2

E4 DRC Solution: Force Bidirectional Pins to Z ................................................................................. 2

E5 DRC: X States Propagate to Observation Point .............................................................................. 2

E10 DRC: Bus Contention ................................................................................................................... 2

Trace Rule DRCs: Scan Chain Tracing ................................................................................................ 2

T3 DRC: Scan Chain Trace Rules ........................................................................................................ 2

Scan Chain Trace Rules: T4, T5 .......................................................................................................... 2

T24 DRC: Missing Lockup Cell .......................................................................................................... 2

DRC Debug: Reporting ........................................................................................................................ 2

DRC Debug: Viewing .......................................................................................................................... 2

DRC Debug: Reporting and Viewing .................................................................................................. 2

DRC Debug: Gate Reporting ............................................................................................................... 2

State Stability Analysis ........................................................................................................................ 2

Lab 6: Troubleshooting DRCs ............................................................................................................. 2

Module 7: Troubleshooting Low Test Coverage .................................................. 2

Objectives ............................................................................................................................................. 2

Sources of Low Coverage .................................................................................................................... 2

Identifying Areas of Low Coverage ..................................................................................................... 2

Assessing the Problem ......................................................................................................................... 2

Assessing the Problem in DFTVisualizer ............................................................................................ 2

Analyze Faults in DFTVisualizer ......................................................................................................... 2

Report Faults in DFTVisualizer ........................................................................................................... 2

Table of Contents

Tessent Scan and ATPG IX

Analyzing Causes of Low Coverage (Stuck-at Fault) ......................................................................... 2

Uncontrolled and Unobserved Faults ................................................................................................... 2

Aborted Faults ...................................................................................................................................... 2

Addressing Aborted Faults ................................................................................................................... 2

Fault-by-Fault UC Debugging: report_faults Command ..................................................................... 2

Fault-by-Fault UC Debugging: analyze_fault Command .................................................................... 2

Fault-by-Fault UC Debugging: report_test_stimulus Command ......................................................... 2

Faults Class: ATPG Untestable ............................................................................................................ 2

Tools for Debugging AU Faults: set_gate_report Command .............................................................. 2

Constrain State Reporting .................................................................................................................... 2

Tools for Debugging AU Faults: Stuck-at Faults ................................................................................. 2

Tools for Debugging AU Faults: Transition Faults ............................................................................. 2

Debugging Transition/Path Delay Faults: Cell Constraints Can Prevent Detection ........................... 2

Debugging Transition/Path Delay Faults: Perform a Stuck-at Test for Sites Along Path .................. 2

Adding Primary Input Points For Investigation ................................................................................... 2

ATPG Event Simulation ....................................................................................................................... 2

Event Simulation: DFFs and Latches ................................................................................................... 2

Example 1: Reporting Pattern Index .................................................................................................... 2

Example 2: Reporting Parallel Pattern 0 .............................................................................................. 2

Example 3: DRC Pattern Load_Unload ............................................................................................... 2

Lab 7: Troubleshooting Low Coverage ............................................................................................... 2

Module 8: Simulation Mismatch ............................................................................ 2

Objectives ............................................................................................................................................. 2

Verilog Testbenches ............................................................................................................................. 2

Parameter Options for the Verilog Testbench ...................................................................................... 2

Table of Contents

Tessent Scan and ATPG X

Controlling Messaging ......................................................................................................................... 2

SIM_VECTYPE_SIGNAL .................................................................................................................. 2

Serial Testbench ................................................................................................................................... 2

Serial Pattern Verification .................................................................................................................... 2

Parallel Verilog Testbench ................................................................................................................... 2

Testbenches: Recommended Simulation Order ................................................................................... 2

Simulation Mismatches: Steps ............................................................................................................. 2

Required Debug Files ........................................................................................................................... 2

Mismatch Report .................................................................................................................................. 2

Shift or Capture Problem? .................................................................................................................... 2

Parallel Testbench Mismatch ............................................................................................................... 2

Parallel Testbench Trace Back ............................................................................................................. 2

Typical Distribution of Problem Types ................................................................................................ 2

Possible Mismatch Causes: Clock Skew Problems .............................................................................. 2

Possible Mismatch Causes: Timing Violations .................................................................................... 2

Possible Mismatch Causes: DRC Violations ....................................................................................... 2

Possible Mismatch Causes: Library Problems ..................................................................................... 2

Modeling Abstraction ........................................................................................................................... 2

Library Verification Flow .................................................................................................................... 2

Library Verification With LibComp .................................................................................................... 2

Possible Mismatch Causes: Modeling Issues ....................................................................................... 2

Possible Mismatch Causes: Mux Model Pessimism ............................................................................ 2

Possible Mismatch Causes: ROM / RAM Initialization Data .............................................................. 2

Possible Mismatch Causes: Weak Pulls ............................................................................................... 2

Possible Mismatch Causes: Black Boxes ............................................................................................. 2

Table of Contents

Tessent Scan and ATPG XI

Possible Mismatch Causes: Simulation Settings .................................................................................. 2

X Clock Handling ................................................................................................................................. 2

Bus Simulation ..................................................................................................................................... 2

Set Z Handling ..................................................................................................................................... 2

Possible Mismatch Causes: Internal Primary Inputs ............................................................................ 2

Pattern Masking .................................................................................................................................... 2

Automatic Simulation Mismatch Analysis Flow ................................................................................. 2

Analyze Simulation Mismatches .......................................................................................................... 2

ModelSim Invocation Script ................................................................................................................ 2

Report Mismatch Sources Command ................................................................................................... 2

Lab 8: Debug Simulation Mismatches ................................................................................................. 2

Module 9: Compression .......................................................................................... 2

Objectives ............................................................................................................................................. 2

Understanding the ATPG Process ........................................................................................................ 2

Standard Test Application Process ....................................................................................................... 2

ATPG-Based Compression Techniques ............................................................................................... 2

Static Compression ............................................................................................................................... 2

Dynamic Compression ......................................................................................................................... 2

Clock Domain Analysis and Clock Merging ....................................................................................... 2

Multiple Clock Capture per Pattern ..................................................................................................... 2

ATPG Create Patterns Command ........................................................................................................ 2

Balanced Scan Chains .......................................................................................................................... 2

Short Scan Chains ................................................................................................................................ 2

Embedded Deterministic Test (EDT) ................................................................................................... 2

Basic Terminology ............................................................................................................................... 2

Table of Contents

Tessent Scan and ATPG XII

Data Volume and Test Application Time ............................................................................................ 2

EDT Reduces Test Data Volume and Application Time ..................................................................... 2

ATPG With EDT .................................................................................................................................. 2

EDT Test Application Process ............................................................................................................. 2

Example Results of EDT ...................................................................................................................... 2

The Decompressor ................................................................................................................................ 2

Decompressor — Representative Block Diagram................................................................................ 2

Test Pattern Decompression ................................................................................................................. 2

The Compactor ..................................................................................................................................... 2

EDT Compression Inside of Tessent Shell .......................................................................................... 2

Tessent Shell EDT Flows and Usage ................................................................................................... 2

EDT Logic Creation ............................................................................................................................. 2

Post-Synthesis Internal Logic Insertion ............................................................................................... 2

Lab 9: Introduction to Tessent ｮ TestKompress ｮ ................................................................................ 2

Module 10: Scan and Test Insertion ...................................................................... 2

Objectives ............................................................................................................................................. 2

Tessent Scan Tool Flow: An Overview ............................................................................................... 2

Tessent Scan Tool Flow With Commands ........................................................................................... 2

DFT Library ......................................................................................................................................... 2

SETUP: Scan Cell Mapping ................................................................................................................. 2

SETUP: Input Constraints .................................................................................................................... 2

SETUP: Adding Clocks ....................................................................................................................... 2

SETUP: Scan/Test Logic Configuration .............................................................................................. 2

SETUP: Defining Pin Connections ...................................................................................................... 2

SETUP: Adding Test Logic ................................................................................................................. 2

Table of Contents

Tessent Scan and ATPG XIII

SETUP: Set Test Logic Configuration (Defining Non-Scan Areas) .................................................... 2

SETUP: Scan Specific DRCs ............................................................................................................... 2

ANALYSIS: Scan/Test Logic Insertion ............................................................................................... 2

ANALYSIS: Saving Scan Inserted Design .......................................................................................... 2

Leading Edge / Trailing Edge Scan Cells ............................................................................................ 2

One Chain — 2 Clocks ......................................................................................................................... 2

Balancing Scan Chains ......................................................................................................................... 2

Hierarchical Scan Insertion .................................................................................................................. 2

Scan Chain Family ............................................................................................................................... 2

Simple Example of 2 Scan Modes ....................................................................................................... 2

Examples: multi-mode Scan Insertion ................................................................................................. 2

Example for Analyze and Introspect .................................................................................................... 2

Comparing Old Usage with HSI .......................................................................................................... 2

Dofile Translator .................................................................................................................................. 2

Tessent Scan Tool Flow: Using TSDB Option .................................................................................... 2

Read_design and Import_scan_mode ................................................................................................... 2

Tessent ScanPro ................................................................................................................................... 2

What are Test Points? ........................................................................................................................... 2

EDT Test Points ................................................................................................................................... 2

How EDT Test Points Work ................................................................................................................ 2

Module 10: Optional Labs .................................................................................................................... 2

Module 11: Additional Test Methodologies and Topics ...................................... 2

Objectives ............................................................................................................................................. 2

User Defined Fault Model (UDFM) ..................................................................................................... 2

ATPG Model - Review ........................................................................................................................ 2

Table of Contents

Tessent Scan and ATPG XIV

User Defined Fault Model: Test Alternatives ...................................................................................... 2

User Defined Fault Model: Cell-Aware ............................................................................................... 2

Cell-Aware Model Creation: Layout Extraction .................................................................................. 2

Cell-Aware Model Creation: Fault Simulation .................................................................................... 2

Cell-Aware Model Creation: Usage ..................................................................................................... 2

More Information ................................................................................................................................. 2

Low Power / Power Aware ATPG ....................................................................................................... 2

Control and Observe Test Cube (Review) ........................................................................................... 2

Reducing Switching Activity: Shift (Non-EDT) ................................................................................. 2

Reducing Switching Activity: Shift (EDT) ......................................................................................... 2

Limiting Switching During Capture (EDT and Non-EDT) ................................................................. 2

Basic Usage Flow for Low Power ATPG (EDT) ................................................................................. 2

EDT Power Control Block Diagram .................................................................................................... 2

Load/Response Shift Switching Activity ............................................................................................. 2

Low Power ATPG Flow ....................................................................................................................... 2

Example 1: Power Metrics Reporting .................................................................................................. 2

Example 2: Power Metrics Reporting .................................................................................................. 2

Example 3: Power Metrics Reporting .................................................................................................. 2

Example 4: Pattern Filtering ................................................................................................................ 2

Low-Power / Power-Aware Test Flow ................................................................................................. 2

IEEE1801 (UPF 2.0) and CPF 1.1 ....................................................................................................... 2

Usage Overview ................................................................................................................................... 2

Test Sequencing ................................................................................................................................... 2

Testing Low Power Components ......................................................................................................... 2

More Information ................................................................................................................................. 2

Table of Contents

Tessent Scan and ATPG XV

On-Chip Clock Control (OCC) Requirements ..................................................................................... 2

Design Placement ................................................................................................................................. 2

Primary Clock Control Functions ........................................................................................................ 2

Standard Clock Controller Schematic .................................................................................................. 2

Functional Mode Operation ................................................................................................................. 2

Programmable Length Shift Register ................................................................................................... 2

Shift Mode ............................................................................................................................................ 2

Slow Capture Mode .............................................................................................................................. 2

Timing Diagram for Slow Capture Mode ............................................................................................ 2

Scan Enable Synchronization ............................................................................................................... 2

Fast Capture Mode ............................................................................................................................... 2

Timing Diagram for Fast Capture Mode .............................................................................................. 2

Tessent On-Chip Clock Controller ....................................................................................................... 2

Accessing Support Center Material ...................................................................................................... 2

Customer Support ................................................................................................................................. 2

Related Courses .................................................................................................................................... 2

Hierarchical DFT Overview ................................................................................... 2

Objectives ............................................................................................................................................. 2

DFT Challenges in Large SoCs ............................................................................................................ 2

Divide & Conquer with Hierarchical DFT ........................................................................................... 2

Top-level Flat ATPG vs. Hierarchical ATPG ...................................................................................... 2

Hierarchical DFT Flow Overview ........................................................................................................ 2

Manufacturing Test .............................................................................................................................. 2

Pattern Retargeting Commands ............................................................................................................ 2

Hierarchical Fault Accounting ............................................................................................................. 2

Table of Contents

Tessent Scan and ATPG XVI

Scan Test Diagnosis ............................................................................................................................. 2

Hierarchical Scan Test Diagnosis Flow ............................................................................................... 2

Hierarchical Scan Test Diagnosis Considerations ............................................................................... 2

Graybox Model Usage ......................................................................................................................... 2

Graybox Generation Command ........................................................................................................... 2

Why Are Wrapper Chains Required for Hierarchical? ........................................................................ 2

Hierarchical DFT – Wrapper Chains ................................................................................................... 2

Hierarchical DFT – Core Level Ideal Scenario – All I/Os functionally registered .............................. 2

Hierarchical DFT – Core Level Ideal Scenario – All I/Os functionally registered .............................. 2

Hierarchical DFT – Core Level Non - Ideal Scenario – Unregistered I/Os ......................................... 2

Hierarchical DFT – Core Level Non - Ideal Scenario – Unregistered I/Os ......................................... 2

More Resources .................................................................................................................................... 2