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Muthukaruppasamy et al., International Journal of Advanced Engineering Technology E-ISSN 0976-3945

Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/434-444

Research Paper

THD AND PFC CONTROL SCHEMES FOR AC TO DC SWITCHING CONVERTER

1S. Muthukaruppasamy, 2A. Abudhahir Address for Correspondence

1SCAD College of Engineering and Technology, Cheranmahadevi, Tirunelveli District, Tamilnadu-627414, India.

2Vel Tech Multi Tech, Dr. Rangarajan Dr. Sakunthala Engineering College Chennai-600062, Tamilnadu, India.

ABSTRACT— The traditional behavior of an uncontrolled rectifier is the conversion of AC line input voltage to DC output voltage. This conversion feeds current pulsation, which is absorbed from the AC line. The current pulsation comprises of a large amount of harmonics that will induce harmonic contamination and low power factor in the power system. To overcome these troubles, an active approach that combines bridge rectifier and switching power converter, is employed. The voltage regulation of AC to DC switching power converter usually exhibits poor voltage regulation. Closed loop active current mode control schemes such as peak, hysteretic, line feed forward average current mode and soft switching technique are used to amend the dynamic regulation of total harmonic distortion of line current, power factor correction, and output voltage on switching converter. It also provides better control accuracy, enhanced system stability, increased reliability, and response speed. The simulation results revealed that line feed forward average current mode control scheme outperforms other current mode control schemes in terms of total harmonic distortion and power factor correction control. INDEX TERMS— AC to DC switching power converter, Current Mode Control (CMC), Continuous Conduction Mode (CCM), Power Factor Correction (PFC), Total Harmonic Distortion (THD), Voltage Mode Control (VMC.

I. INTRODUCTION For any electrical equipment, drawing power from the utility, THD of input line current and power factor are an indication to assess the power quality. The 1Ø AC to DC converter consists of an uncontrolled rectifier feeding the bulky filter capacitor. The circuit draws lanky input current pulse around line voltage peaks. The input current has high peak and contains a large number of harmonic components that would be injected into the utility [1],[2]. Such severely distorted AC utility voltage can damage sensitive electrical equipment. Passive approach is used for the reduction of THD and improving the PFC [3]. However, it is limited to only low power application up to 300W and drawbacks are the size and weight of filter choke and inductor. The most common approach to prevent the electrical hazards is to use an active pulse width modulated AC to DC switching converter [1],[2]. The chosen AC to DC switching converter is boost converter which provides high output voltage than input voltage [2]-[6]. To attain the good stability during transient stage, closed loop control has two loops such as VMC and CMC [2],[7]. The VMC is used for load voltage regulation of boost converter and it is done by the PI controller in the absence of CMC [8],[9]. To avert the harmonic oscillation of input line current and improve the THD reduction level, CMC is opted which are given below [10]:

Peak CMC Hysteretic CMC Line feed forward average CMC

In addition to the above mentioned control methods, the soft switching boost converter is used for cutting down switching loss and the size of passive elements[11][12]. A comprehensive review of these methods is examined and verified by MATLAB simulation. II. DEFINITION OF THD AND POWERFACTOR Harmonic distortion represents the measurement of the non-linearity of input impedance of the power electronic converter. Any changes in impedance will make distortion of input current and this distortion is

the root cause of poor power factor. If the non-linearity is small, the harmonic distortion will be low. Nonlinear load results typical distorted line current from the line. For sinusoidal voltage and non-sinusoidal current, the power factor can be expressed as [13]

))((

)(PF

CurrentRMSVoltageRMS

powerAverage

COSØIV

IV

rmsrms

rmsrms 1PF

PF = Kd CosØ = Kd Kθ

PF = (Distortion factor) x (Displacement factor)

)1(

2

2I

IK

1

1d

2

2

1

rms

rms

n

nII

I

O

‘Kd’ is the ratio of the rms fundamental component of the current to the total rms value of current. ‘Kθ’ is the cosine angle between the fundamental components of the voltage and current waveforms. Total harmonic distortion is defined as the ratio of rms value of the waveform not including the fundamental to the rms fundamental magnitude.[13]

)2(THD1

2

2

rms

n

rmsn

I

I

The Total harmonic distortion and distortion factor are closely related to comparison of equation (1) and (2), with I0=0, leads to, Distortion factor (Kd)

= )3(

)(1

12

THD

Equation (3) is plotted in Fig. 1. if the waveform contains third harmonic whose magnitude is 10% of fundamental, the distortion factor is 99.5%. Increment of third harmonic to 20% decreases the



distortion factor to 98%. As illustrated in Fig.2, 3 % of total harmonic distortion has a power factor of 0.999. A current with 30% of total harmonic distortion still has a power factor of 0.95. The aim of THD and PFC control is to minimize the input current distortion and make the current in phase with the voltage.

Fig.1.THD vs. Distortion factor

Fig. 2. THD vs. Power factor

III. THD-PFC CONTROL SCHEMES

Fig. 3. THD-PFC control schemes

The THD-PFC control schemes to reduce the harmonic contents of the line current are shown in Fig.3. A. Passive approach of THD-PFC control schemes In the passive PFC, only passive elements are used with the diode bridge rectifier to improve the shape of line current. It is possible to design a filter that passes current at line frequency. This filter reduces harmonic content using inductor and capacitor. At this point, power factor can be brought nearer to unity[14],[15]. Various combinations of these passive components in different circuit location give rise to many possible schemes. i) Rectifier with an ac side inductance ii) Rectifier with a dc side inductance iii) Rectifier with a series resonance band pass filter iv) Rectifier with a parallel resonant band stop filter v) Rectifier with harmonic trap filter Limitations: The filters used in the passive approach require large value high current inductors. They are bulky and expensive because the line frequency reactive

components are used. [14],[15].They also have poor dynamic response, lack of voltage regulation and limit their use to applications of below 300W. Even though line current harmonics are reduced, fundamental component may lead to excessive phase shift that causes power factor decrement, ie power factor less than 0.85 can be achieved. They are sensitive to circuit parameters and optimization of design is difficult. B. Active approach of THD – PFC control schemes The active control has many advantages such as high power factor (0.99) and low THD (3 to 10%), size, weight and cost benefits for higher power level. The active control technique is classified into: 1) PWM control technique 2) Soft switching control technique 1) PWM control technique: This control technique provides pulse width modulation to power switching device in power converter. It has the features such as lowest voltage and current stress, ease of analysis and smooth control, high switching frequency for minimization of converter size. PWM control technique is classified into: a) Conventional active topology with poor load dynamics This is further classified into: i) Boost converter ii) Voltage mode control of boost converter b) High power factor active topology with fast load dynamics This is further subdivided into: i) Peak current mode control ii) Hysteretic current mode control iii) Line feed forward average current mode control a) Conventional active topology with poor load dynamics i) Boost converter

The existing conventional active topology for THD and PFC control are buck, boost, buck-boost, cuk converter. Among these, boost topology is most suitable.[2]-[6],[16]. This is because the boost inductor is in series with input terminal, the inductor will achieve smaller current ripple and it reduces total harmonic distortion and avoids the transient impulse from power net. The main role of boost converter is to keep the output voltage as close as possible to the desired constant reference. But the continuous switching commutation gives nonlinearity to the converter. This nonlinearity of the converter will not be able to cope for the steady state errors due to the changes in input voltage and load variation [17],[18]. ii) Voltage mode control of boost converter

Fig. 4. Voltage mode control of boost converter



To achieve the proper objective of boost converter, a PI controller is added for maintaining the output voltage at the required level. It reduces the steady state errors and rise time [19],[22]. The voltage mode control is shown in Fig. 4. In voltage mode control, the output voltage of boost converter is compared with reference signal to generate a control signal which triggers the pulse width modulator through classical control feedback compensation. Under VMC, twice the line frequency ripple on the output voltage transmits through the voltage loop path to distort the input current waveform. This leads to poor performance [17], [18]. b) High power factor active topology with fast load dynamics The objective of the high power factor topology is to govern the power flow. It guarantees rigid output voltage regulation as well as unity input power factor and reduction of THD of input current. The control requirements of high power factor topology are to:[7],[9],[17],[20] i) maintain a pure DC output voltage at a constant value [21][22]. ii)maintain an input current wave shape as pure sinusoidal at unity power factor, iii)provide a lower conducted noise, lower conduction losses, iv)provide robust performance in presence of uncertainties in component values and operating conditions [23]. The boost converter tries to keep a constant DC voltage [24],[25]. At the same time, boost converter draws a current that should be always in phase with the line voltage at the same frequency. So the feedback control loop is effectively needed to control the boost converter during transient and steady state behavior of the circuit [20],[21]. The feedback control loop consists of both the voltage control loop and the current control loop [26]. The conventional CMC scheme of high power factor active PFC topology is shown in Fig. 5.

Fig. 5. Conventional CMC

Generally the conventional CMC is classified into: i) Peak CMC ii) Hysteretic CMC iii) Line feed forward average CMC i) Peak CMC Fig. 6 shows the peak current mode feedback system. The peak value of the inductor current is commanded to shape the input line current [26]. The compensation circuit for achieving overall boost converter loop stability, consists of error amplifier, external ramp circuit and clock signal. The conventional peak current mode control without slope compensation struggles due to instability when the duty ratio surpasses 0.5 [27].

Fig. 6. Peak CMC

This requires the addition of stabilizing external ramp. The external ramp for slope compensation is added to the sensed current for ensuring stability when the duty ratio exceeds 0.5 [28]. The output of voltage error amplifier Verror is multiplied by the rectifier input voltage signal to generate reference current iref [28]-[30]. When the switch is turned on at constant frequency by a clock signal, the inductor current goes up, and as it attains iref, the switch is turned off, thereby causing the inductor current to ramp down until the next clock comes [28],[29]. It is shown in Fig. 7.

Fig. 7. Waveform of reference current and inductor

current Limitations: i) Presence of sub harmonic oscillations at duty ratio is greater than 0.5. So the slope compensation is needed [30]. ii) Commutation noise immunity is poor. Merits: i) The operation mode is CCM at constant switching frequency. ii) Current error amplifier is not needed. iii) The instantaneous cycle-by-cycle current limit directs to increased response speed. ii) Hysteretic CMC:

Fig. 8. Hysteretic CMC

Fig. 8 shows the hysteretic current mode feedback system. The inductor current is maintained within the total hysteresis band to shape the input line current [31]. The compensation cycle for shaping the input line current consists of error amplifier, hysteresis band circuit and clock signal [32]. The hysteresis band circuit consists of two comparators and IP ref and IV ref [33]. The inductor current (IL) ramps



alternatively between an upper limit IP ref and a lower limit IV ref as shown in Fig. 9. As the inductor current increases, the output of current sense amplifier reaches the threshold of the comparator IP ref, whose output goes high which resets the flip flop and turns off switch. As the inductor current ramps down, the output of current sense amplifier decreases to the threshold of comparator IV ref. The output of this comparator goes high and the flip flop sets, and switch (Q) turns back on.

Fig. 9. Waveform of reference current and inductor

current Limitations: i) This current mode control needs two current commands. ii) It is done by the variable switching frequency. Merits i) Slope compensation is not needed. ii) Low distorted input current is achieved, and iii) Better switching noise immunity is attained than the peak CMC. iii) Line feed forward average CMC: Fig. 10 shows the line feed forward average current mode feedback system. The average value of inductor current is commanded to shape the input line current [34]-[37]. The output of the voltage error amplifier is limited to a safe value and forms the amplitude of reference current [38]-[40].

Fig. 10. Line feed forward average CMC

Fig. 11. Line feed forward system

Fig. 12.Waveform of reference current and inductor

current

Importance of line feed forward system is explained as follows: The line feed forward system is as shown in Fig. 11 The reference amplitude (Verror) is multiplied to a template of input voltage (Vdc) to synchronize the reference with input voltage as required for unity power factor operation. Moreover, the input voltage feed forward consists of squarer and divider. The output of the voltage error amplifier is multiplied by a rectified input voltage signal. Then it is divided by the square of the RMS input voltage signal to improve the dynamic response of the converter [40]-[47]. The inductor current is coerced to follow its reference current using a current controller which produces gating signal for the active devices. It is shown in Fig. 12. Merits: i) Operation mode is CCM at a constant switching frequency[43]. ii) Compensation ramp is not needed. iii) Control is less sensitive to commutation noise [44]. iv) Dynamic response to load change is good. v) Control loop with the facility of squarer and divider makes good tracking performance of an average current[45]-[46]. 2) Soft switching control technique:

Fig. 13. Soft switching boost converter

The soft switching THD and PFC control technique unites PWM mode and resonant mode technique with an additional resonant network comprising of a resonant inductor, a resonant capacitor and an auxiliary switch. The AC to DC converter functions in the PWM mode during most portion of switching cycle but works in resonant mode during the switch turn on and turn off intervals[48]. Eventually, the THD-PFC control circuit performs at constant switching frequency and power switch excites to turn on and off at zero voltage or zero current conditions [49]-[50].The soft switching topology and waveform are shown in Fig. 13. Mode 1 and Mode 2: The switch is in off state and the rectified DC output is transformed to the load through L and Dout. Thus the main inductor current reduces linearly. This is shown in Fig. 14 of operation of mode1. If the switch is in on state during zero current switching, the mode 2 begins. The current through resonant inductor Lr rises and it causes the same current to the main inductor L. The current through diode Dout turns to the zero level. This is shown in Fig. 15 of operation of mode2.



Fig. 14. Operation of mode 1


Mode 3 and Mode4: Here the section of resonant mode begins and the auxiliary resonant inductor Lr and auxiliary capacitor Cr1 start to resonate. The voltage of Cr1 is reduced to zero at the output voltage. The current of main inductor L starts to flow through Lr and the switch. At this time, voltage at Cout discharges. This is shown in Fig. 16 of operation of mode3.



In mode4, If the auxiliary resonant capacitor Cr1 is reduced to zero, two auxiliary diodes D1 and D2 start to turn on. In this mode, auxiliary resonant inductor current is separated into two, one is the current of main inductor and the other is the current flow through auxiliary diodes D1 and D2. At this juncture, the main inductor current(iL) rises linearly. This is shown in Fig. 17. Mode 5, Mode6, and Mode7: When the switch is turned off with the zero voltage condition, at the current loop of L-Cr1-Vin, the voltage of Cr1 rises linearly from zero to Vout. In the second current loop of Lr-Cr2-D1, energy stored in Lr moves to Cr2, then Lr becomes zero and the voltage of Cr2 gets maximum value. This is shown in Fig. 18 of operation of mode 5. In this mode 6, the current loop occurs in the direction D2-Cr2-Lr-Dout-Cout and displaces the energy of Cr2 to Lr. If the voltage of Cr2 turns zero, the current of Lr flows in opposite way and the

antiparallel diode turns over to next mode. This is shown in Fig. 19.

. Fig. 18. Operation of mode 5



In mode 7, the main inductor current L transfers the energy to the output through Dout and reduces linearly. The current of Lr transfer the energy to the load through Dout. If Lr turns to zero, this mode ceases. This is shown in Fig. 20. Limitations: i) Reactive elements are large. ii) Count of reactive elements is more. iii) Regulation of the output voltage is slow under wide range of input voltage and load power variation. Merits: i) Switching losses are reduced greatly [51]. ii) Higher efficiency of the system is achieved [52]. IV. RESULTS AND DISCUSSION THD – PFC control schemes are verified by the MATLAB simulation for the following cases: A. Active approach of conventional AC to DC converter with poor load dynamics. B. Active approach of high power factor AC to DC converter with fast load dynamics. C. Active approach of soft switching AC to DC converter D. Performance overview for active approach of THD-PFC control schemes. Following table 1 explains about the performance comparison measures of THD-PFC control schemes A. Active approach of conventional AC to DC converter with poor load dynamics Table 2 shows the parameters of AC to DC boost converter. In this simulation 1) Conventional boost converter 2) VMC boost converter are discussed. For both these methods, input voltage, input current, THD of input current, and output voltage are shown in Fig. 21 a, b, c and Fig. 22 a, b, c.



TABLE 1- PERFORMANCE COMPARISON MEASURES OF THD-PFC CONTROL SCHEMES

TABLE 2 PARAMETERS OF AC TO DC BOOST CONVERTER

Fig. 21.a. Input voltage, current waveform of AC to

DC boost converter

Fig. 21.b.Line current THD of AC to DC boost

converter

Fig. 21.c. Output voltage of boost converter



Fig. 22.a. Input voltage and current of VMC boost

converter

Fig. 22.b. Line current THD of VMC boost converter

Fig. 22.c. Output voltage of VMC boost converter

The simulation results of source side performance factors such as THD, displacement factor (Kθ), distortion factor (Kd), power factor and load side performance factors such as delay time (td), rise time (tr), peak time (tp), settling time (ts), peak over shoot (Mp) are placed in Table 3.

TABLE 3. PERFORMANCE OF BOOST CONVERTER AND VMC BOOST CONVERTER

B. Active approach of high power factor AC to DC converter with fast load dynamics 1) Peak CMC The peak CMC senses and controls the peak inductor current. Though it attains input line current wave shaping, it gives few problems such as the poor noise immunity, the need for slope compensation and the peak to average current error. This circuit is simulated and the simulation results of input voltage and input current, THD, output voltage are shown in Fig. 23. a ,b and c. The performance factors of source and load sides are shown in Table 4.

Fig. 23.a. Input voltage and current of peak CMC

Fig. 23.b. Line current THD of peak CMC

Fig. 23.c. Output voltage of peak CMC

TABLE 4 PERFORMANCE OF PEAK CMC

2) Hysteretic CMC

Fig. 24.a. Input voltage and current of hysteretic

CMC



The Hysteretic CMC controls the inductor current within the hysteretic band by two reference signals of IP ref and IV ref.. But this makes the variable frequency operation. This circuit is simulated and the results are taken which are shown in Fig. 24. a ,b and c. The performance factors of source and load sides are tabulated in Table 5.

Fig. 24.b. Line current THD of hysteretic CMC

Fig. 24.c. Output voltage of hysteretic CMC

TABLE 5. PERFORMANCE OF HYSTERETIC CMC

3) Line feed forward average CMC The Line feed forward average CMC controls the average value of inductor current. It has the merits of the improved noise immunity, the less THD and the ease to shape sinusoidal waveform.

Fig. 25.a. Input voltage and current of line feed forward

average CMC This circuit is simulated and the results of input voltage and current, THD of input current and output voltage are shown in Fig.25. a, b and c. Performance factors from simulation are listed in Table 6.

Fig. 25.b. Line current THD of line feed forward

average CMC

Fig. 25.c. Output voltage of line feed forward average

CMC TABLE 6 PERFORMANCE OF LINE FEED

FORWARD AVERAGE CMC

C.Active approach of soft switching AC to DC converter The main aim of the soft switching is to maintain a very low power loss by means of resonant operation when the switch is turned on. The parameters of soft switching converter are shown in Table 7. Fig. 26 a, b and c represents the input voltage and input current, the THD of input current, and the output voltage. The simulation results are tabulated in Table 8.

TABLE 7. PARAMETERS OF SOFT SWITCHING CONVERTER

Fig. 26.a. Input voltage and current of soft switching

converter



Fig. 26.b. Line current THD of soft switching

converter

Fig. 26.c. Output voltage of soft switching converter

TABLE 8. PERFORMANCE OF SOFT SWITCHING CONVERTER

D. Performance overview for active approach of THD – PFC control schemes

Fig. 27. Output voltage of THD –PFC control schemes

TABLE 9. PERFORMANCE OVERVIEW FOR

ACTIVE APPROACH OF THD –PFC CONTROL SCHEMES IN SOURCE SIDE

In passive schemes, the output voltage is not regulated and require over dimensioning of parts. Active schemes overcome many of the drawbacks of passive schemes and are the popular choice for THD and PFC control because of their switching speed,

ease of driving and ruggedness. TABLE 10. PERFORMANCE OVERVIEW FOR

ACTIVE APPROACH OF THD –PFC CONTROL SCHEMES IN LOAD SIDE

The high power factor active schemes such as the peak, the hysteretic and the Line feed forward average CMC and the soft switching technique were discussed. The performance results are overviewed in the Table 9, Table 10 and Fig. 27.The peak CMC can reach the power factor of 0.916 and the THD of 11.77% and the hysteretic CMC can attain the power factor of 0.969 and the THD of 10.80%. The line feed forward average CMC gives the power factor of 0.989 and the THD of 5.98% .The soft switching control has the power factor of 0.868 and the THD of 10.81%. Other performance factors like delay time (td), rise time (tr), settling time(ts), peak overshoot (Mp) are reduced well and are tabulated. IV. CONCLUSION All the passive and active THD-PFC control schemes were reviewed and simulated through MATLAB. The passive THD and PFC control schemes are applicable only for less than 300W application. It has poor dynamic response due to the time lag associated with the passive elements. To achieve the reduction of THD and power factor, rapid settling time and reduction of peak overshoot, the active THD-PFC control schemes were simulated. The active THD-PFC control schemes are classified into PWM control and soft switching control techniques. The PWM control includes conventional topology with poor load dynamics and high power factor topology with fast load dynamics. In conventional topology with poor load dynamics, VMC boost converter attains the THD of 45.17% and the power factor is 0.850. In order to attain the power factor improvement, reduction of THD in source side and reduction of settling time, reduced peak overshoot in load side over conventional topology with poor load dynamics, high power factor active topology with fast load dynamics is preferred. The simulation of high power factor active schemes such as the peak, the hysteretic, the average CMC and the soft switching control technique were carried out. When compared to other schemes, the average CMC scheme is found to have good performance in load side as well as source side. The line feed forward average CMC has the power factor of 0.989 and reaches 5.98% of THD. It also has the settling time in 0.06s and reduces 2.5% of peak over shoot. The study indicates that the line feed forward average CMC of boost converter under high



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