the esa music project design of dsp hw and analog tx/rx ends

The ESA The ESA MUSICMUSIC ProjectProject

Design of DSP HW Design of DSP HW andand Analog TX/RX ends Analog TX/RX ends

Advanced Mobile Satellite Systems & Technologies presentation days

ESA/ESTEC – 14-15 November 2000

AMSST Presentation Days – 14-15 November 2000

Presentation Outline

• The PROTEO Signal Processing BoardThe PROTEO Signal Processing Board

• The MUSIC TX/RX Analog Signal The MUSIC TX/RX Analog Signal Conditioning UnitsConditioning Units


FLEX10K100ACPLD

ST18952RAM FLASH

RAM

MAX7032

JTAGRESET

VCXO

DIG.INP. CON 24SIMM xRAM

78S05

78S05

LM317T

LM317T

+12 V +5 V

CON 40 CON 40

ICD2053BProg.CLK

AD5323DAC

CY7B991ROBOCLK

CON40

CON40

CON40

CON 40

CON40

CON40

OPA2681

OPA2681

ADS807ADC

TL7702 POR

LED

ADS807ADC

74LCX245BUFFERS

74LCX245BUFFERS

74LCX245BUFFERS

ICD2053BProg.CLK

FLEX10K100ACPLD

TO LOGICANALYZER

TO LOGICANALYZER

EXT. BOARD PROG.

CON 8

BIT BLASTER

CON 10

AGC1 VC

AGC2 VC

IF / I IN

Q IN

AD5323DAC

AFC VC

EXT. CLK

QS3238BUS SW

LEDLED LED LEDLED LED

EXT. CLK

AMP. & ADC

BUFFERING

MASTER CLK GEN.

LOGIC100K Gates CPLD

ANALOGAGC

POWER SUPPLY & P-ON RESET


DSP + Glue Logic

MEMORY Extension (SRAM or DRAM)

The PROTEO Signal Processing Board


The PROTEO Signal Processing Board

FLEX10K100ACPLD

ST18952RAM FLASH

RAM

MAX7032

JTAGRESET

VCXO


78S05

78S05

LM317T

LM317T

+12 V +5 V

CON 40 CON 40

ICD2053BProg.CLK

AD5323DAC

CY7B991ROBOCLK

CON40

CON40

CON40

CON 40

CON40

CON40

OPA2681

OPA2681

ADS807ADC

TL7702 POR

LED

ADS807ADC

74LCX245BUFFERS

74LCX245BUFFERS

74LCX245BUFFERS

ICD2053BProg.CLK

FLEX10K100ACPLD

TO LOGICANALYZER

TO LOGICANALYZER

EXT. BOARD PROG.

CON 8

BIT BLASTER

CON 10

AGC1 VC

AGC2 VC

IF / I IN

Q IN

AD5323DAC

AFC VC

EXT. CLK

QS3238BUS SW


EXT. CLK

AMP. & ADC

BUFFERING

MASTER CLK GEN.


ANALOGAGC

POWER SUPPLY & P-ON RESET


DSP + Glue Logic

MEMORY Extension (SRAM or DRAM)


PROTEO Functional Block Diagram

CPLDFlex10K100A

16bit DSPST18952

JTAG IEEE 1149.1

OState Anal./ other

12bitADC

Clock Gen.&Skew Mng.

Vcxo

ext.CLK1

DualDAC

AGC1AGC2

O

SRAM D Mem.64Kx16

FLASH P Mem.4Mx16

SRAM Mem.256Kx16

IF /I in I

Q in I

Buffer

Buffer12bitADC

Buffer

I

Amp.

Amp.

CPLDFlex10K100A

Prog.Clock

Prog.Clock

Xtal27MHz

ByteBlaster

DualDAC

Voltage Reg.

VCC5V

VDD5V

CPLD3V3

DSP3V3

IF Dig. In

MAX7032

BusSwitch

YBusAFCoption

ext.CLK2

2Vpp

2Vpp

12

12

12

12

12

Fs

ADS807

ADS807

OPA2681

OPA2681

A

B A

B

Vz

AD5323 AD5323

44

Glob.CLK1

Glob.CLK1

Glob.CLK2

Glob.CLK2

36

FRef

Fo1 Fo2 Fo3Fo4

Fo5

Set Pull Up/Down Resistors

CY7B991

Fout=Fo3*(M/N)

Fout=Fo4*(M/N)

P-onReset

RESET

IBus

XBus

Interrupts& Flash Mng.

74LCX245

74LCX245

74LCX245CY7C1041V33

STM29W800

38 72

5

CPLDConfig.DATA

Ext. Board Prog.

5

33

8

8

816

16

16

ICD2053BICD2053B

I/Oto/fromExt. Board

32

CY7C1021V

from PC/WS

Enable

+

Data/Cntrl

QS3R384

Ext. Memory Module(optional)

TL7702


PROTEO Board Main Features Summary• 12 bit pipelined ADC Converter (BB ADS807) up to 53MHz sampling.• 100 Kgates CPLD (Altera Flex EPF10K100A):

- clock >100MHz;- usable gates: 90%;- embedded array blocks: 12 (ex. RAM, ROM, FIFO functions);- in-circuit re-configurability via Byte-Blaster or JTAG port.

• 66 MIPS 16bit DSP (ST18952).• On board Memories:

- x CPLD: SRAM 256Kx16 & SIMM-like Module for SRAM 1MB or SDRAM 4MB;- x DSP : SRAM 64Kx16, FLASH 4Mx16.

• Master Clock distribution by Prog. Skew Clock Buffer (Cypress CY7B991):- selectable skew to 18ns (+-12 time units of 1.5ns).

• Prog. Clock Generator (Cypress ICD2053B) for CPLD only:- clock out : 391KHz-90MHz;- prog. "on the fly" by 2 wire serial interface.

• 2x 12 bit dual DAC converters (Analog Device AD5323) :- high-speed serial interface control logic (up to 30 MHz).


PROTEO Clocks Distribution

FLEX10K100ACPLD

ST18952DSPRAM FLASH

RAM

MAX7032

JTAGRESET

VCXO


78S05

78S05

LM317T

LM317T

+12 V +5 V

CON 40 CON 40

ICD2053BProg.CLK

AD5323DAC

CY7B991ROBOCLK

CON40

CON40

CON40

CON 40

CON40

CON40

OPA2681

OPA2681

ADS807ADC

TL7702 POR

LED

ADS807ADC

74LCX245BUFFERS

74LCX245BUFFERS

74LCX245BUFFERS

ICD2053BProg.CLK

FLEX10K100ACPLD

TO LOGICANALYZER

TO LOGICANALYZER

EXT. BOARD PROG.

CON 8

BIT BLASTER

CON 10

AGC1 VC

AGC2 VC

IF / I IN

Q IN

AD5323DAC

AFC VC

EXT. CLK1

QS3238BUS SW


EXT. CLK2

Fo = 16.384 MHz

Fo * M/N Fo * M/N

Fxtal 27MHz

Fo

-6 tu, +6 tu, :2, :4 (1,2)

-6 tu, +6 tu, :2, Neg (3)

-4 tu, +4 tu (4)

-4 tu, +4 tu (5)

tu = 1.4 ns

Note :

(1) (2)

(3) (4)

(5)


MUSIC Breadboard System Overview

MAIN "PROGRAMMABLE" BOARD

EXTENSION BOARD

EC-BAIDCPLD CPLD

DSP

TX TEST SIGNAL GENERATION &RX ANALOG F-E


MUSIC TX - System requirements

• IF Carrier Frequency: 70MHz

• Max Carrier Frequency Uncertainty: +/-100 Hz

• TX Output Power Level: -10 to -30 dBm

• Spurious and Harmonics: <40 dBc

• In-Band Ripple: <0.1 dB


The MUSIC TX/RX: Analog IF Front End

AWG NOISEGENERATOR

IF 70MHz1V p-pDiff.out

L.O.Ext.in

fIFD

Signal+MAI

Signal+MAI+Noise

ArbitraryWaveformGenerator

Downloadvia IEEE488

Controlvia IEEE488

to MUSIC ReceiverDigital Section

T

AGC

PLL

B-PFilter 1

VGA

L.O.

Mixer

BALUN

B-PFilter 2

Low-passFilter

fIF

fIF

fLO

Vagc

TX SECTION

RX SECTION

TestPoint

TP

TPIF

IF N

TP

TP

TP


Up-conversion TX board Block Diagram

Controlvia IEEE488

AWG NOISEGENERATOR

L.O.Ext.in

Signal+MAI+Noise

fIFD

Signal

+MAIArbitraryWaveformGenerator

Downloadvia IEEE488

T

TCXO

B-P

Filter 1

Mixer

Low-pass

Filter

fIF

fLO

TX SECTION

TestPoint

LO 65.536 MHzLC Butterworth Low-pass Filter

Order: 53-dB Bandwidth: 7.5 MHz

Active Mixer: Analog Device AD831

LO Drive required (min): -10 dBmP1dB: +10 dBmIP3: +24 dBm

SAW Filter: SAWTEK 854657

1-dB Bandwidth: 3.25 MHzInsertion Loss: 7.7 dBIn-band ripple: 0.8-1 dBGroup delay in spec

TCXO: Fordahl DFA 36-MS

Nom Frequency: 65.536 MHz Output Load: Sine 0 dBm (50 Ohm)Frequency stability: +/- 1 ppm


P1dB Measurements

•P1dB (input): +10 dBm

Compression Gain

-60

-50

-40

-30

-20

-10

0

10

-50 -40 -30 -20 -10 0 10 20

Input Power [dBm]

Ou

tpu

t P

ow

er

[dB

m]


Harmonics and in-band ripple

•Max Outband spurious level: -44 dBc

-13

-12.5

-12

-11.5

-11

-10.5

-10

-9.5

-9

-8.5

-8

68.7 68.9 69.1 69.3 69.5 69.7 69.9 70.1 70.3 70.5 70.7 70.9 71.1 71.3

•In-band ripple (Pin=0dBm): 1 dB

•Isolation LO to Output: -65 dB


MUSIC RX AGC board Block Diagram


Signal+MAI+Noise


fIF

IF N

BALUN

B-PFilter 2

RX SECTION

TP

VGA 1VGA 2 TP

Vref

-

+

Amp2Amp1

BUFFER LOG AMP RSSILow-Pass filter

error signal

VGA: Philips SA5219

Bandwidth: 700 MHz7 dB Noise Figure Min0-1V gain control pin

SAW Filter: SAWTEK 854657

1-dB Bandwidth: 3.25 MHzInsertion Loss: 7.7 dBIn-band ripple: 0.8-1 dBGroup delay in specRSSI: Analog Devices AD8307

Dynamic range: 92 dBSlope: 25 mV/dB

Op-Amp: TSH31

Op-Amp: TL082

1 pole RC filter


Control loop


Signal+MAI+Noise


fIF

IF N

BALUN

B-PFilter 2

RX SECTION

TP

VGA 1VGA 2 TP

Vref

-

+

Amp2Amp1

BUFFER LOG AMP RSSILow-Pass filter

Loop stability!!Loop error

Loop gain

Loop Bandwidth


Loop Bandwidth

•Loop Bandwidth must be limited in order to avoid input signal modulation.

•Loop bandwidth fixed: 200 Hz

•Loop gain: ~20 dB


HP-ADS Simulation Schematic


HP-ADS Simulation Input Signal

•Input Signal Average Power Dynamics: 20 dB

•Average Fading rate: 20dB/3ms


HP-ADS Simulation Results

•20 dB Input Power Dynamics

•1 dB Output Power Dynamics


Conclusions

• Implementation of TX and RX boardsImplementation of TX and RX boards

• Testing and measurements has confirmed Testing and measurements has confirmed simulations resultssimulations results

the esa music project design of dsp hw and analog tx/rx ends

Documents

x cpld

mb x dsp

analog txrx

master clock distribution

sram 64kx16

dsp st18952

sram 256kx16 simm

wire serial interface