the vlsi industry - an overview of market, job functions and product development cycle

THE VLSI INDUSTRY

AN OVERVIEW OF

MARKET

JOB FUNCTIONS

AND PRODUCT DEVELOPMENT CYCLE

© 2015 Logosent Semiconductors India Pvt. Ltd.

Tony Thomas

Logosent Semiconductors India Pvt. Ltd.www.logosent.com

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Agenda

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Tony Thomas E ( [email protected] ) 8

A Snapshot of the Revenues and the Major Players

Typical Application Spaces and Target End-Equipment

VLSI engineering – An Overview of the Scope and Job Functions

Requirements Definition to Packaged Silicon : A quick tour

The Revenues

• Estimated total revenue of approximately $340B in 2014

52.3

34.7

19.3

16.3

16

11.5

10.7

8.4

7.4

7.2

7.1

149.4

2014 Revenue Split up* ($Billions)

Intel

Samsung

Qualcomm

Micron Technology

SK Hynix

Texas Instruments

Toshiba

Broadcom

STMicroelectronics

Renesas Electronics

MediaTek

Others

Source: Gartner, IHS iSuppli Semiconductor rankings

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*Approximate revenue numbers, may not be accurate

Typical Target End Equipment

Industrial and Home Automation


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• Support for multiple industrial communication protocols

• Display and graphics for HMI.

• Good application processor.

Typical Target End Equipment (Contd.)


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Automotive control, auto-vision and infotainment

• Multimedia capabilities for Infotainment and dashboard panels.

• Extremely high safety and reliability standards required to ensure that the systems do not fail resulting in human injuries.

- Require SOCs to meet “Zero DPPM”” standards, that in turn maps to very high Silicon test-coverage.- Many automotive safety standards also mandate BIST (Built In Self Tests).- Redundancy and data error detection/correction mechanisms.

• Support for automotive-oriented communication protocols like the CAN Bus.



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Portable Hand-held devices

• Very tight power-consumption budgets and support for multiple power-modes that are needed to minimize the battery charge consumption.

• High-performance video, audio and graphics capabilities, coupled with high-resolution touch-screen display support.

• Support for functionalities like GPS, WiFi, USB, Bluetooth, NFC, bar-code scanners etc.



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Point of Sale (POS) Terminals

• Extremely high security requirements to protect the personal information- Multi-layer data encryption, decryption and authentication support in hardware- Support for tamper detection and prevention mechanisms

• Good graphics and touch-screen display functionality for user interface.

The realm of VLSI engineering

IP blocks

IP Development

SOC /FPGA

CPU

DSP

PLLsHWA

I/O

I/O

I/O

I/O

I/O

OCM

Bus Interconnect

DMA

System

SOC / FPGA Development

SOFTWARE

Software Development

EDA Centric


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Analog

Process Technology

Driven

VLSI Engineering Job Functions

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Design Implementation

• Micro-architecture definition and detailed design development.

• RTL code implementation using languages like SystemVerilog or VHDL.

• Design entry using schematic capture or other UI tools in some cases.

• Quality Checks and basic sanity checks on the implemented RTL.

`timescale 1ns / 100ps

module pwm_top (input pwm_clk,input presetn,input pclk,input [15:0] paddr,input psel,input penable,input pwrite,input [31:0] pwdata,input [3:0] pstrb,output pready,output [31:0] prdata,output pwm_out);

Responsibilities


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Design Verification and Validation

• Test bench and test-case development based on the Architecture Specifications.

• Detailed verification of the RTL implementation to achieve a bug-free design.

• Test coverage analysis and enhancements to ensure robustness of the design.

Responsibilities


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Design For Test and Manufacturability (DFTM) and Product Engineering

• Architect and implement the logic required for conducting the manufacturing tests and the power/performance characterization processes towards silicon qualification.

• Generate silicon test patterns and ensure the required level of circuit coverage

• Conduct the silicon qualification tests and characterization on manufactured silicon using various Automatic Test Equipment (ATE) like VLCT, Fusion, Burn-In set-up etc.

Responsibilities

VLSI Engineering Job Functions (Contd.)

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Gate Netlist Generation and Logic Equivalence Checks (LEC)

• Logic Synthesis of the RTL code using tools like Synopsys Design Compiler or Cadence RTL Compiler to generate the equivalent gate-netlist.

• Insertion of DFTM specific logic like scan chains, scan-combiners etc. in the netlist.

• Improve QOR (Quality of Results) to meet the power, area and performance targets.

• Conduct Logic Equivalence Checks (LEC) to formally prove the functional equivalence of the gate-netlist against the source RTL code.

Responsibilities


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Physical Design/Implementation and Static Timing Analysis (STA)

• Develop the Floorplan for optimum physical placement of blocks and logic-gates to achieve the lowest die-area, best device pin-out and robust power/signal routing.

• Place and route of the gates and macros to meet the PPA goals.

• Extraction of parasitic information and Static Timing Analysis (STA) for timing closure.

• Backend layout checks to ensure electrical integrity, reliability and manufacturability.

Responsibilities


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Package Design

• Select the right package(s) to house the silicon-die and meet the requirements in terms of package-size, pin-out, ball-pitch, thermal, performance, reliability, price etc.

• Implement optimum substrate routing (die pins to package pins) and conduct various electrical, thermal and reliability simulations to ensure robustness.

Responsibilities


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FPGA Implementation and Emulation

• Deployed for low-volume applications requiring dynamic configurability, special DSP applications and pre-silicon validation.

• Synthesis and Implementation of IP and SOCs in FPGA making the best utilization of the logic, memory and pre-defined macros in the FPGA fabric meeting timings.

• Hardware validation of the design by running the firmware/software on the FPGA implementation.

Responsibilities


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• Development of the software tools required for executing various stages of design implementation, verification, synthesis, LEC, test-pattern development, physical implementation, electrical analysis, STA, Noise analysis, backend verification etc.

• Must keep-up with the advancements in process technology and design complexities, continuously pushing the envelope on capacity, accuracy and run-times.

Electronic Design Automation (EDA) tool development

Responsibilities


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Software and Firmware Development

• Due to the extreme complexity of the modern day SOCs, the chip manufactures include a complete software support infrastructure along with every SOC sold making it easier for the SOC customers to build their applications.

• The software package include customized Operating System (like LINUX), drivers, BIOS, Boot-loader, Codecs and various debugger tools.

Responsibilities

System requirements

Texas Instruments DM368 based IP Camera reference design

Source: http://www.ti.com/diagrams/rd/schematic_dm368ipnc-mt5_20140402125602.jpg


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http://www.ti.com/diagrams/rd/schematic_dm368ipnc-mt5_20140402125602.jpg

SOC High Level Block Diagram

Source: http://archive.linuxgizmos.com/ldimages/stories/ti_integra_c6a816x_block.jpg


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ARM core for GUIs,network functions, system control and running various applications in OS.

High PerformanceDSP core for complex Math functions and signal/image processing.

1.5 GHz 1.5 GHz

SGX530

Hardware Accelerator for 3D Graphics

HD Display

High-Speed Interfaces

Serial Port i/f for keypad, speakers, Bluetooth, PMIC, GPS, TSC etc.

External memory and secondary storage interfaces

Bus Interconnect infrastructure

The Design Cycle simplified.

Functional and DFTM Specifications

Micro-architectureand detailed design development

Business justification,Requirements sign-off,Boundary Agreements

Kick-off

RTL CodeImplementation and

Quality checks

Synthesis and scan-insertionLogic Equivalence checks

Functional verification& Hardware Emulation

(if applicable)

Test Bench andTest-case/stimuli

development

DFTM pattern generation, Pattern Simulations,

Coverage analysis andEnhancements.

Floorplan, package design,CTS, Place and Route,

Back-end checksFinal QC and

Hand-off

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Parasitic extraction andStatic Timing Analysis

Chip Functional, Package and DFTM Specs

Detailed Micro-architectureand Bottom-up schedule definition

IP definition, verification

and QC checks

Chip-level Func/DFTMTest-plan generation,

Test-bench and Test-case development

Constraintsdevelopment,

Initial Floorplan

Business justification,Requirements sign-off,Boundary Agreements

Kick-off

Initial RTL integration Quality checks

Initial IP hand-off

Synthesis setupInitial netlist

100% RTL integrationTrial Quality checks

Trial Synthesis DFTM insertion,

Full netlist, Netlist QC, LEC

Intermediate IP hand-off

Trial Physical DesignDetailed Floorplan, PnR,

CTS, hold fix, IR drop, power-grid,

Timing-closure, backend flush

PackageCo-design

Final Physical DesignFinal Floorplan, PnR, CTS, hold fix, IR Drop,

power-grid, High-Vt swap,Timing-closure, slew fixes

Final Synthesis DFTM insertion,

Optimized netlist, Netlist QC, LEC

Timing ECOs,Backend checks

Gate simulationswith back-anno

TapeOut

DFTM verification, Analysis, Coverage

enhancements

Final RTLUpdates and

Quality checks

Frozen netlist

Frozen RTLScripts andconstraints

Func. mode constraints

PnR & STA constraintsFinal IP

hand-off Functional VerificationAnd Validation

A

A

Trial netlist

Scripts andconstraints

A

Trial RTL

An SOC design cycle – Next level details

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Physical implementation


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Source: http://wp.iosfans.com/wp-content/uploads/2012/09/A6-Layout.jpeg

Silicon manufacturing and packaging

Silicon ingot

Fabrication


Silicon wafers Silicon die

Package

Package

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Contact us

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Contact the presenter : [email protected]

Online instructor-led course for beginners by Logosent on Edureka : www.edureka.co/vlsi-digital-design

Why Learn VLSI Digital Design?

Hands-on knowledge of Digital Design is a must-have for multipleelectronics engineering job categories ranging from board leveldesign that involves PLD programming, through FPGA based systemdesign, to ASIC design/verification job functions.

The Logosent VLSI Digital Design Essentials course is optimized forhelping the new-entrants gain confidence and jump-start theircareer minimizing the ramp-up requirements upon entering thesejob categories.

The students can use the experience and concepts gained from thecourse not only for performing with higher confidence in jobinterviews, but also in getting an added competitive edge towardsbecoming a high-performing VLSI professional.

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About Logosent : www.logosent.com

mailto:[email protected]

http://www.edureka.co/vlsi-digital-design



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25Tony Thomas E ( [email protected] )17 September, 2015


Questions ?

Thank You&Good Luck!

17 September, 2015




DUTDesign Under

Test

Pin-Mux and

Control Registers

ARM 926EJ

BFM2

BFM3

BFM1

Assertions/monitors, Score-board, coverage buckets, randomization.

Test Code base, Register map

Physical Design flows - Overview

Gate Netlist

Technology Library, Files

Clocking / Architecture

PPA Goals, Package,Aspect ratio, IO spec

FLOOR-PLAN, POWER-GRID

PLACEMENT OPTIMIZATION

STACLOCK-TREE SYNTHESIS

PLACE AND ROUTE, EXTRACTION

DFM - NOTCH/METAL FILL, DRC FIXES, ECOs

FINAL TIMING SIGN-OFF

LEC SIGN-OFF BACKEND SIGN-OFF TAPE

OUT

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