Thermal-Aware SoC Test Scheduling with Test Set

Partitioning and Interleaving

Zhiyuan He 1 , Zebo Peng 1 , Petru Eles 1 Paul Rosinger 2 , Bashir M. Al-Hashimi 2

1 Linköping University, Sweden2 University of Southampton, U.K.

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Core-based System-on-Chip• Integration of pre-designed and

pre-verified cores in a single chip

• Advantages• Reduced design complexity

• Lower cost

• Shorter time-to-market

• Challenges to testing• Large quantities of test data,

long test time

• High power consumption, high temperature

• Need efficient test approach

DRAM CPU

ROMANALOG

SRAM

RF

UDL

DSP

FPU

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Increasing Power Density

High power density high temperature on chip!

Source: Fred Pollack (Intel Corp.), Micro32, “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies”

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Thermal Issue in SoC Test

• Higher power dissipation during test than in normal operations [Pouya, ITC’00]

• High temperature during test• Slow down transistors

• Large RC delay

• High leakage

• Shorter lifetime

• Permanent damage

• Require temperature-aware test techniques

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Contribution

• An SoC test scheduling technique that

• Minimizes test application time

• Prevents over-heating during test

• Utilizing test set partitioning and interleaving

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Outline

• Basic Test Architecture

• Test Set Partitioning and Interleaving

• Problem Formulation

• Constraint Logic Programming (CLP)

• Experimental Results and Conclusions

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Basic Test Architecture

• Tester• Test controller

• Tester memory

• On-chip or external

• Test bus (single)• Bandwidth limit

• Dedicated TAM wires connecting cores to the test bus

Core 2Core 1

Test Bus

Tester

Test Controller

Tester Memory

Core 4Core 3

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Test Set Partitioning

Temperature

Time

Upper Temperature Limit Test Completion Time

TSi1 TSi2 TSi3Cooling Cooling Cooling TSi4

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Test Set Interleaving

Core 1

Core 2

Temperature

Time

TMmaxTest Completion

Test for Core 1

Test for Core 2

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The Basic Strategy

Generate an initial partitioning scheme(thermal-safe, min number of partitions)using temperature simulation (HotSpot)

Generate alternative partitioning schemes w.r.t. the number of partitions

Generate the optimal test schedule constrained by a bus bandwidth limit

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Assumption

• A test set is partitioned into test sequences with equal lengths, except the first one

• To simplify the test controller

• To reduce design space

Temperature

Time

Upper Temperature Limit Test Completion Time

TSi1 TSi2 TSi3Cooling Cooling Cooling TSi4

Temperature

Time

Upper Temperature Limit Test Completion Time

TSi1 TSi2 TSi3Cooling Cooling Cooling TSi4

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A Motivational ExampleBandwidth

0 Time

Bandwidth Upper Limit

TS32TS31

Test Completion

TS11 TS12 TS13 TS14 TS15

TS22TS21 TS23

Bandwidth

0 Time

Bandwidth Upper Limit

TS23TS21 TS22 TS24

TS11 TS12 TS13 TS14

Test Completion

TS31 TS32 TS33

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Test Time Minimization Problem• Input

• Test architecture• Test sets for all cores• Test bus bandwidth limit Bmax

• Temperature upper limit TMi,max for each core Ci

• Output• The optimized test schedule

• Objective• Minimize the total test time TTT• Subject to

–Total amount of bus bandwidth utilization B < Bmax

–Temperature of each core TMi < TMi,max

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Constraint Logic Programming

• Define relationships or constraints by using logic programming language

• Provide solvers to find optimal solutions• Exhaustive search

• Branch and bound

• CHIP• Developed by COSYTEC

• Uses Prolog

• Integrated solvers

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Experimental Results

# of Cores# of

Partitioning Schemes

Problem Size

Total Test Times

(# of clock cycles)

CPU Times (s)

4 7 28 2775 2.141

12 8 96 8306 35.359

24 20 480 9789 47.500

36 20 720 10017 120.219

48 20 960 10941 881.766

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Conclusions

• An exact approach to minimize total test time for SoC test under a temperature upper limit and bus bandwidth limit

• Proposed test set partitioning and interleaving techniques

• Optimal solution obtained by using constraint logic programming

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Thank you!