Issue 64 October 2014

Thermal Processing Part III - Oxidationand KineticsBy Christopher HendersonLast month we explored the topic of oxidation and kinetics inthermal processing. We’ll continue our discussion this month. Thereare three steps in the oxidation model. The first step is the gastransfer of oxygen from the ambient environment to the gas/oxideinterface. The second step is the diffusion of oxygen across the oxidelayer. The third step is the chemical reaction that occurs at the siliconsurface. The equations for each step are shown here.

F1 is the gas transport equation, F2 is the oxide diffusionequation, and F3 is the oxygen/silicon reaction equation. H sub G isthe mass transfer coefficient in gas, and H is Henry’s law constant.C star is defined as H times p sub G, where p sub G is the partialpressure of the oxidizing species in the bulk of the gas. D is thediffusivity of the oxidizing species in SiO2 and k sub s is the chemicalsurface reaction rate constant for oxidation.

Page 1 Thermal ProcessingPart III - Oxidationand KineticsPage 6 Technical TidbitPage 8 Ask the ExpertsPage 9 SpotlightPage 13 Upcoming Courses

 

   

Issue 64

2

October 2014

In the steady state condition F1 should equal F2 which should also equal F3. When the equations areset equal to one another, one can solve for the concentration at the surface of the oxide and theconcentration at the interface between the silicon and the silicon dioxide. When the diffusion constant Dis very small, the flux of oxygen through the silicon dioxide is small compared to the reaction rate at theinterface. This is known as the diffusion rate controlled case, indicated by the line shown here.

When the diffusion constant D is very large, an ample supply of oxygen can reach the interface. This isa reaction rate controlled case, indicated by the line shown here.If one solves for equation F3 (the reaction rate at the silicon/silicon dioxide surface) after applying theappropriate boundary conditions, one can obtain a solution for X, or the thickness of the oxide. This is asomewhat complicated differential equation boundary value problem, so we will not work it here.Basically, the thickness can be described under two different conditions: one where the time scale is quitelong, and one where the time scale is short. The short time scale describes the initial growth region, or thereaction rate limited case, and the long time scale describes the diffusion limited case. For short timeswhere t plus tau is much less than A squared over 4B, X sub O equals B over A times the quantity t plustau, where B over A is called the linear rate constant. For very long times where t is much greater than Asquared over 4B, X sub O squared equals B times t, where B is called the parabolic rate constant. These

Issue 64

3

October 2014

are the fundamental pieces of the Deal-Grove oxidation model, which we will cover next. The graph hereshows the composite of the two growth regimes, where oxide thickness is plotted against oxidation time.

Scientists have studied thermal oxidation for many years. Bruce Deal and Andrew Grove developedthe first model to explain thermal oxidation in the mid-1960s while working at Fairchild Semiconductor.Here we show the basic model, where x is the oxide thickness, B is the parabolic rate constant, B over A isthe linear rate constant, and tau is a factor to account for oxide present at the start of the oxidation.

Deal and Grove developed their model to agree with the two regimes, the linear growth regime andthe parabolic growth regime. In the linear growth regime, the rate of the oxidation reaction dominates.This regime occurs while the oxide layer is still thin, and diffusion of oxygen to the surface is unimpeded.So if B is much greater than B over A, the Deal-Grove equation reduces to this formula.

Issue 64

4

October 2014

In the parabolic growth regime, the diffusion of oxygen to the silicon-silicon dioxide interface isincreasingly limited. This regime occurs when the oxide increases beyond 500 angstroms. So in this case,if B over A is much greater than B, the Deal-Grove equation reduces to this formula.These graphs show the Deal-Grove oxidation model applied to both wet oxidation and dry oxidationexamples at various temperatures. We show the experimentally-derived constants in the tables below thegraphs. Notice that the Deal-Grove model shows a clear oxidation rate driven regime as well as a diffusionrate limited regime.

Issue 64

5

October 2014

This image shows a cross-section of the silicon dioxide growth in a LOCOS (pronounced “low-cos”)technology. In a LOCOS technology, process engineers grow a thermal oxide that serves as the isolationbetween transistors. A silicon nitride mask prevents the oxidation in the active region areas. Notice thatthe silicon dioxide has consumed a portion of the silicon, expanding down into the silicon itself. Theoriginal silicon surface is shown by the dotted line. There is even some growth of the oxide beneath theedge of the silicon nitride mask.

In conclusion, we discussed thermal oxidation and the kinetics of the reaction. While thermaloxidation is primarily driven by temperature, there are two regimes that also control the growth of theoxide: the oxidation rate-limited, or linear regime, and the diffusion rate-limited, or parabolic regime.Deal and Grove developed a model for thermal oxidation in the mid-1960s, and that model is still theprevailing model to explain and understand the first-order effects associated with oxidation.

Issue 64

6

October 2014

Technical TidbitProcess Capability IndexProcess Capability Index, or Cpk, is an important topic for Product and Manufacturing Engineers toknow. Cpk is an index in the form of a simple number which measures how close a process in running toits specification limits relatively to the natural variability of the process. The Cpk index is part of a seriesof indices that measure how much natural variation a process experiences relative to its specificationlimits and permits the engineer to compare different processes to one another with respect to theiroverall control. The larger the index number, the less like any particular data point will be outside thespecification limits. However, a large index is not necessarily a good thing, so engineers may tighten thelimits if there is a large Cpk. If Cpk is too large, one never sees an indication that prompts action to fix oroptimize the process.

This table describes the process capability indices and the equations to calculate them. Although thereare a number of indices, Cpk is the most popular. Process capability indices assume that one is dealingwith normally distributed data, and that may not always be the case. It’s important to remember thoughthat some data might have an upper bound, but no lower bound, or vice-versa. An example of this mightbe quiescent power supply current (IDDQ), or maximum frequency (Fmax). IDDQ typically has an upperbound, but no lower bound, whereas Fmax typically has a lower bound, but no upper bound.

Issue 64

7

October 2014

Let’s use a car and a garage as an analogy. The garage will define the specification limits, and the carwill define the output of the process. We show four scenarios with cars and garages. If my car is only alittle bit smaller than the garage, then I need to park it right in the middle of the garage (center of thespecification) if you want to get all of the car in the garage. This is similar to a Cpk of 1. It is a marginaloutcome. If my car is wider than the garage, it does not matter how I try to center it, because it will not fit.This is similar to a Cpk of less than 1. It is an unacceptable outcome. If my car is a lot smaller than thegarage, it doesn't matter if I park it exactly in the middle, because it will fit and have plenty of room oneither side. This is similar to a Cpk of greater than 1. If I can always park my smaller car in the center andwith little variation, then this is equivalent to the highest Cpk value, or a value that is much greater than 1.Cpk describes the relationship between the size of the car, the size of the garage and how far away fromthe middle of the garage I parked the car.

So what is an acceptable value? Clearly, values that are below 1 will be unacceptable, and a value of 1will be marginal, but what about larger values?

Issue 64

8

October 2014

In general in semiconductor manufacturing, we would like to see values equal to or greater than 2.00.This would constitute excellent process capability. A value of 1.33 would be acceptable, and a value of1.67 would be good. These numbers will obviously vary depending on the process and the type of testingperformed to generate the data. Some procedures like trim tests will have lower Cpks, but that is notnecessarily a problem, as the purpose of trimming is to improve Cpk.

Ask the Experts

Q: How do you adequately protect high speed signal interfaces like LVDSinterfaces from ESD and EOS?

A: This is a difficult task. The problem is that high speed signal interfaces requirehigh performance transistors, which are small and sensitive to overstress. Thismeans that to protect them from overstress events, particularly overstress eventslike charged device model ESD pulses, one must place resistors on the gates of theinput transistors, or in series with the output. Unfortunately, this will slow downthe operation of the circuits. This places the designer between a rock and a hardplace. If one really needs a combination of high speed with additional protection,then one may need to consider other interface schemes that are not directelectrical connections, like optical connections or RF energy connections.

Issue 64

9

October 2014

Spotlight: IC Packaging Design and ModelingWe have had some interest in running our IC Packaging Design and Modeling Course in the nearfuture. We show the course overview and outline below. Please contact us at info@semitracks.com or1-505-858-0454 if you are interested in attending this course. We can also run this course as an in-housecourse in certain instances as well.OVERVIEWSemiconductor and integrated circuit developments continue to proceed at an incredible pace. Forexample, today’s microprocessor chips have one thousand times the processing power of those a decadeago. These challenges have been accomplished because of the integrated circuit industry’s ability to tracksomething known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power willdouble every two years. This has been accomplished by making devices smaller and smaller. Theindustry is also pushing to use semiconductor devices in an increasing array of applications. Toaccomplish this, the industry is also driving prices down. This has created a number of challenges relatedto the packaging of these components. IC Packaging Design and Modeling is a 3-day course that offersdetailed instruction on the design and modeling of IC packages. We place special emphasis on packageinteractions with the die. This course is a must for every manager, engineer, and technician working in ICpackaging, using IC components in high performance applications or non-standard packagingconfigurations, or supplying packaging tools to the industry.By focusing on the fundamentals of packaging design and modeling, participants will learn whyadvances in the industry are occurring along certain lines and not others. Our instructors work hard toexplain semiconductor packaging without delving heavily into the complex physics and materials sciencethat normally accompany this discipline.Participants learn basic but powerful aspects about the semiconductor packaging. This skill-buildingseries is divided into four segments:1. Packaging Design Overview. Participants learn the fundamentals of packaging design. Theylearn why modeling has become critical to semiconductor packaging for today’s designs.2. Mechanical Simulations. Participants learn the fundamentals of displacement, strain, stress, andenergy. They learn how to leverage St. Venant’s Principle and apply fracture mechanics to aproblem.3. Thermal Simulations. Participants learn heat transfer modeling. They also learn about steady-state and transient thermal modeling. The instructor also explains industry standard and compactthermal models.4. Modeling Semiconductor Packages. Participants learn about the software used for modeling avariety of aspects of semiconductor packaging. They see a number of examples using currentmodeling tools used by Package Design experts.COURSE OBJECTIVES1. The seminar will provide participants with an in-depth understanding of semiconductor packagingdesign and its technical issues.

Issue 64

10

October 2014

2. The participant will understand the basic concepts behind thermal and mechanical simulations ofpackages.3. The seminar will identify the key issues related to the continued growth of the semiconductorindustry. This includes the need for high power dissipation, and designs that can mitigate theincreasing fragility of the die because of low-k dielectrics.4. The seminar offers a wide variety of sample modeling problems that participants work in class to helpthem gain knowledge of the fundamentals of packaging modeling.5. The participant will be able to identify basic and advanced principles for mechanical stress andthermal diffusion.6. The participant will understand how package reliability, power consumption and device performanceare inter-related.7. The participant will be able to make decisions about how to construct and evaluate new packagingdesigns and technologies.8. The participant will also be introduced to wafer-level simulations, which are increasingly necessarywith the advent of low-k dielectrics.INSTRUCTIONAL STRATEGYBy using a combination of instruction by lecture, classroom exercises, problem solving, andquestion/answer sessions, participants will learn practical information on semiconductor packaging andthe operation of this industry. From the very first moments of the seminar until the last sentence of thetraining, the driving instructional factor is application. We use instructors who are internationallyrecognized experts in their fields that have years of experience (both current and relevant) in this field.COURSE OUTLINE1. Package Design Principlesa. Backgroundb. ITRS Roadmap Issuesc. JEDEC Standards for Packagingd. Semiconductor Package Designs: What is a Good Packaging Design?e. Modeling Software2. Assembly and Packaging Processesa. Assembly and Packaging Processesb. Selecting Package Materialsc. Advanced Packagingd. Stacked Die & Stacked Packagese. Through Silicon Via (TSV) Interconnects3. Stress Simulationsa. Solid Mechanics Conceptsi. Basics of Displacement, Strain, Stress and Energyii. Leveraging St. Venant’s Principleiii. Applying Fracture Mechanics

Issue 64

11

October 2014

b. Manufacturabilityi. Thermomechanical Modeling Metricsii. To Model or Not to Modeliii. Assembly Process Simulations4. Thermal Simulationsa. Heat Transfer Principlesb. JEDEC Thermal Test and Simulationsc. Steady-State and Transient Thermal Modelingd. Application-Specific Thermal Simulationse. Using Compact Thermal Models5. Reliability and Coupled Mechanicsa. Thermomechanical Reliabilityi. Solder Joint Reliability (SJR)ii. Single Chip & Multiple Chip Package SJRiii. Solder Joint Shape Predictionsb. Coupled Mechanicsi. Moisture Diffusionii. Plastic Package “Popcorn” Cracking6. Wafer-Level Simulationsa. Venturing into New Territory (Submodeling)b. Chip-Package Interactionsi. Interfacial Fracture Mechanicsii. Bridging IC Interconnect and Package Gapsc. Microelectromechanical Systems (MEMS)i. Device Operationsii. MEMS Packaging7. Drop Tests SimulationsIC Packaging Design and Modeling Course Outline- 2a. Drop Test & Structural Dynamicsb. Solder Selection & Performancei. Leaded Soldersii. Lead-Free Soldersiii. Surface Finishes, Solder Pastes, & Metallizationc. Package Design Effects i. Stand-Off Heightsii. Ball Array Patterniii. Single Chip & Multiple Chip Packages

Issue 64

12

October 2014

Semitracks will exhibit at this year's International Symposium forTesting and Failure Analysis. Please stop by and see us (booth 725). Callus at 1-505-858-0454 or email us at info@semitracks.com to schedule.

40th Annual International Symposiumfor Testing and Failure Analysis

Conference and Exposition

November 9 – 13 • Houston, TexasStop by and see us!

For more information on the symposium, visithttp://www2.asminternational.org/content/Events/istfa

Please feel free to contact us to set up an appointmentwhile you are there!

Issue 64

13

October 2014

Upcoming Courses(Click on each item for details)Product QualificationJanuary 26 – 27, 2015 (Mon – Tue)San Jose, California, USAWafer Fab ProcessingJanuary 26 – 29, 2015 (Mon – Thur)San Jose, California, USA

EOS, ESD and How to DifferentiateJanuary 28 – 29, 2015 (Wed – Thur)San Jose, California, USAFeedbackIf you have a suggestion or a comment regarding our courses, onlinetraining, discussion forums, or reference materials, or if you wish tosuggest a new course or location, please call us at 1-505-858-0454 orEmail us (info@semitracks.com).To submit questions to the Q&A section, inquire about an article, orsuggest a topic you would like to see covered in the next newsletter,please contact Jeremy Henderson by Email(jeremy.henderson@semitracks.com).We are always looking for ways to enhance our courses and educationalmaterials.~For more information on Semitracks online training or public courses,visit our web site!http://www.semitracks.com

To post, read, or answer a question, visit our forums.We look forward to hearing from you!