tips and tricks with dma on mpc56xx - nxp semiconductors · 2016. 3. 21. · support for...

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLinkand VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-AUT-F0451

Tips and Tricks with DMA on MPC56xx

June, 2010

David CermakSystems Application Engineer


Session Introduction

►Using enhanced Direct Memory Access (eDMA) on the MPC56xx to emulate SPI/SCI* communication

►Useful techniques with eDMA• Friendly guide to DMA configuration• From simple transfers to complex linkage configuration

►David Cermak -- Systems Application Engineer• SW Verification and Validation Team• Development of automated test system• AUTOSAR MCAL for MPC56xx platform

►Question and Answer►Time to finish: About one hour

* Definitions: SPI - Serial Peripheral Interface; SCI - Serial Communications Interface

2


Session Objectives

►By completing this training, you will be able to:• Configure and use your eDMA peripheral to

Perform complex data transfers linking and prioritizing multiple channelsSend and receive data on SPI/SCI

• Implement DMA to efficiently balance your application performance• Effectively employ described techniques for parallel and serial access in

your application• Utilize advanced features of eDMA peripheral on the MPC56xx

3

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLinkand VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 44

Agenda

►Overview of eDMA on the MPC56xx

• Features and options

• Peripherals eDMA and DMA channel mux

• Devices and peripherals

►Configuration and simple DMA transfers

• Transfer Control Descriptor

• DMA common use

• Single SCI transfer


Agenda (continued)

►SPI emulation example• SPI master

• SPI slave

►SCI emulation example• SCI receiver

►Demonstration

►Other ideas with eDMA

►Wrap up


eDMA Basic Features

►All data movements occur via dual address transfers• Programmable source address• Destination address• Transfer size• Support for enhanced addressing mode

► Transfer control descriptor (TCD) is organized to support two-deep, nested transfer operations

• Inner data transfer - minor byte count• Outer data transfer loop - major iteration count

► Activation• Requires explicit SW• Channel-to-channel linking• Peripheral paced HW requests

6


eDMA Basic Features (continued)

►Fixed priority or round robin arbitration • Separately configurable for groups and for channels

►Optional interrupt requests• Upon completion of a major loop• Error terminations are enabled per channel and summed to form one

interrupt►Support for scatter/gather DMA processing

• Pointer to the next TCD to be loaded to channel after completion of major loop

►Channel preempting• Any channel can be suspended by a higher priority channel before

completion of a minor loop

7


eDMA and DMA Channel Mux

►eDMA performs actual data movements

►Configuration based on TCD (transfer control descriptor)

• Source address, increment• Destination address, increment• Iteration count (major, minor)

• Channel linking

8


eDMA and DMA Channel Mux

►DMA channel multiplexer routes requests to DMA channels

►Channel configuration options:• Periodic triggering capability• No triggering capability• Always enabled channels

9


DMA Channels and Multiplexing Options

10

Device DMA DMA channel muxMPC5606S 16 channels 21 sources, 4 periodic

MPC5604P 16 channels 21 sources, 4 periodic

MPC5604B -- --

MPC5607B 16 channels 59 sources, 4 periodic

MPC563XM 32 channels Sources hardwired

MPC5643L 16 channels 27 sources, 4 periodic

MPC5646A 64 channels --

MPC5646C 32 channels --

MPC5668GE 32 channels 55 sources,4 periodic

MPC5674F 32 + 64 channels --

TM

Configuration and Simple DMA Transfers

11


Configuration

►Transfer Control Descriptor (TCD)

• 32 bytes• Source• Destination• Attributes• Control/Status

12

Source Address

Transfer Attributes (mod,size) Signed Source Address Offset

Inner “Minor” Byte Counts (offset per minor iteration)

Last Source Address Adjustment

Destination Address

Current “Major” Iteration Count

Signed Destination Address Offset

Last Destination Address Adjustment (scatter/gather)

Beginning “Major” Iteration Count Channel Control/Status


Common Use

►Buffering ADC results

• Route ADC done flag to appropriate channel

• Configure TCD• Receive interrupt

when half major loop is finished

13

Source Address = &ADC.result

Size = 32 bit Offset = 0

Minor Loop = 4 bytes

Last Source Address Adjustment = 0

Destination Address = &Buffer

Current Iteration = Buffer_size Offset = 4 bytes

Last Destination Address Adjustment = - Buffer_size * 4 bytes

Start Iteration = Buffer_size EN INT in half


Single SCI Transfers

►SCI emulation in software• Driving GPIO pins in digital output mode – i.e. writing to

registers• Changing digital output periodically at exact times• Setting one bit of a word to be sent at a time.

STA

RT

STO

P1 0 1 0 1 1 0 0

DMA: data movement

DMA: triggering by periodic interrupt timer (PIT)

DMA: need to move one byte at a time as per an example in the next slide


►Example: • Byte array representation of one

transmission, including start and stop bit.

0x00

0x01

0x00

0x01

0x00

0x01

0x01

0x00

0x00

0x01

MPC56xx

eDMA

PITS

TAR

T

STO

P1 0 1 0 1 1 0 0

DATA=b’00110101’=0x35

uint8_t bitsToSend[10]= {0 /* START BIT */,1, 0, 1, 0, 1, 1, 0, 0 /* DATA 0x35*/, 1 /* STOP BIT */ };

DMA source address: &bitsToSend



0x01

0x00

0x00

0x01

0x01

0x00

0x01

0x00

0x01

0x00

MPC56xx

eDMA

PITS

TAR

T

STO

P1 0 1 0 1 1 0 0

DATA=b’00110101’=0x35

…. 1 0 0 1 1 0 1 0 1 0 …

PGPDO_0(15:8)

GPDO_8–GPDO_15



0x01

0x00

0x00

0x01

0x01

0x00

0x01

0x00

0x01

0x00

MPC56xx

eDMA

PITS

TAR

T

STO

P1 0 1 0 1 1 0 0

DATA=b’00110101’=0x35

…. 1 0 0 1 1 0 1 0 1 0 …

PGPDO_0(15:8)

GPDO_8–GPDO_15Tip:•Use serial GPIO registers for byte access by DMA•Use parallel PGPDI/O registers for whole word access by application SW

•Unused x GPIO pins in a row -- normal pins, which are not used by customer application in GPIO mode•Phantom register of non-existent pins or GPIO pins not connected to package (i.e. unusable pins)

Definitions : GPIO - General Purpose Input/Output ; PGPDI/O – Parallel access GPIO registers


TM

SPI Emulation Example

18


SPI Emulation – Application

►Application example: Automated Test System –testing AUTOSAR SPI driver

• All SPI nodes are used for acquisition test data• Need another SPI node for configuration• Minimum CPU load

19

5517*

CPLD*

SPI signal under test -> need maximum number of nodes

Configuration – SPI-> need to configure with minimum CPU intervention


SPI Emulation

►Example:

Features used:►Channel to channel linking is possible

• After major loop completion• After major loop iteration

►Trigger channels from peripherals

20


SPI Emulation

Nodes:►SPI master

• Similar to SCI• Three (3) channels linked• Similar to SCI transmitter, but more signals

►SPI slave• Triggered external interrupt pin• Three (3) channels

21


CH0 -- SCKuint8_t sckPattern={

};

0x000x01

source dest

SCK

CH1 -- SOUTsource destination

SOUT

CH2 -- SIN

destination source

SIN

iteration link

completion link

0x000x010x010x000x010x00

0x000x010x010x000x010x00

GPDO registers

Serial Clock

Serial Out

Serial In

SPI Master


CH0 -- SCKuint8_t sckPattern={

};

0x000x01

source dest

SCK

CH1 -- SOUTsource dest

SOUT

CH2 -- SOUT

dest source

SIN

iter link comp link

0x000x010x010x000x010x00

0x000x010x010x000x010x00

GPDO registersTip:Chaining Minor loop completion • Major loop channels after both of the following:• completion, which takes priority•can be used to divide into odd and even jobs

SPI Master


SPI Master – Triggering

►Generating an SPI clock• In GPIO mode

DMA channel in periodic triggering capabilityTriggered by periodic interrupt timer (PIT)

• In eMIOS (enhanced Modular IO Subsystem) mode

Each channel has one DMA requestChannel 0 (CH0) to generate pulses and trigger SPI data read (DMA CH1)CH0 to trigger SPI data write (DMA CH2)

24

DMA CH0 -- SCK

source dest

SCK

PIT

EMIOS0 -- SCK SCK

CH1 SIN

EMIOS1 -- trig

SAOC

NC

SAOC

CH2 SOUT

Not connected


SPI Master – Triggering

►Generating SPI clock• In GPIO mode

DMA channelPeriodic triggering capability

• In eMIOS modeEach channel – one DMA requestCH0 to generate pulses and trigger SPI data read (DMA CH1)CH0 to trigger SPI data write (DMA CH2)

25

DMA CH0 -- SCK

source dest

SCK

PIT

EMIOS0 -- SCK SCK

CH1 SIN

EMIOS1 -- trig

SAOC

NC

SAOC

CH2 SOUT

Tip:•Unconnected eMIOS channels can be used:

As timersTo trigger DMA channels


CH0 -- SCKuint8_t startChan={

};

0x010x02

source

dest

SCK


SOUT

CH2 -- SIN

dest source

SIN

0x000x010x010x000x010x00

0x000x010x010x000x010x00

GPDO DMA_start

SPI Slave


CH0 -- SCKuint8_t startChan={

};

0x010x02

source

dest

SCK


SOUT

CH2 -- SIN

dest source

SIN

0x000x010x010x000x010x00

0x000x010x010x000x010x00

GPDO DMA_start

Tip:•Transfer channel number to SSBR could be used as dynamic linking

SPI Slave

TM

SCI Emulation Example

28


SCI Emulation – Application

►Application example:• All LINFlex peripherals are used by the application• Need printf function for debugging/testing• Minimum CPU load

29

printf

SCI: debug info


SCI Emulation

►Features used:• Channel-to-channel

linking• Channel trigger• Scatter/gather feature

►Modes:• Tx - Transmitter

1 channel only

• Rx - ReceiverNeeds triggeringQuite complex

• Both Rx and TxTiming constraints

30


Signal which appears on GPIO pin

STA

RT

STO

P1 0 1 0 1 1 0 0

Start reading

Data readingDATA=b’00110101’=0x35

DMA: trigger from interrupt pin

Stop reading

DMA: data movements

DMA: disable channel after completion

SCI Reception


SCI Receiver

►Start reading• Trigger to falling edge• Disable the trigger• Start timer

►Reading data bits• Sampling data• After all the data, check the stop bit

►Stop reading• Stop the timer• Enable trigger to falling edge

32

STA

RT

STO

P1 0 1 0 1 1 0 0

DATA=b’00110101’=0x35


Transfer Control Descriptors (TCDs) Channel 0

Channel 1

Channel 2

Source Memory Location

Destination Memory Location

Linking –chaining

Note: The source the destination memory are displayed as separate entities only to demonstrate the data movements

Normal eDMA Multichannel Processing


Transfer Control Descriptors (TCDs) Channel 0

Channel 1

Destination Memory Location

pointer

User TCD

User TCD

pointer

User TCD

pointer

Channel 2

►After completion of major loop of channel 0, this TCD defines next transfers for channel 0

eDMA Scatter Gather Principle


eDMA Scatter Gather Description

►Transfer Control Descriptor (TCD) contains information about • The Transfer itself (source, destination addresses, size)• Links to other channels• Links to other TCD’s – scatter-gather feature

►Upon completion of major loop for given channel (if scatter-gather is enabled)

• Pointer to the next TCD is de-referenced and loaded into this channel• Further transfers are defined using new TCD

►Use case• Multiple data movements of dissimilar properties• Limited number of channels

35


SCI Receiver

►Channel 0• Trigger to falling edge• Disable the trigger• Start timer

►Channel 1• Sampling data• After all the data, check the

stop bit• Stop the timer• Enable the trigger to falling

edge

36

STA

RT

STO

P1 0 1 0 1 1 0 0

DATA=b’00110101’=0x35


SCI Receiver

►Channel 0• Trigger to falling edge• Disable the trigger• Start timer

►Channel 1• Sampling data• After all the data, check the

stop bit• Stop the timer• Enable the trigger to falling

edge

37

STA

RT

STO

P1 0 1 0 1 1 0 0

DATA=b’00110101’=0x35

Tip:•Complex transfers within limited number of channels could use scatter-gatheroperation to service multiple heterogeneous data movements.

TM

Demonstration

38


Demonstration Section

►SCI communication• Sending data to serial line

►SPI• Sending data from and to the chip itself

39


►Connections can be made:• Using DPSI* as Master• Using emulated SPI as slave

Including CS**Using 4 channels

*DSPI: MPC56xx SPI peripheral (Deserial SPI)**CS: Chip select

DSPI_0

CS PA1

SCK PA2

SIN GPIO

SOUT GPIO

DM

A s

SPI Emulation Demo

TM

Other ideas with DMA

41


►Motor control• ADC – triggering at Pulse Width Modulation (PWM)

high side• Commutation• Sine wave generation

►Flash programming• Sequence of register writes

►Watchdog• Trigger reset on timer overflow• GPIO pin is wired to the RESET pin

42

RE

SE

T

GPIO

Other Ideas with eDMA


►Touch-sensing1. Set GPIO as output low – discharging the capacitor2. Set as input capture unit – waiting till the capacitor charges3. Compare measured time and raise an interrupt4. Go to 1) – discharge the capacitor again

43

GPIO

Time

Vol

tage

on

GP

IO

1

2

3

Charge time

Capacity increase detected

Charge time

High Level DetectedHigh

Low

Other Ideas with eDMA


Session Summary

►Basic features of eDMA ►Serial communication with eDMA►Advanced features

• Channel-to-channel linking• Scatter-gather operation

44


Session Wrap-Up

►By now, you should be able to:• Configure and use your eDMA peripheral to

Implement complex data transfers via linking and prioritizing multiple channelsSend and receive data on SPI/SCI

• Implement DMA to efficiently balance your application performance• Effectively employ described techniques for parallel and serial access in

your application• Begin to use advanced features of eDMA peripheral on MPC56xx

45


Questions & Answers

46


For Further Information

►http://www.freescale.com►[email protected]►AN4147: Tips and Tricks with DMA on MPC56xx ►MPC56xx Reference Manual

• Power Architecture Processors• Power Architecture Controllers (5xx/5xxx)• 56XX Controllers

http://www.freescale.com/

tips and tricks with dma on mpc56xx - nxp semiconductors · 2016. 3. 21. · support for...

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