dma 与 dma 控制器
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DMA 与 DMA 控制器. DMA(Direct Memory Access) 的概念 DMA 方式不用处理器干预完成 M 与 I/O 间数据传送。 DMA 期间系统总线由其它主模块控制 ( 驱动 ) 控制总线的主模块要提供系统的地址及控制信号。 DMA 控制器与处理器配合可实现系统的 DMA 功能。. DMA 与 DMA 控制器（续）. 2. DMA 系统组成及工作过程 ․ DMA 系统组成. 地址总线. HOLD HLDA. 总线 请求. DMA 请求. I / O 设备. - PowerPoint PPT PresentationTRANSCRIPT
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DMADMADMA(Direct Memory Access)DMAMI/ODMA()DMADMA
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HRQ DREQDMACHLDA DACK HOLD
HLDA
CPUDMADMAI / ODMADMA2. DMA DMA
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DMADMA2. DMA DMA
I/ODMAC DMAC CPU DMAC CPU DMAC I/O
DMADMA
DMACDMAC
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DMA DMADMACBUSCPUDMABUSDMAC NDMANY YDMA
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DMADMADMACBUSCPU DMA BUSDMAC DMANYYNDMA
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DMA DMADMACBUSCPUDMADMAC YDMAYNNYDEMAND REQUESTDMA
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REG. 8 HRQAddr.Temp.16Count Temp. 16 REG. 8 8HLDARENMODE REG.6REQ1FLAG1MASK FLAGADDR..REG. 16 REG. 16.16REG.16 0123HOLDHLDACLOCKAENCPUEN#STBADSTBDB7 DB0IO / M#CS#ADDR.
DATA SUBA15~A8A7~A0A3~A0A7~A4IOR#MEMR#IOW#MEMW#READYRESETDREQ0DACK0DREQ1DACK1DREQ2
DREQ3
DACK2DACK3EOP#3.Intel 8237ADMA
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DMADMA3.Intel 8237ADMA(8237ADMAC8237AI/O8237A8237A-8237A8237A16REG166REG8
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DMADMA3.Intel 8237ADMA(8237ADMARAM DMA, DMA DMA,
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DMADMA3.Intel 8237ADMA(8237ADB7-DB08237ADB7-DB08237ADB7-DB0A15-A8 M MDB7-DB0M8237AA3-A48237A
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DMADMAA7-A4A7-A4CS#8237AIOR#IOW#I/O8237AAENADSTB88237A8MEMR#MEMWREADY
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DMADMARESET10EOP#DMADREQ0-DREQ3I/ODMADACK0-DACK3DMAHRQ8237AHLDA8237A
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REGISTERCS #10R# 10W# A3 A2 A1 A0 F/FDB0~DB7000 1111 / / / / 0 1 0 0 1 00 0 10 0 1 0 1 0 0 1 0 0 0 1 0 0 1
0 1 00 1 00 0 10 0 1
0 0 10 0 10 1 00 1 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 10 0 0 10 0 0 10 0 0 10 0 1 00 0 1 00 0 1 00 0 1 00 0 1 10 0 1 10 0 1 10 0 1 1 0 1 0 1010101010101 A0 ~ A7 A8 ~ A15 A0 ~ A7 A8 ~ A15W0 ~ W7W8 ~ W15W0 ~ W7W8 ~ W15W0 ~ W7W8 ~ W15W0 ~ W7W8 ~ W15A0 ~ A7A8 ~ A15A0 ~ A7A8 ~ A158237A 18237A0
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REGISTERCS #10R# 10W# A3 A2 A1 A0 F/FDB0~DB722 3333 / / / / 0 1 0 0 1 00 0 10 0 1 0 1 0 0 1 0 0 0 1 0 0 1
0 1 00 1 00 0 10 0 1
0 0 10 0 1
0 1 00 1 00 1 0 00 1 0 00 1 0 00 1 0 00 1 0 10 1 0 10 1 0 10 1 0 10 1 1 00 1 1 00 1 1 00 1 1 00 1 1 10 1 1 10 1 1 10 1 1 1 0 1 0 1010101010101 A0 ~ A7 A8 ~ A15 A0 ~ A7 A8 ~ A15W0 ~ W7W8 ~ W15W0 ~ W7W8 ~ W15W0 ~ W7W8 ~ W15W0 ~ W7W8 ~ W15A0 ~ A7A8 ~ A15A0 ~ A7A8 ~ A158237A 222
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A3 A2 A1 A0 IOR# IOW# 1 0 0 0 0 1 REG. 81 0 0 0 1 0 / REG. 1 0 0 1 0 1 91 0 0 1 1 0 DMA REG. 1 0 1 0 0 1 A1 0 1 0 1 0 REG. 1 0 1 1 0 1 B1 0 1 1 1 0 REG.1 1 0 0 0 1 C1 1 0 0 1 0 F/F 1 1 0 1 0 1 D 1 1 0 1 1 0 1 1 1 0 0 1 E1 1 1 0 1 0 / REG.1 1 1 1 0 1 F1 1 1 1 1 0 REGDB
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8237A REG. B D7D6D5 D4
D3D2D1D0 0 00011111 01 1 0 1 0 0# Channel 0 0 1 11 01 1# Channel 2# Channel 3# Channel 0 0 001111 X X D7 D6=11
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8237A /REG. 88237A D7D6D5 D4
D3D2D1D0DACK 0 1 01DREQ MEM.0 11 001 Enable 8237A 01D3=1 X01MEM. Channel 0 XDisableEnable D0=08237A Disable 8237A01 XD0=1
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8237A DMA REG. 9 D7D6D3D2D1D0D5D40DMADMA100Channel 0001111Channel 1
Channel 2
Channel 3 8237A /REG. 9
8237ADMA
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8237A REG. A D7D6D3D2D1D0D5D40 MASK MASK 100Channel 0001111Channel 1
Channel 2
Channel 3 8237A /REG. A8237A
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8237A 4 MASK REG. F D7D6D3D2D1D0D5D40 Channel 3 M Channel 3 M 10011
0 Channel 2 M 1 Channel 2 M
Channel 0 Mask
Channel 0 Mask Channel 1 Mask
Channel 1 Mask 8237A /REG. F8237A
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DMADMA8237A3DBCF/FLSBMSBDREG.1REG.0 E
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HLDA8237APHRQ8237A8237A804HMaster Clear)0DH8237ADMA
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8237A REG. 8 D7D6D3D2D1D0D5D4 3 DMA 11 0 2DMA 1
1 DMA 1
0 DMA 1
1 11 21 38237A8237A