tlc372 lincmos dual differential comparators

8/14/2019 Tlc372 Lincmos Dual Differential Comparators

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TLC372LinCMOS DUAL DIFFERENTIAL COMPARATORS

SLCS114E NOVEMBER 1983 REVISED JULY 2008

1POST OFFICE BOX 655303 DALLAS, TEXAS 75265

D Single or Dual-Supply Operation

D Wide Range of Supply Voltages 2 V to 18 V

D Low Supply Current Drain150 A Typ at 5 V

D Fast Response Time . . . 200 ns Typ for

TTL-Level Input StepD Built-in ESD Protection

D High Input Impedance . . . 1012 Typ

D Extremely Low Input Bias Current

5 pA Typ

D Ultrastable Low Input Offset Voltage

D Input Offset Voltage Change at Worst-CaseInput Conditions Typically 0.23 V/Month,Including the First 30 Days

D Common-Mode Input Voltage RangeIncludes Ground

DOutput Compatible With TTL, MOS, andCMOS

D Pin-Compatible With LM393

description

This device is fabricated using LinCMOS

technology and consists of two independentvoltage comparators, each designed to operatefrom a single power supply. Operation from dualsupplies is also possible if the difference betweenthe two supplies is 2 V to 18 V. Each devicefeatures extremely high input impedance

(typically greater than 1012), allowing directinterfacing with high-impedance sources. Theoutputs are n-channel open-drain configurationsand can be connected to achieve positive-logicwired-AND relationships.

The TLC372 has internal electrostatic discharge(ESD) protection circuits and has been classifiedwith a 1000-V ESD rating using human bodymodel testing. However, care should be exercisedin handling this device as exposure to ESD mayresult in a degradation of the device parametric

performance.

The TLC372C is characterized for operation from 0C to 70C. The TLC372I is characterized for operation from40C to 85C. The TLC372M is characterized for operation over the full military temperature range of 55Cto 125C. The TLC372Q is characterized for operation from 40C to 125C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright 19832008, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing doesnot necessarilyincludetesting of all parameters.

1

2

3

4

8

7

6

5

1OUT

1IN

1IN+

GND

VCC2OUT

2IN

2IN+

TLC372C, TLC372I, TLC372M, TLC372Q

D, P, OR PW PACKAGE

TLC372M . . . JG PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC

2OUT

NC

2IN

NC

NC

1IN

NC

1IN+

NC

TLC372M . . . FK PACKAGE

(TOP VIEW)

NC1OUT

NC

2IN+NC

NC

NC

GNDNC

OUT

IN+

symbol (each comparator)

IN

NC No internal connection

VDD

1

2

3

4

5

10

9

8

7

6

NC

1OUT1IN

1IN+

GND

NC

VCC2OUT

2IN

2IN+

TLC372M

U PACKAGE

(TOP VIEW)

LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.


2/22



2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

equivalent schematic (each comparator)

Common to All Channels

VDD

GND

OUT

IN + IN

AVAILABLE OPTIONS(1)

PACKAGED DEVICES

TAVIO max

AT 25CSMALL

OUTLINE(D)(2)

CHIPCARRIER

(FK)

CERAMICDIP(JG)

PLASTICDIP(P)

TSSOP(PW)

CERAMICFLAT PACK

(U)

0C to 70C 5 mV TLC372CD TLC372CP TLC372CPW

40C to 85C 5 mV TLC372ID TLC372IP

55C to 125C 5 mV TLC372MD TLC372MFK TLC372MJG TLC372MP TLC372MU

40C to 125C 5 mV TLC372QD TLC372QP

1.For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web

site at www.ti.com.

2.The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC372CDR).


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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Differential input voltage, VID (see Note 2) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input voltage range, VI 0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output voltage, VO 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current, II 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output current, IO 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duration of output short circuit to ground (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Package thermal impedance, JA (see Notes 6 and 7): D package 97.1C/W. . . . . . . . . . . . . . . . . . . . . . . . . .

P package 84.6C/W. . . . . . . . . . . . . . . . . . . . . . . . . .PW package 149C/W. . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, JC (see Notes 6 and 7): FK package 5.6C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .JG package 14.5C/W. . . . . . . . . . . . . . . . . . . . . . . . .

U package 14.7C/W. . . . . . . . . . . . . . . . . . . . . . . . . .Operating free-air temperature range, TA: TLC372C 0C to 70C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC372I 40C to 85C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TLC372M 55C to 125C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TLC372Q 40C to 125C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range 65C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Case temperature for 60 seconds: FK package 260C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package 260C. . . . . . . . . . . .Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U package 300C. . . . . . . . . . . . . . .

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 3. All voltage values except differential voltages are with respect to network ground.

4. Differential voltages are at IN+ with respect to IN .

5. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.

6. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowableambient temperature is PD = (TJ(max) TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability.

7. The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).

recommended operating conditions

TLC372C TLC372I TLC372M TLC372Q

MIN MAX MIN MAX MIN MAX MIN MAXUNIT

Supply voltage, VDD 3 16 3 16 4 16 4 16 V

VDD = 5 V 0 3.5 0 3.5 0 3.5 0 3.5

Common-mode input voltage, VIC VDD = 10 V 0 8.5 0 8.5 0 8.5 0 8.5V

Operating free-air temperature, TA 0 70 40 85 55 125 40 125 C


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TLC372


emp a e e ease a e:

DUAL DIFFERENTIAL COMPARATORSLinCMOS


electricalcharacter

isticsatspecifiedfree-airtem

perature,

VDD=5V(unlesso

therwisenoted)

TLC372C

TLC372I

TLC372M,

TL

C372Q

PARAMETER

TESTCONDITIONS

TA

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TY

P

MAX

UNIT

25C

1

5

1

5

1

5

VIO

Inputoffsetvoltage

VIC

=VICRmin,

SeeNote4

Fullrange

6.5

7

10

mV

25C

1

1

1

pA

IIO

Inputoffsetcurrent

MAX

0.3

1

10

nA

25C

5

5

5

pA

IIB

Inputbiascurrent

MAX

0.6

2

20

nA

Common-modeinp

ut

25C

0to

VDD1

0to

VDD1

0to

VDD1

VICR

-

voltagerange

Fullrange

0to

VDD1.5

0to

VDD1.5

0to

VDD1.5

V

VOH

=5V

25C

0.1

0.1

0.1

nA

IOH

High-leveloutputc

urrent

VID

=1V

VOH

=15V

Fullrange

1

1

3

A

25C

150

400

150

400

15

0

400

VOL

Low-leveloutputvoltage

VID

=1V,

IOL=4mA

Fullrange

700

700

700

mV

IOL

Low-leveloutputcurrent

VID

=1V,

VOL=1.5V

25C

6

16

6

16

6

1

6

mA

Su

l

current

25C

150

300

150

300

15

0

300

IDD

(twocomparators)

VID

=1V,

Noload

Fullrange

400

400

400

A

Allcharacteristicsaremea

suredwithzerocommon-modeinputvoltageunlessotherwisenoted.Fullrangeis0C

to70C

forTLC372C,40C

to85C

forTL

C372I,and55C

to

125C

forTLC372Mand

40C

to125C

forTLC372Q.IMPORTANT:

SeeParameterMeasurementInformation.

NOTE8:

Theoffsetvoltage

limitsgivenarethemaximumvaluesrequire

dtodrivetheoutputabove4Vorbelow400

mVwitha10-kresistorbetweentheoutpu

tandVDD.Theycan

beverifiedbyapp

lyingthelimitvaluetotheinputandcheckin

gfortheappropriateoutputstate.

switchingcharacteristics,

VDD=5V,

TA=25C

PARAMETER

TESTCONDITIONS

MIN

TYP

MAX

UNIT

R

connectedto5Vthrou

h5.1k,C

=15pF,

100-mVinputstepwith5-mV

overdrive

650

Responsetime

.

,

=

,

SeeNote5

TTL-levelinputstep

200

ns

CLincludesprobeandjigcapacitance.

NOTE9:

Theresponsetim

especifiedistheintervalbetweentheinput

stepfunctionandtheinstantwhentheoutp

utcrosses1.4V.


5/22




electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25C (unless otherwisenoted)

TLC372Y

PARAMETER TEST CONDITIONSMIN TYP MAX

UNIT

VIO Input offset voltage VIC = VICRmin, See Note 4 1 5 mV

IIO Input offset current 1 pAIIB Input bias current 5 pA

VICR Common-mode input voltage range0 to

VDD1V

IOH High-level output current VID = 1 V, VOH = 5 V 0.1 nA

VOL Low-level output voltage VID = 1 V, IOL = 4 mA 150 400 mV

IOL Low-level output current VID = 1 V, VOL = 1.5 V 6 16 mA

IDD Supply current (two comparators) VID = 1 V, No load 150 300 A

All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement

Information.

NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-k resistor

between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.

PARAMETER MEASUREMENT INFORMATION

The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to forcethe device output to a level within this linear region. Since the servo-loop method of testing cannot be used, thefollowing alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., areoffered.

To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shownin Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. Withthe input polarity reversed, the output should be low.

A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages canbe slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greateraccuracy.

5 V

5.1 k

VO

Applied VIOLimit

VO

5.1 k

1 V

4 V

+

+

(a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V

Applied VIOLimit

Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits


6/22





A close approximation of the input offset voltage can be obtained by using a binary search method to vary thedifferential input voltage while monitoring the output state. When the applied input voltage differential is equal, butopposite in polarity, to the input offset voltage, the output changes states.

Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the

comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates atriangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residualdc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting inputis driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loopreaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, whichcan only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input

exactly equals the input offset voltage.

Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurementeasier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it issuggested that their tolerance level be 1% or lower.

Measuring the extremely low values of input current requires isolation from all other sources of leakage current and

compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakagecan be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted fromthe measurement obtained with a device in the socket to obtain the actual input current of the device.

R6

5.1 kBuffer

U1b

1/4 TLC274C

R1

240 k

C2

1 F

R4

47 k

U1a

1/4 TLC274CN

U1c

1/4 TLC274CN

R2

10 kR3

100 k

C1

0.1 F

R10

100 , 1%

R9

10 k, 1%

R7

1 M

R81.8 k, 1%

R5

1.8 k, 1%

VDD

DUT

Integrator

VIO(X100)

C3

0.68 F

C4

0.1 F

Triangle

Generator

+

+

+

Figure 2. Circuit for Input Offset Voltage Measurement


7/22





Response time is defined as the interval between the application of an input step function and the instant when theoutput reaches 50% of its maximum value. Response time, low-to-high level output, is measured from the leadingedge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the inputpulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The

offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuitis just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change

state.

Low-to-High-

Level Output

DUT

5.1 k 1 F

0.1 F

1 k

50

CL(see Note A)

VDD

Pulse

Generator

Input Offset VoltageCompensation Adjustment

10 10 Turn

1 V

1 V

Overdrive

Input

100 mV

Overdrive

Input

tf

tPHL

10%

50%

90%90%

50%

tr

tPLH

High-to-Low-

Level Output

TEST CIRCUIT

VOLTAGE WAVEFORMS

10%

100 mV

NOTE A: CL includes probe and jig capacitance.

Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms


8/22




PRINCIPLES OF OPERATION

LinCMOS process

The LinCMOS process is a Linear polysilicon-gate complementary-MOS process. Primarily designed forsingle-supply applications, LinCMOS products facilitate the design of a wide range of high-performance

analog functions, from operational amplifiers to complex mixed-mode converters.

While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.This short guide is intended to answer the most frequently asked questions related to the quality and reliabilityof LinCMOS products. Further questions should be directed to the nearest Texas Instruments field sales office.

electrostatic discharge

CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is onlyfor very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage toCMOS devices. It can occur when a device is handled without proper consideration for environmentalelectrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operationalamplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision

for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail.To prevent voltage buildup, each pin is protected by internal circuitry.

Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or moretransistors break down at voltages higher than the normal operating voltages but lower than the breakdownvoltage of the input gate. This type of protection scheme is limited by leakage currents which flow through theshunting transistors during normal operation after an ESD voltage has occurred. Although these currents aresmall, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as

tens of picoamps.

To overcome this limitation, Texas Instruments design engineers developed the patented ESD-protection circuitshown in Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminatingleakage currents that may be drawn through the input pins. A more detailed discussion of the operation of TexasInstrumentss ESD- protection circuit is presented on the next page.

All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protectioncircuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor througha 1500- resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor(charged device model). These tests simulate both operator and machine handling of devices during normaltest and assembly operations.

D3

R2

Q2

To Protected Circuit

VDD

D2D1

Q1

R1Input

VSS

Figure 4. LinCMOS ESD-Protection Schematic

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.


9/22





input protection circuit operation

Texas Instruments patented protection circuitry allows for both positive-and negative-going ESD transients.These transients are characterized by extremely fast rise times and usually low energies, and can occur both

when the device has all pins open and when it is installed in a circuit.

positive ESD transients

Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input risesabove the voltage on the VDD pin by a value equal to the VEB of Q1. The base current increases through R2with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2

to exceed its threshold level (VT ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to V SSis now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pincontinues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy isdissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below thegate oxide voltage of the circuit to be protected.

negative ESD transients

The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is 0.3 V to 1 V (the forwardvoltage of D1 and D2).

circuit-design considerations

LinCMOS products are being used in actual circuit environments that have input voltages that exceed therecommended common-mode input voltage range and activate the input protection circuit. Even under normaloperation, these conditions occur during circuit power up or power down, and in many cases, when the deviceis being used for a signal conditioning function. The input voltages can exceed VICR and not damage the deviceonly if the inputs are current limited. The recommended current limit shown on most product data sheets is

5 mA. Figure 5 and Figure 6 show typical characteristics for input voltage versus input current.Normal operation and correct output state can be expected even when the input voltage exceeds the positivesupply voltage. Again, the input current should be externally limited even though internal positive current limitingis achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the currentto approximately 5-mA collector current by design. When saturated, Q1 base current increases with inputcurrent. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2

producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the inputvoltage is below the VT of Q2.

When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltagestates may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can beseverely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and

no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is

required (see Figure 7).


10/22





circuit-design considerations (continued)

Figure 5

VDD

0

InputCurrent(mA)

Input Voltage (V)

8

1

2

3

4

5

6

7

VDD + 4 VDD + 8 VDD + 12

TA = 25C

INPUT CURRENT

vs

POSITIVE INPUT VOLTAGE

Figure 6

TA = 25C

0.90.70.5

Input Voltage (V)

00.3

1

2

3

4

5

6

7

8

9

10

INPUT CURRENT

vsNEGATIVE INPUT VOLTAGE

InputCurrent(mA)

+

Vref

TLC372

RL

VDD

RI

See Note A

VI

Positive Voltage Input Current Limit:

Negative Voltage Input Current Limit:

RI =

+VI VDD 0.3 V

5 mA

RI =| VI | 0.3 V

5 mA

NOTE A: If the correct output state is required when the negative input is less than GND, a schottky clamp is required.

Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator


11/22

PACKAGING INFORMATION

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

5962-87658012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type

5962-8765801PA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type

5962-9554901NXD ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

5962-9554901NXDR ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


TLC372CD ACTIVE SOIC D 8 75 Green (RoHS &no Sb/Br)


TLC372CDG4 ACTIVE SOIC D 8 75 Green (RoHS &no Sb/Br)


TLC372CDR ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


TLC372CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


TLC372CP ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type

TLC372CPE4 ACTIVE PDIP P 8 50 Pb-Free(RoHS)


TLC372CPSR ACTIVE SO PS 8 2000 Green (RoHS &no Sb/Br)


TLC372CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS &no Sb/Br)


TLC372CPW ACTIVE TSSOP PW 8 150 Green (RoHS &no Sb/Br)


TLC372CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &no Sb/Br)


TLC372CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI

TLC372CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS &

no Sb/Br)


TLC372CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &no Sb/Br)


TLC372ID ACTIVE SOIC D 8 75 Green (RoHS &no Sb/Br)


TLC372IDG4 ACTIVE SOIC D 8 75 Green (RoHS &no Sb/Br)


TLC372IDR ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


TLC372IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


TLC372IP ACTIVE PDIP P 8 50 Pb-Free(RoHS)


TLC372IPE4 ACTIVE PDIP P 8 50 Pb-Free(RoHS) CU NIPDAU N / A for Pkg Type

TLC372MD ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM

TLC372MDG4 ACTIVE SOIC D 8 75 Green (RoHS &no Sb/Br)


TLC372MDR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-3-245C-168 HR

TLC372MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 1


12/22

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TLC372MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type

TLC372MJG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type

TLC372MJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg TypeTLC372MP ACTIVE PDIP P 8 50 Pb-Free

(RoHS)CU NIPDAU N / A for Pkg Type

TLC372MUB ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type

TLC372QD ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM

TLC372QDG4 ACTIVE SOIC D 8 75 Green (RoHS &no Sb/Br)


TLC372QDR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-1-220C-UNLIM

TLC372QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC372, TLC372M :

Enhanced Product: TLC372-EP

NOTE: Qualified Version Definitions:

Enhanced Product - Supports Defense, Aerospace and Medical Applications

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 2
http://www.ti.com/productcontenthttp://focus.ti.com/docs/prod/folders/print/tlc372-ep.htmlhttp://focus.ti.com/docs/prod/folders/print/tlc372-ep.htmlhttp://www.ti.com/productcontent


13/22

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1(mm)

W(mm) Q

5962-9554901NXDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0

TLC372CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0

TLC372CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0

TLC372CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0

TLC372IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0

PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2008

Pack Materials-Page 1


14/22

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

5962-9554901NXDR SOIC D 8 2500 346.0 346.0 29.0

TLC372CDR SOIC D 8 2500 340.5 338.1 20.6

TLC372CPSR SO PS 8 2000 346.0 346.0 33.0

TLC372CPWR TSSOP PW 8 2000 346.0 346.0 29.0

TLC372IDR SOIC D 8 2500 340.5 338.1 20.6

PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2008

Pack Materials-Page 2


15/22

MECHANICAL DATA

MTSS001C JANUARY 1995 REVISED FEBRUARY 1999

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10

0,10

0,25

0,50

0,75

0,15 NOM

Gage Plane

28

9,80

9,60

24

7,90

7,70

2016

6,60

6,40

4040064/F 01/97

0,30

6,60

6,20

8

0,19

4,30

4,50

7

0,15

14

A

1

1,20 MAX

14

5,10

4,90

8

3,10

2,90

A MAX

A MIN

DIM

PINS **

0,05

4,90

5,10

Seating Plane

08

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153


16/22

MECHANICAL DATA

MLCC006B OCTOBER 1996


FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

4040140/ D 10/96

28 TERMINAL SHOWN

B

0.358

(9,09)

MAX

(11,63)

0.560

(14,22)

0.560

0.458

0.858

(21,8)

1.063

(27,0)

(14,22)

ANO. OF

MINMAX

0.358

0.660

0.761

0.458

0.342

(8,69)

MIN

(11,23)

(16,26)

0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)

0.938

(28,99)

1.141

(24,43)

(29,59)

(19,32)(18,78)

**

20

28

52

44

68

84

0.020 (0,51)

TERMINALS

0.080 (2,03)

0.064 (1,63)

(7,80)

0.307

(10,31)

0.406

(12,58)

0.495

(12,58)

0.495

(21,6)

0.850

(26,6)

1.047

0.045 (1,14)

0.045 (1,14)

0.035 (0,89)

0.035 (0,89)

0.010 (0,25)

121314151618 17

11

10

8

9

7

5

432

0.020 (0,51)

0.010 (0,25)

6

12826 27

19

21

B SQ

A SQ

22

23

24

25

20

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004


17/22


18/22


19/22

MECHANICAL DATA

MCER001A JANUARY 1995 REVISED JANUARY 1997


JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.310 (7,87)

0.290 (7,37)

0.014 (0,36)

0.008 (0,20)

Seating Plane

4040107/C 08/96

5

4

0.065 (1,65)

0.045 (1,14)

8

1

0.020 (0,51) MIN

0.400 (10,16)

0.355 (9,00)

0.015 (0,38)

0.023 (0,58)

0.063 (1,60)

0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)

0.280 (7,11)

0.100 (2,54)

015

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8


20/22

MECHANICAL DATA

MPDI001A JANUARY 1995 REVISED JUNE 1999


P (R-PDIP-T8) PLASTIC DUAL-IN-LINE

8

4

0.015 (0,38)

Gage Plane

0.325 (8,26)

0.300 (7,62)

0.010 (0,25) NOM

MAX

0.430 (10,92)

4040082/D 05/98

0.200 (5,08) MAX

0.125 (3,18) MIN

5

0.355 (9,02)

0.020 (0,51) MIN

0.070 (1,78) MAX

0.240 (6,10)

0.260 (6,60)

0.400 (10,60)

1

0.015 (0,38)

0.021 (0,53)

Seating Plane

M0.010 (0,25)

0.100 (2,54)

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm


21/22


22/22

I M P O R T A N T N O T I C E

T e x a s I n s t r u m e n t s I n c o r p o r a t e d a n d i t s s u b s i d i a r i e s ( T I ) r e s e r v e t h e r i g h t t o m a k e c o r r e c t i o n s , m o d i f i c a t i o n s , e n h a n c e m e n t s , i m p r o v e m e n t s , a n d o t h e r c h a n g e s t o i t s p r o d u c t s a n d s e r v i c e s a t a n y t i m e a n d t o d i s c o n t i n u e a n y p r o d u c t o r s e r v i c e w i t h o u t n o t i c e . C u s t o m e r s s h o u l do b t a i n t h e l a t e s t r e l e v a n t i n f o r m a t i o n b e f o r e p l a c i n g o r d e r s a n d s h o u l d v e r i f y t h a t s u c h i n f o r m a t i o n i s c u r r e n t a n d c o m p l e t e . A l l p r o d u c t s a r e s o l d s u b j e c t t o T I s t e r m s a n d c o n d i t i o n s o f s a l e s u p p l i e d a t t h e t i m e o f o r d e r a c k n o w l e d g m e n t .

T I w a r r a n t s p e r f o r m a n c e o f i t s h a r d w a r e p r o d u c t s t o t h e s p e c i f i c a t i o n s a p p l i c a b l e a t t h e t i m e o f s a l e i n a c c o r d a n c e w i t h T I s s t a n d a r d

w a r r a n t y . T e s t i n g a n d o t h e r q u a l i t y c o n t r o l t e c h n i q u e s a r e u s e d t o t h e e x t e n t T I d e e m s n e c e s s a r y t o s u p p o r t t h i s w a r r a n t y . E x c e p t w h e r e m a n d a t e d b y g o v e r n m e n t r e q u i r e m e n t s , t e s t i n g o f a l l p a r a m e t e r s o f e a c h p r o d u c t i s n o t n e c e s s a r i l y p e r f o r m e d .

T I a s s u m e s n o l i a b i l i t y f o r a p p l i c a t i o n s a s s i s t a n c e o r c u s t o m e r p r o d u c t d e s i g n . C u s t o m e r s a r e r e s p o n s i b l e f o r t h e i r p r o d u c t s a n d a p p l i c a t i o n s u s i n g T I c o m p o n e n t s . T o m i n i m i z e t h e r i s k s a s s o c i a t e d w i t h c u s t o m e r p r o d u c t s a n d a p p l i c a t i o n s , c u s t o m e r s s h o u l d p r o v i d e a d e q u a t e d e s i g n a n d o p e r a t i n g s a f e g u a r d s .

T I d o e s n o t w a r r a n t o r r e p r e s e n t t h a t a n y l i c e n s e , e i t h e r e x p r e s s o r i m p l i e d , i s g r a n t e d u n d e r a n y T I p a t e n t r i g h t , c o p y r i g h t , m a s k w o r k r i g h t , o r o t h e r T I i n t e l l e c t u a l p r o p e r t y r i g h t r e l a t i n g t o a n y c o m b i n a t i o n , m a c h i n e , o r p r o c e s s i n w h i c h T I p r o d u c t s o r s e r v i c e s a r e u s e d . I n f o r m a t i o np u b l i s h e d b y T I r e g a r d i n g t h i r d - p a r t y p r o d u c t s o r s e r v i c e s d o e s n o t c o n s t i t u t e a l i c e n s e f r o m T I t o u s e s u c h p r o d u c t s o r s e r v i c e s o r a w a r r a n t y o r e n d o r s e m e n t t h e r e o f . U s e o f s u c h i n f o r m a t i o n m a y r e q u i r e a l i c e n s e f r o m a t h i r d p a r t y u n d e r t h e p a t e n t s o r o t h e r i n t e l l e c t u a l p r o p e r t y o f t h e t h i r d p a r t y , o r a l i c e n s e f r o m T I u n d e r t h e p a t e n t s o r o t h e r i n t e l l e c t u a l p r o p e r t y o f T I .

R e p r o d u c t i o n o f T I i n f o r m a t i o n i n T I d a t a b o o k s o r d a t a s h e e t s i s p e r m i s s i b l e o n l y i f r e p r o d u c t i o n i s w i t h o u t a l t e r a t i o n a n d i s a c c o m p a n i e d b y a l l a s s o c i a t e d w a r r a n t i e s , c o n d i t i o n s , l i m i t a t i o n s , a n d n o t i c e s . R e p r o d u c t i o n o f t h i s i n f o r m a t i o n w i t h a l t e r a t i o n i s a n u n f a i r a n d d e c e p t i v e b u s i n e s s p r a c t i c e . T I i s n o t r e s p o n s i b l e o r l i a b l e f o r s u c h a l t e r e d d o c u m e n t a t i o n . I n f o r m a t i o n o f t h i r d p a r t i e s m a y b e s u b j e c t t o a d d i t i o n a l r e s t r i c t i o n s .

R e s a l e o f T I p r o d u c t s o r s e r v i c e s w i t h s t a t e m e n t s d i f f e r e n t f r o m o r b e y o n d t h e p a r a m e t e r s s t a t e d b y T I f o r t h a t p r o d u c t o r s e r v i c e v o i d s a l l

e x p r e s s a n d a n y i m p l i e d w a r r a n t i e s f o r t h e a s s o c i a t e d T I p r o d u c t o r s e r v i c e a n d i s a n u n f a i r a n d d e c e p t i v e b u s i n e s s p r a c t i c e . T I i s n o t r e s p o n s i b l e o r l i a b l e f o r a n y s u c h s t a t e m e n t s .

T I p r o d u c t s a r e n o t a u t h o r i z e d f o r u s e i n s a f e t y - c r i t i c a l a p p l i c a t i o n s ( s u c h a s l i f e s u p p o r t ) w h e r e a f a i l u r e o f t h e T I p r o d u c t w o u l d r e a s o n a b l y b e e x p e c t e d t o c a u s e s e v e r e p e r s o n a l i n j u r y o r d e a t h , u n l e s s o f f i c e r s o f t h e p a r t i e s h a v e e x e c u t e d a n a g r e e m e n t s p e c i f i c a l l y g o v e r n i n g s u c h u s e . B u y e r s r e p r e s e n t t h a t t h e y h a v e a l l n e c e s s a r y e x p e r t i s e i n t h e s a f e t y a n d r e g u l a t o r y r a m i f i c a t i o n s o f t h e i r a p p l i c a t i o n s , a n d a c k n o w l e d g e a n d a g r e e t h a t t h e y a r e s o l e l y r e s p o n s i b l e f o r a l l l e g a l , r e g u l a t o r y a n d s a f e t y - r e l a t e d r e q u i r e m e n t s c o n c e r n i n g t h e i r p r o d u c t s a n d a n y u s e o f T I p r o d u c t s i n s u c h s a f e t y - c r i t i c a l a p p l i c a t i o n s , n o t w i t h s t a n d i n g a n y a p p l i c a t i o n s - r e l a t e d i n f o r m a t i o n o r s u p p o r t t h a t m a y b e p r o v i d e d b y T I . F u r t h e r , B u y e r s m u s t f u l l y i n d e m n i f y T I a n d i t s r e p r e s e n t a t i v e s a g a i n s t a n y d a m a g e s a r i s i n g o u t o f t h e u s e o f T I p r o d u c t s i n s u c h s a f e t y - c r i t i c a l a p p l i c a t i o n s .

T I p r o d u c t s a r e n e i t h e r d e s i g n e d n o r i n t e n d e d f o r u s e i n m i l i t a r y / a e r o s p a c e a p p l i c a t i o n s o r e n v i r o n m e n t s u n l e s s t h e T I p r o d u c t s a r e s p e c i f i c a l l y d e s i g n a t e d b y T I a s m i l i t a r y - g r a d e o r " e n h a n c e d p l a s t i c . " O n l y p r o d u c t s d e s i g n a t e d b y T I a s m i l i t a r y - g r a d e m e e t m i l i t a r y s p e c i f i c a t i o n s . B u y e r s a c k n o w l e d g e a n d a g r e e t h a t a n y s u c h u s e o f T I p r o d u c t s w h i c h T I h a s n o t d e s i g n a t e d a s m i l i t a r y - g r a d e i s s o l e l y a t t h e B u y e r ' s r i s k , a n d t h a t t h e y a r e s o l e l y r e s p o n s i b l e f o r c o m p l i a n c e w i t h a l l l e g a l a n d r e g u l a t o r y r e q u i r e m e n t s i n c o n n e c t i o n w i t h s u c h u s e .

T I p r o d u c t s a r e n e i t h e r d e s i g n e d n o r i n t e n d e d f o r u s e i n a u t o m o t i v e a p p l i c a t i o n s o r e n v i r o n m e n t s u n l e s s t h e s p e c i f i c T I p r o d u c t s a r e d e s i g n a t e d b y T I a s c o m p l i a n t w i t h I S O / T S 1 6 9 4 9 r e q u i r e m e n t s . B u y e r s a c k n o w l e d g e a n d a g r e e t h a t , i f t h e y u s e a n y n o n - d e s i g n a t e d p r o d u c t s i n a u t o m o t i v e a p p l i c a t i o n s , T I w i l l n o t b e r e s p o n s i b l e f o r a n y f a i l u r e t o m e e t s u c h r e q u i r e m e n t s .

F o l l o w i n g a r e U R L s w h e r e y o u c a n o b t a i n i n f o r m a t i o n o n o t h e r T e x a s I n s t r u m e n t s p r o d u c t s a n d a p p l i c a t i o n s o l u t i o n s :

P r o d u c t s A p p l i c a t i o n s A m p l i f i e r s a m p l i f i e r . t i . c o m A u d i o w w w . t i . c o m / a u d i o D a t a C o n v e r t e r s d a t a c o n v e r t e r . t i . c o m A u t o m o t i v e w w w . t i . c o m / a u t o m o t i v e D L P P r o d u c t s w w w . d l p . c o m B r o a d b a n d w w w . t i . c o m / b r o a d b a n d D S P d s p . t i . c o m D i g i t a l C o n t r o l w w w . t i . c o m / d i g i t a l c o n t r o l C l o c k s a n d T i m e r s w w w . t i . c o m / c l o c k s M e d i c a l w w w . t i . c o m / m e d i c a l I n t e r f a c e i n t e r f a c e . t i . c o m M i l i t a r y w w w . t i . c o m / m i l i t a r y L o g i c l o g i c . t i . c o m O p t i c a l N e t w o r k i n g w w w . t i . c o m / o p t i c a l n e t w o r k P o w e r M g m t p o w e r . t i . c o m S e c u r i t y w w w . t i . c o m / s e c u r i t y M i c r o c o n t r o l l e r s m i c r o c o n t r o l l e r . t i . c o m T e l e p h o n y w w w . t i . c o m / t e l e p h o n y R F I D w w w . t i - r f i d . c o m V i d e o & I m a g i n g w w w . t i . c o m / v i d e o R F / I F a n d Z i g B e e S o l u t i o n s w w w . t i . c o m / l p r f W i r e l e s s w w w . t i . c o m / w i r e l e s s

M a i l i n g A d d r e s s : T e x a s I n s t r u m e n t s , P o s t O f f i c e B o x 6 5 5 3 0 3 , D a l l a s , T e x a s 7 5 2 6 5 C o p y r i g h t 2 0 0 9 , T e x a s I n s t r u m e n t s I n c o r p o r a t e d
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tlc372 lincmos dual differential comparators

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