tlv705 200-ma, low iq, low-noise, low-dropout regulator in … · 2020. 12. 14. · tlv705 200-ma,...

TLV705

GND

EN

VIN VOUTInput Output

On

Off

CIN COUT

1 mFCeramic

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV705, TLV705PSBVS151F –DECEMBER 2010–REVISED APRIL 2017

TLV705 200-mA, Low IQ, Low-Noise, Low-Dropout Regulator in Ultra-Small,0.77-mm × 0.77-mm DSBGA and PicoStar™

1

1 Features1• Very Low Dropout:

– 105 mV at IOUT = 150 mA– 145 mV at IOUT = 200 mA

• Accuracy: 0.5% Typical• Low IQ: 35 μA• Available in Fixed-Output Voltages From

0.7 V to 4.8 V• VIN Range: 2 V to 5.5 V• High PSRR: 70 dB at 1 kHz• Stable With Effective Capacitance of 0.1 μF• Thermal Shutdown and Overcurrent Protection• Available in an Ultra-Low Profile (0.15-mm

Maximum Height) PicoStar Package Option

2 Applications• Wireless Handsets• Smart Phones• Zigbee® Networks• Bluetooth® Devices• Other Li-Ion Operated Handheld Products• WLAN and Other PC Add-On Cards

3 DescriptionThe TLV705 series of low-dropout (LDO) linearregulators are low quiescent current devices withexcellent line and load transient performance. Thesedevices are designed for power-sensitiveapplications, with a precision band gap. An erroramplifier provides typical accuracy of 0.5%. Lowoutput noise, very high power-supply rejection ratio(PSRR), and low dropout voltage make this series ofLDOs ideal for a wide selection of battery-operatedhandheld equipment. All devices have a thermalshutdown and current limit for safety.

Furthermore, the TLV705 series is stable with aneffective output capacitance of only 0.1 μF. Thisfeature enables the use of cost-effective capacitorsthat have higher bias voltage and temperaturederating. The devices regulate to the specifiedaccuracy with zero output load. The TLV705P seriesalso provides an active pulldown circuit to quicklydischarge output.

The TLV705 and TLV705P series are both availablein 0.77-mm × 0.77-mm DSBGA and PicoStarpackages with three height options that are optimalfor handheld applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TLV705DSGBA (4) 0.77 mm × 0.77 mmPicoStar (4) 0.77 mm × 0.77 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Typical Application Circuit (Fixed-Voltage Versions)

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2

TLV705, TLV705PSBVS151F –DECEMBER 2010–REVISED APRIL 2017 www.ti.com

Product Folder Links: TLV705 TLV705P

Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated

Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 46 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 56.2 ESD Ratings ............................................................ 56.3 Recommended Operating Conditions....................... 56.4 Thermal Information .................................................. 56.5 Electrical Characteristics........................................... 66.6 Typical Characteristics .............................................. 7

7 Detailed Description ............................................ 127.1 Overview ................................................................. 127.2 Functional Block Diagrams ..................................... 127.3 Feature Description................................................. 137.4 Device Functional Modes........................................ 14

8 Application and Implementation ........................ 158.1 Application Information............................................ 15

8.2 Typical Application .................................................. 158.3 Do's and Don'ts....................................................... 16

9 Power Supply Recommendations ...................... 1610 Layout................................................................... 17

10.1 Layout Guidelines ................................................. 1710.2 Layout Example .................................................... 1710.3 Power Dissipation ................................................. 1710.4 Power Dissipation and Junction Temperature ...... 1710.5 Estimating Junction Temperature ......................... 18

11 Device and Documentation Support ................. 1911.1 Device Support .................................................... 1911.2 Documentation Support ....................................... 1911.3 Related Links ........................................................ 1911.4 Community Resources.......................................... 2011.5 Trademarks ........................................................... 2011.6 Electrostatic Discharge Caution............................ 2011.7 Glossary ................................................................ 20

12 Mechanical, Packaging, and OrderableInformation ........................................................... 2012.1 Package Mounting ................................................ 20

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (May 2015) to Revision F Page

• Deleted "x" from TLV705 device in document title ................................................................................................................ 1• Changed package dimensions in document title from "0.8-mm × 0.8-mm" to "0.77-mm × 0.77-mm" .................................. 1• Changed ultra-low profile maximum height from 0.2-mm to 0.15-mm in Applications section ............................................. 1• Changed package dimensions in Description section from 0.8-mm to 0.77-mm. .................................................................. 1• Changed DSBGA package dimensions from "0.80 mm × 0.80 mm" to "0.77 mm × 0.77 mm" in the Device

Information table .................................................................................................................................................................... 1• Added copyright statement to the Typical Application Circuit ............................................................................................... 1• Changed formatting of Thermal Information table note ......................................................................................................... 5• Deleted "x" from device number in Thermal Information table .............................................................................................. 5• Added copyright statement to functional block diagrams in Functional Block Diagrams section ........................................ 12• Added copyright statement to Typical Application Circuit (Fixed-Voltage Versions) in the Typical Application section ..... 15• Changed formatting of document reference in Related Documentation section ................................................................. 19• Changed table header title from "Sample & Buy" to "Order Now" in the Related Links table ............................................ 19

Changes from Revision D (April 2015) to Revision E Page

• Added new package (YFM) to document .............................................................................................................................. 1• Added PicoStar to title ........................................................................................................................................................... 1• Changed last Features bullet ................................................................................................................................................. 1• Changed last sentence of Description section ...................................................................................................................... 1• Added second row to Device Information table ..................................................................................................................... 1• Added YFM pin out drawing ................................................................................................................................................... 4• Added YFM package to Thermal Information table ............................................................................................................... 5• Changed VO parameter units in Electrical Characteristics table: % for first row, mV for second row.................................... 6



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3

TLV705, TLV705Pwww.ti.com SBVS151F –DECEMBER 2010–REVISED APRIL 2017


Submit Documentation FeedbackCopyright © 2010–2017, Texas Instruments Incorporated

• Changed first sentence of Overview section: removed new ............................................................................................... 12• Changed fifth sentence of Internal Current Limit section to clarify description of the shutdown circuit functionality .......... 13• Changed Vµs to V/µs in second paragraph of Start-Up Current section ............................................................................ 13• Changed it to the start-up current in third paragraph of Start-Up Current section .............................................................. 13• Changed INPUT to VIN in Power Supply Recommendations section .................................................................................. 16• Added Related Links section ............................................................................................................................................... 19• Added YFM package to Package Mounting section ........................................................................................................... 20

Changes from Revision C (October 2012) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementationsection, Power Supply Recommendations section, Layout section, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section ................................................................................................. 1

• Added Features bullet for VIN range ...................................................................................................................................... 1• Changed Applications list items ............................................................................................................................................. 1• Deleted Power Dissipation Ratings table .............................................................................................................................. 5• Changed y-axis unit measurement from ILIM to ICL for Figure 11............................................................................................ 7• Changed Figure 31 and deleted layout silkscreen images; replaced with image of PCB layout drawing. .......................... 17• Changed title for Figure 31 .................................................................................................................................................. 17• Changed title of Thermal Protection section ....................................................................................................................... 17

Changes from Revision B (December 2011) to Revision C Page

• Deleted last Features bullet.................................................................................................................................................... 1

Changes from Revision A (August 2011) to Revision B Page

• Added last Features bullet...................................................................................................................................................... 1• Changed last sentence of Description section ....................................................................................................................... 1• Added Mechanical Packages section (removed June 2013; packages are now automatically appended)........................... 1• Added YFP to title of pin out drawing..................................................................................................................................... 4• Added YFP package to Thermal Information table ................................................................................................................ 5



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EN

GND

VIN

VOUT

2

1

A B

EN

GND

VIN

VOUT

2

1

A B

4




5 Pin Configuration and Functions

YFF, YFP Packages4-Pin DSBGA

Top View

YFM Package4-Pin PicoStar

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

GND A1 — Ground pin.

EN A2 IEnable pin.Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V places the regulator intoshutdown mode, which reduces the operating current to 1 μA (nominal).

VOUT B1 ORegulated output voltage pin.Placing a small 1-μF ceramic capacitor is required from this pin to ground to ensure stability.See Input and Output Capacitor Requirements for more details.

VIN B2 IInput pin.TI recommends placing a small 1-µF capacitor from this pin to ground for good transient performance.See Input and Output Capacitor Requirements for more details.



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5




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) All voltages are with respect to network ground pin.

6 Specifications

6.1 Absolute Maximum Ratingsspecified at TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND. (1)

MIN MAX UNIT

Voltage (2)

VIN –0.3 6 VVEN –0.3 6 VVOUT –0.3 6 V

Maximum output current IOUT Internally limitedOutput short-circuit duration Indefinite

TemperatureOperating junction, TJ –55 150 °CStorage, Tstg –55 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000

VCharged device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

6.3 Recommended Operating Conditionsover operating junction temperature range (unless otherwise noted)

MIN NOM MAX UNITVIN Input voltage 2 5.5 VVOUT Output voltage 0.7 4.8 VIOUT Output current 0 200 mATJ Junction temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

6.4 Thermal Information

THERMAL METRIC (1)

TLV705

UNITYFF, YFP(DSBGA)

YFM(PicoStar)

4 PINS 4 PINSRθJA Junction-to-ambient thermal resistance 160 191.7 °C/WRθJC(top) Junction-to-case (top) thermal resistance 80 3.1 °C/WRθJB Junction-to-board thermal resistance 90 36.5 °C/WψJT Junction-to-top characterization parameter 0.5 2.8 °C/WψJB Junction-to-board characterization parameter 78 26.5 °C/W



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6




(1) VDO is measured for devices with VOUT(nom) = 2.35 V so that VIN = 2.3 V.(2) Start-up time = time from EN assertion to 0.98 × VOUT(nom).

6.5 Electrical Characteristicsat TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = 0.9 V, andCOUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVIN Input voltage range 2 5.5 VVOUT Output voltage range 0.7 4.8 V

VO DC output accuracy –40°C ≤ TJ ≤ 125°C0 mA ≤ IOUT ≤ 200 mA, VOUT ≥ 1 V –2% ±0.5% 2%0 mA ≤ IOUT ≤ 200 mA, VOUT < 1 V –20 ±5 20 mV

ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V 0.05 5 mVΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 200 mA 1 mVVDO Dropout voltage (1) VIN = 0.98 × VOUT(nom), IOUT = 200 mA 145 250 mVICL Output current limit VOUT = 0.9 × VOUT(nom), TJ = 25°C 260 400 550 mA

IGND Ground pin currentIOUT = 0 mA 35 55 μAIOUT = 200 mA 315 μA

ISHUTDOWNShutdown ground pincurrent VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V 1 1.8 μA

PSRR Power-supplyrejection ratio

VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA,f = 10 kHz 80 dB

VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA,f = 1 MHz 55 dB

Vn Output noise voltage

BW = 100 Hz to100 kHz, IOUT = 10 mA

VIN = 2.3 V, VOUT = 1.8 V 26.6 μVRMS

VIN = 3.3 V, VOUT = 2.8 V 26.7 μVRMS

VIN = 3.8 V, VOUT = 3.3 V 28.2 μVRMS

BW = 10 Hz to 100 kHz,IOUT = 10 mA

VIN = 2.3 V, VOUT = 1.8 V 30.7 μVRMS

VIN = 3.3 V, VOUT = 2.8 V 31.3 μVRMS

VIN = 3.8 V, VOUT = 3.3 V 34.1 μVRMS

tSTR Start-up time (2) COUT = 1 μF, IOUT = 200 mA 100 μsVHI Enable high (enabled) 0.9 VIN VVLO Enable low (disabled) 0 0.4 VIEN EN pin current VEN = 5.5 V 0.01 μAUVLO Undervoltage lockout VIN rising 1.9 V

tSDThermal shutdowntemperature

Shutdown, temperature increasing 160 °CReset, temperature decreasing 140 °C

TJOperating junctiontemperature –40 125 °C



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140

120

100

80

60

40

20

0

VD

O(m

V)

0

I (mA)OUT

200

+125 C°

+85 C°

+25 C°

-40 C°

V = 4.8 VOUT

50 100 150

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

V(V

)O

UT

-40 -25 -10 5 20 35 50 65 80 95 110

Temperature ( C)°

125

10mA

150mA

200mA

V = 1.8 VOUT

0 150100 200

I (mA)OUT

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

V(V

)O

UT

50

+125 C°

+85 C°

+25 C°

-40 C°

V = 1.8 VOUT

250

200

150

100

50

0

V(m

V)

DO

2 2.5 2.75 3.75 4.25 4.75

V (V)IN

+125 C°

+85 C°

+25 C°

-40 C°

4.543.53 3.252.25

I = 200 mAOUT

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

VO

UT

(V)

2.1 2.6 3.1 3.6 4.1 4.6 5.1

V (V)IN

5.6

+125 C°

+85 C°

+25 C°

-40 C°

V = 1.8 V

I = 10 mAOUT

OUT

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

VO

UT

(V)

2.1 2.6 3.1 3.6 4.1 4.6 5.1

V (V)IN

5.6

+125 C°

+85 C°

+25 C°

-40 C°

V = 1.8 V

I = 200 mAOUT

OUT

7




6.6 Typical Characteristicsover operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(nom) +0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C.

Figure 1. Line Regulation Figure 2. Line Regulation

Figure 3. Load Regulation ( 0 mA ≤ IOUT ≤ 200 mA) Figure 4. Dropout Voltage vs Input Voltage

Figure 5. Dropout Voltage vs Output Current Figure 6. Output Voltage vs Temperature



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100

90

80

70

60

50

40

30

20

10

0

PS

RR

(dB

)

10 100 1k 10k 100k

Frequency (Hz)

10M1M

V = 2.3 V

V = 1.8 VOUT

IN

I = 10 mAOUT

I = 150 mAOUT

500

470

440

410

380

350

I(m

A)

CL

2.5 3 3.5 4 4.5

V (V)IN

5.55

V = 1.8 VOUT

+25 C°

50

45

40

35

30

25

20

15

10

5

0

I(

A)

mG

ND

-40 -25 -10 5 20 35 50 65 80 95 110

Temperature ( C)°

125

V = 1.8 V

I = 0 mAOUT

OUT

2.5

2

1.5

1

0.5

0

I SH

DN

(A

m)

2.3 2.7 3.1 3.5 3.9 4.3 4.7

V (V)IN

5.5

+125 C°

+85 C°

+25 C°

-40 C°

V = 1.8 VOUT

5.1

50

45

40

35

30

25

20

15

10

5

0

I GN

D(

Am

)

2.3 2.7 3.1 3.5 3.9 4.3 4.7

V (V)IN

5.5

+125 C°

+85 C°

+25 C°

-40 C°

V = 1.8 V

I = 0 mAOUT

OUT

5.1

400

350

300

250

200

150

100

50

0

I GN

D(m

A)

0

I (mA)OUT

200

+125 C°

+85 C°

+25 C°

-40 C°

V = 1.8 VOUT

50 100 150

8




Typical Characteristics (continued)over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(nom) +0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C.

Figure 7. Ground Pin Current vs Input Voltage Figure 8. Ground Pin Current vs Output Current

Figure 9. Ground Pin Current vs Temperature Figure 10. Shutdown Pin Current vs Input Voltage

Figure 11. Current Limit vs Input Voltage Figure 12. Power-Supply Rejection Ratio vs Frequency



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(20 mV/div)

Time (200 s/div)m

(100 mA/div)

t = t = 1 smR F

VOUT

IOUT

200 mA

1 mA

(20 mV/div)

Time (200 s/div)m

(50 mA/div)

t = t = 1 smR F

100 mA

1 mA

VOUT

IOUT

0.8 1.2 1.6 2 2.4 2.8 3.2 4.8

V (V)OUT

45

40

35

30

25

20

15

10

5

0

Inte

gra

ted

No

ise

(V

)m

RM

S

Bandwidth: 100 Hz to 100 kHz

Bandwidth: 10 Hz to 100 kHz

3.6 4 4.4

(20 mV/div)

Time (200 s/div)m

(100 mA/div)

t = t = 1 smR F

VOUT

IOUT

200 mA

0 mA

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8

Input Voltage (V)

100

90

80

70

60

50

40

30

20

10

0

PS

RR

(dB

)

V = 1.8 VOUT

1 kHz

10 kHz

100 kHz

10

1

0.1

0.01

0

Outp

ut S

pectr

al N

ois

e D

ensity (

V/

)m

ÖH

z

10 100 1 k 10 k 100 k 1 M

Frequency (Hz)

10 M

V = 1.8 VOUT

9





Figure 13. Power-Supply Rejection Ratio vs Input Voltage Figure 14. Output Spectral Noise Density vs Frequency

Figure 15. Integrated Noise vs Output Voltage Figure 16. Load Transient 0

Figure 17. Load Transient 1 Figure 18. Load Transient 3



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(2 V/div)

Time (100 s/div)m

(5 mV/div)

Slew Rate = 1 V/ sm

VIN

VOUT

5.5 V

2.3 V(2 V/div)

Time (100 s/div)m

(5 mV/div)

Slew Rate = 1 V/ sm

VIN

VOUT

5.5 V

2.3 V

C1

(1 V/div)

Time (50 s/div)m

C4

(100 mA/div)

C2

(1 V/div)

I = 0 mAOUT

C1

(1 V/div)

Time (10 s/div)m

C4

(100 mA/div)

C2

(1 V/div)

I = 200 mAOUT

(200 mV/div)

Time (100 s/div)m

(5 mV/div)

Slew Rate = 1 V/ sm

VIN

VOUT

2.9 V

2.3 V

(200 mV/div)

Time (100 s/div)m

(5 mV/div)

Slew Rate = 1 V/ sm

VIN

VOUT

2.9 V

2.3 V

10





Figure 19. Small-Step Line Transient (10 mA) Figure 20. Small-Step Line Transient (200 mA)

Figure 21. VIN Inrush Current Figure 22. VIN Inrush Current

Figure 23. Line Transient (10 mA) Figure 24. Line Transient (200 mA)



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Time (100ms/div)

(1 V/div)

VIN

VOUT

11





Figure 25. Power-Up and Power-Down



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ThermalShutdown

CurrentLimit

UVLO

Bandgap

VIN

EN

VOUT

LOGIC

GND

TLV705P Series

120 Ω


ThermalShutdown

CurrentLimit

UVLO

Bandgap

VIN

EN

VOUT

LOGIC

GND

TLV705 Series


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7 Detailed Description

7.1 OverviewThe TLV705 and TLV705P series of devices belong to a family of next-generation value low-dropout (LDO)voltage regulators. These devices consume low quiescent current and deliver excellent line and load transientperformance. This performance, combined with low noise, very good PSRR with little (VIN – VOUT) headroom,makes these devices ideal for RF portable applications. This family of regulators offers sub-band-gap outputvoltages down to 0.7 V, current limit, and thermal protection, and are specified from –40°C to +125°C. TheTLV705P provides an active pulldown circuit to quickly discharge the outputs.

7.2 Functional Block Diagrams

Figure 26. TLV705 Series

Figure 27. TLV705P Series



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7.3 Feature Description

7.3.1 Internal Current LimitThe internal current limits of the TLV705 series help protect the regulator during fault conditions. During currentlimit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case,the output voltage is not regulated, and can be measured as VOUT = ILIMIT × RLOAD. The PMOS pass transistordissipates [(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. When the devicecools down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, thedevice cycles between current limit and thermal shutdown; see Power Dissipation and Junction Temperature formore details.

The PMOS pass element in the TLV705 has a built-in body diode that conducts current when the voltage at VOUTexceeds the voltage at VIN. This current is not limited, so if extended reverse voltage operation is anticipated, TIrecommends external limiting to 5% of the rated output current.

7.3.2 Undervoltage Lockout (UVLO)The TLV705 uses an UVLO circuit to keep the output shut off until the internal circuitry is operating properly.

7.3.3 Start-Up CurrentThe TLV705 uses a unique start-up architecture that creates a constant start-up time regardless of the outputcapacitor. The start-up current is given by Equation 1. Equation 1 shows that start-up current is directlyproportional to COUT.

ISTARTUP = COUT (μF) × 0.06 (Vμs) + ILOAD (mA) (1)

The output voltage ramp rate is independent of COUT and the load current, and has a typical value of 0.06 V/μs.

The TLV705 automatically adjusts the soft-start current to supply both the load current and the current to chargeCOUT. For example, if ILOAD = 0 mA upon enabling the LDO, then ISTARTUP = 1 μF × 0.06 Vμs + 0 mA = 60 mA,which is the current that charges the output capacitor.

However, if ILOAD = 200 mA, then ISTARTUP = 1 μF × 0.06 V / μs + 200 mA = 260 mA, which is the required currentto charge the output capacitor and supply the load current.

If the output capacitor and load increase such that the start-up current exceeds the output current limit, the start-up current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF andIOUT = 200 mA, then 10 μF × 0.06 V / μs + 200 mA = 800 mA is not supplied and is instead clamped at 400 mA.

7.3.4 Dropout VoltageThe TLV705 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropoutvoltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is theRDS(on) of the PMOS pass element. VDO approximately scales with the output current because the PMOS devicefunctions as a resistor in dropout.

As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.This effect is shown in Figure 13 in the Typical Characteristics.

7.3.5 ShutdownThe enable pin (EN) is active high. The device is enabled when the EN pin goes above 0.9 V. This relativelylower value of voltage required to turn the LDO on can power the device with the GPIO of recent processors witha GPIO voltage lower than traditional microcontrollers. The device is turned off when the EN pin is held at lessthan 0.4 V. When shutdown capability is not required, EN can be connected to the VIN pin. The TLV705P versionhas internal active pulldown circuitry that discharges the output with a time constant of:

τ = (120 × RL) / (120 + RL) × COUT

where• RL = load resistance• COUT = output capacitor (2)



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14




7.4 Device Functional Modes

7.4.1 Normal OperationThe device regulates to the nominal output voltage under the following conditions:

• The input voltage is greater than the nominal output voltage added to the dropout voltage.• The output current is less than the current limit.• The input voltage is greater than the UVLO voltage.

7.4.2 Dropout OperationIf the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all otherconditions are met for normal operation, the device operates in dropout mode. In this condition, the outputvoltage is the same the input voltage minus the dropout voltage. The transient performance of the device issignificantly degraded because the pass device is in a triode state and no longer regulates the output voltage ofthe LDO. Line or load transients in dropout can result in large output voltage deviations.

Table 1 lists the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

OPERATING MODEPARAMETER

VIN IOUT

Normal mode VIN > VOUT (nom) + VDO IOUT < ICL

Dropout mode VIN < VOUT (nom) + VDO IOUT < ICL

Current limit VIN > UVLO IOUT > ICL



http://www.ti.com




TLV705

GND

EN

VIN VOUTInput Output

On

Off

CIN COUT

1 mFCeramic


15




8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe TLV705 is a LDO that offers very low dropout voltages in a tiny package. The operating junction temperatureof this device is –40°C to +125°C.

8.2 Typical Application

Figure 28. Typical Application Circuit (Fixed-Voltage Versions)

8.2.1 Design RequirementsTable 2 lists the design parameters.

Table 2. Design ParametersPARAMETER DESIGN REQUIREMENTInput voltage 2.5 V to 3.3 V

Output voltage 1.8 VOutput current 100 mA

8.2.2 Detailed Design ProcedureSelect the desired device based on the output voltage.

Provide an input supply with adequate headroom to account for dropout. The input supply must also provideadequate current to account for the GND pin current and load current.



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100

90

80

70

60

50

40

30

20

10

0

PS

RR

(dB

)

10 100 1k 10k 100k

Frequency (Hz)

10M1M

V = 2.3 V

V = 1.8 VOUT

IN

I = 10 mAOUT

I = 150 mAOUT

Time (100ms/div)

(1 V/div)

VIN

VOUT

16




8.2.2.1 Input and Output Capacitor RequirementsTI recommends using 1-μF X5R- and X7R-type ceramic capacitors because these components have minimalvariation in value and equivalent series resistance (ESR) over temperature. However, the TLV705 series isdesigned to be stable with an effective capacitance of 0.1 μF or larger at the output. As a result, the device isstable with capacitors of other dielectrics as long as the effective capacitance under the operating bias voltageand temperature is greater than 0.1 μF. This effective capacitance refers to the capacitance that the LDO detectsunder operating bias voltage and temperature conditions (that is, the capacitance after taking the bias voltageand temperature derating into consideration). In addition to allowing the use of lower cost dielectrics, the effectivecapacitance enables using smaller footprint capacitors that have higher derating in space-constrainedapplications.

Using a 0.1-μF rating capacitor at the output of the LDO does not ensure stability because the effectivecapacitance under operating conditions is less than 0.1 μF. Maximum ESR must be less than 200 mΩ.

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to1-μF low ESR capacitor across the VIN and GND pins of the regulator. This capacitor counteracts reactive inputsources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor can benecessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the powersource. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability.

8.2.2.2 Transient ResponseAs with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,but increases the duration of the transient response.

8.2.3 Application Curves

Figure 29. Power-Supply Rejection Ratio vs Frequency Figure 30. Power-Up and Power-Down

8.3 Do's and Don'tsPlace input and output capacitors as close as possible to the device.

Do not exceed the device absolute maximum ratings.

9 Power Supply RecommendationsConnect a low output impedance power supply directly to the VIN pin of the TLV705. Inductive impedancesbetween the input supply and the VIN pin can create significant voltage excursions at the VIN pin during start-upor load transient events.



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CIN COUT

GND

VIN VOUT

Represents via used for application-specific connections

EN

17




10 Layout

10.1 Layout GuidelinesPlace input and output capacitors as close to the device pins as possible. To improve ac performance (such asPSRR, output noise, and transient response), TI recommends designing the board with the input and outputcapacitors on opposite sides of the device. In addition, connect the ground connection for the output capacitordirectly to the GND pin of the device. High ESR capacitors can degrade PSRR.

10.2 Layout Example

Figure 31. Example PCB Layout

10.3 Power DissipationThe ability to remove heat from the die is different for each package type, presenting different considerations inthe printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components movesthe heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given inThermal Information. Using heavier copper increases the effectiveness in removing heat from the device. Theaddition of plated through-holes to heat-dissipating layers also improves the thermal dissipation.

See for thermal performance on the TLV705 evaluation module (EVM). The EVM is a 2-layer board with twoounces of copper per side.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product ofthe output current and the voltage drop across the output pass element, as shown in Equation 3:

PD = (VIN – VOUT) × IOUT (3)

10.4 Power Dissipation and Junction TemperatureThermal protection disables the output when the junction temperature rises to approximately 160°C, allowing thedevice to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabledagain. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protectioncircuit can cycle on and off. This cycling limits the dissipation of the regulator, which protects the regulator fromdamage as a result of overheating.

For reliable operation, limit junction temperature to 125°C (maximum). To estimate the margin of safety in acomplete design, increase the ambient temperature until the thermal protection is triggered; use worst-case loadsand signal conditions. For good reliability, trigger thermal protection at least 35°C above the maximum expectedambient condition of the particular application. This configuration produces a worst-case junction temperature of125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TLV705 is designed to protect against overload conditions. Continuouslyrunning the TLV705 into thermal shutdown degrades device reliability.



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Y

Y Y ´

JT J T JT D: T = T + PY ´

JB J B JB D: T = T + P

18




10.5 Estimating Junction TemperatureThe JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperaturesof the LDO when in-circuit on a typical PCB board application. These metrics are not strictly discussing thermalresistances; rather, these metrics offer practical and relative means of estimating junction temperatures. Thesepsi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics(ΨJT and ΨJB) are given in Thermal Information and are used in accordance with Equation 4.

where:• PD is the power dissipated, as explained in Thermal Information.• TT is the temperature at the center-top of the device package, and• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package

edge. (4)



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19




(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit thedevice product folder at www.ti.com.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Evaluation ModulesAn evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV705.The TLV70533EVM-596 evaluation module (and related user's guide) can be requested at the TI website throughthe product folders or purchased directly from the TI eStore.

11.1.1.2 Spice ModelsComputer simulation of circuit performance using SPICE is often useful when analyzing the performance ofanalog circuits and systems. A SPICE model for the TLV705 is available through the product folders under Tools& Software.

11.1.2 Device Nomenclature

Table 3. Available Options (1)

PRODUCT VOUT

TLV705xx(x)Pyyyz

xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digitsare used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 475= 4.75 V).P is optional; devices with P have an LDO regulator with an active output discharge.yyy is package designator.z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

11.2 Documentation Support

11.2.1 Related Documentation• TLV70533EVM-596 Evaluation Module User's Guide (SLVU439)

11.3 Related LinksThe table below lists quick access links. Categories include technical documents, support and communityresources, tools and software, and quick access to sample or buy.

Table 4. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICALDOCUMENTS

TOOLS &SOFTWARE

SUPPORT &COMMUNITY

TLV705 Click here Click here Click here Click here Click hereTLV705P Click here Click here Click here Click here Click here



http://www.ti.com




http://www.ti.com

https://store.ti.com/TLV70533EVM-596-Evaluation-Module-for-TLV70533-Low-IQ-Low-Noise-Low-Dropout-Regulator-P2623.aspx

http://www.ti.com/lit/pdf/SLVU439

https://store.ti.com/Search.aspx?k=TLV705&pt=-1

http://www.ti.com/lit/pdf/SLVU439

http://www.ti.com/product/TLV705?dcmp=dsproject&hqs=pf

http://www.ti.com/product/TLV705?dcmp=dsproject&hqs=sandbuy&#samplebuy

http://www.ti.com/product/TLV705?dcmp=dsproject&hqs=td&#doctype2

http://www.ti.com/product/TLV705?dcmp=dsproject&hqs=sw&#desKit

http://www.ti.com/product/TLV705?dcmp=dsproject&hqs=support&#community

http://www.ti.com/product/TLV705P?dcmp=dsproject&hqs=pf

http://www.ti.com/product/TLV705P?dcmp=dsproject&hqs=sandbuy&#samplebuy

http://www.ti.com/product/TLV705P?dcmp=dsproject&hqs=td&#doctype2

http://www.ti.com/product/TLV705P?dcmp=dsproject&hqs=sw&#desKit

http://www.ti.com/product/TLV705P?dcmp=dsproject&hqs=support&#community

20




11.4 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.5 TrademarksE2E is a trademark of Texas Instruments.PicoStar is a trademark of Texas Instruments, Inc.Bluetooth is a registered trademark of Bluetooth SIG, Inc.Zigbee is a registered trademark of ZigBee Alliance.All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.7 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

12.1 Package MountingSolder pad footprint recommendations for the TLV705 are available from the Packaging Information page on TI'swebsite through the TLV705 series product folders. The recommended land patterns for the YFF, YFP, and YFMpackages are appended to this data sheet.



http://www.ti.com




http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://e2e.ti.com

http://support.ti.com/

http://www.ti.com/lit/pdf/SLYZ022

http://www.ti.com/sc/docs/package/related.htm

http://www.ti.com/product/TLV705

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TLV705075YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 3V

TLV705075YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 3V

TLV70509YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 3W

TLV70509YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 3W

TLV70512YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BU

TLV70512YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BU

TLV70515YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BV

TLV70515YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BV

TLV705165YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 CN

TLV705165YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 CN

TLV705185YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 YS

TLV705185YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 YS

TLV70518PYFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 EV

TLV70518PYFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 EV

TLV70518YFMR ACTIVE DSLGA YFM 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

TLV70518YFMT ACTIVE DSLGA YFM 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

TLV70518YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 WT

TLV70518YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 WT

TLV70525PYFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 EK

TLV70525PYFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 EK

http://www.ti.com/product/TLV705?CMP=conv-poasamples#samplebuy












http://www.ti.com/product/TLV705P?CMP=conv-poasamples#samplebuy










Addendum-Page 2



Pins PackageQty

Eco Plan(2)


(6)

MSL Peak Temp(3)


Samples

TLV70525YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 YB

TLV70525YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 YB

TLV705285YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BW

TLV705285YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BW

TLV70528PYFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 4E

TLV70528PYFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 125 4E

TLV70528YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 WU

TLV70528YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 WU



TLV70530YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 XA

TLV70530YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 XA

TLV70533PYFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5L

TLV70533PYFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 5L

TLV70533YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 US

TLV70533YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 US



TLV70533YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 VV

TLV70533YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 VV

TLV70534YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 B4
























Addendum-Page 3



Pins PackageQty

Eco Plan(2)


(6)

MSL Peak Temp(3)


Samples

TLV70534YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 B4



TLV70536YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BX

TLV70536YFPT ACTIVE DSBGA YFP 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BX

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and








Addendum-Page 4

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TLV705075YFPR DSBGA YFP 4 3000 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1

TLV705075YFPT DSBGA YFP 4 250 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1











TLV70518PYFPR DSBGA YFP 4 3000 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1

TLV70518PYFPT DSBGA YFP 4 250 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1

TLV70518YFMR DSLGA YFM 4 3000 180.0 8.4 0.88 0.88 0.22 4.0 8.0 Q1

TLV70518YFMT DSLGA YFM 4 250 180.0 8.4 0.88 0.88 0.22 4.0 8.0 Q1



PACKAGE MATERIALS INFORMATION

www.ti.com 18-Jun-2020

Pack Materials-Page 1

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

















TLV70533YFFR DSBGA YFF 4 3000 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1

TLV70533YFFT DSBGA YFF 4 250 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1














*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV705075YFPR DSBGA YFP 4 3000 182.0 182.0 20.0

TLV705075YFPT DSBGA YFP 4 250 182.0 182.0 20.0











TLV70518PYFPR DSBGA YFP 4 3000 182.0 182.0 20.0

TLV70518PYFPT DSBGA YFP 4 250 182.0 182.0 20.0

TLV70518YFMR DSLGA YFM 4 3000 210.0 185.0 35.0

TLV70518YFMT DSLGA YFM 4 250 210.0 185.0 35.0








Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)















TLV70533YFFR DSBGA YFF 4 3000 182.0 182.0 20.0

TLV70533YFFT DSBGA YFF 4 250 182.0 182.0 20.0














www.ti.com

PACKAGE OUTLINE

C0.5 MAX

0.190.13

0.4TYP

0.4TYP

4X 0.250.21

B E A

D

4223507/A 01/2017

DSBGA - 0.5 mm max heightYFP0004DIE SIZE BALL GRID ARRAY

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.

BALL A1CORNER

SEATING PLANE

BALL TYP 0.05 C

A

B

20.015 C A B

SYMM

SYMM

1

SCALE 10.000

D: Max =

E: Max =

0.806 mm, Min =

0.806 mm, Min =

0.746 mm

0.746 mm

www.ti.com

EXAMPLE BOARD LAYOUT

4X ( 0.23)

(0.4) TYP

(0.4) TYP

( 0.23)METAL

0.05 MAX

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

( 0.23)SOLDER MASKOPENING

0.05 MIN

4223507/A 01/2017


NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

SOLDER MASK DETAILSNOT TO SCALE

SYMM

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:50X

A

B

1 2

NON-SOLDER MASKDEFINED

(PREFERRED)

EXPOSEDMETAL

SOLDER MASKDEFINED

EXPOSEDMETAL

www.ti.com

EXAMPLE STENCIL DESIGN

(0.4) TYP

(0.4) TYP

4X ( 0.25) (R0.05) TYP

METALTYP

4223507/A 01/2017


NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

SYMM

SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCIL

SCALE:50X

A

B

1 2

D: Max =

E: Max =

0.806 mm, Min =

0.806 mm, Min =

0.746 mm

0.746 mm

www.ti.com

PACKAGE OUTLINE

C

0.625 MAX

0.300.12

0.4TYP

0.4 TYP

4X 0.30.2

B E A

D

4219460/A 02/2014

DSBGA - 0.625 mm max heightYFF0004DIE SIZE BALL GRID ARRAY

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. NanoFreeTM package configuration.

NanoFree Is a trademark of Texas Instruments.

BALL A1CORNER

SEATING PLANE

BALL TYP

B

A

1 2

0.015 C A B

SYMM

SYMM

SCALE 13.000

D: Max =

E: Max =

0.806 mm, Min =

0.806 mm, Min =

0.746 mm

0.746 mm

www.ti.com

EXAMPLE BOARD LAYOUT

4X 0.23 0.02

(0.4) TYP

(0.4) TYP

( )METAL

0.23 0.05 MAX

SOLDER MASKOPENING

METALUNDERMASK

( )SOLDER MASKOPENING

0.23

0.05 MIN

4219460/A 02/2014


NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).

SOLDER MASK DETAILSNOT TO SCALE

SYMM

SYMM

LAND PATTERN EXAMPLESCALE:50X

1 2

A

B

NON-SOLDER MASKDEFINED

(PREFERRED)SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(0.4)TYP

(0.4) TYP

4X ( 0.25) (R ) TYP0.05

METALTYP

4219460/A 02/2014


NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

SYMM

SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCIL

SCALE:50X

1 2

A

B

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