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True-Time Delay Test Concepts

Product Version 7.2August 2008


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August 2008 2 Product Version 7.2

Copyright Statement

2008 Cadence Design Systems, Inc. All rights reserved worldwide.


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Contents

True Time Delay Test Concepts ........................................4Purpose ....................................................................................................................... 4

Audience...................................................................................................................... 4Delay Defects .............................................................................................................. 4

Causes of Delay Defects.......................................................................................... 4Effects of Delay Defects........................................................................................... 5Structural Delay Fault Model .................................................................................... 6Testing for a Delay Defect........................................................................................ 6Conditions for Exciting the Defect ............................................................................ 7Launch from Capture/Functional Release................................................................ 8Launch from Shift ..................................................................................................... 9

Timing Considerations............................................................................................... 10SDF Information..................................................................................................... 10

Path Tests ................................................................................................................. 25Path Fault Model.................................................................................................... 25Testing Path Groups versus Path Faults................................................................ 26Path Test Quality.................................................................................................... 27Differences from Delay Test Generation ................................................................ 29

Delay Faults on Scan-Only Paths.............................................................................. 32Detecting Scan-Only Delay Faults ......................................................................... 32

Apriori Fault Mark-Off............................................................................................. 32Summary ................................................................................................................... 33


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True Time Delay Test Concepts

Purpose

The purpose of this document is to give a thorough understanding of the concepts inmodern delay testing as they are applied in Encounter True-Time Delay Test.

Audience

This application note is intended for those who wish to learn delay test concepts andhow these concepts are applied in Encounter True-Time Delay Test.

Delay Defects

A delay defect is a physical manufacturing problem which slows down the propagationof a logical data values transition from logic 0 to logic 1, or vice versa. The presence ofa delay defect may or may not affect the functional operation of the circuit, since thecorrect logical outcome will always be reached if the circuit is given enough time tosettle. This differs greatly from static (stuck-at) defects because static defects willalways cause the wrong logical values to propagate through the circuit, regardless ofthe amount of time that the circuit is allowed to settle.

Delay defects are modeled using the transition fault model, discussed later in this document.

Causes of Delay Defects

Photo source: IBM Corp.

ZzZzZz

0-1

1-10------1


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There are many manufacturing problems which can result in the creation of delaydefects. Impurities in the materials used can cause the resistance of a material tochange, resulting in the RC time constant to increase. Etching processes that removetoo much material, or additive processes (such as addition of copper metal lines), whichadd or remove too much or not enough material, can also increase the resistance of atransmission line. Poorly filled vias are also a common cause of delay defects.Inductance and bridging problems can also cause a given transition to be slower thanthe designers intended. Inductance can be caused by large neighboring wires creating amagnetic field which slow down a given transition on the victim wire. Small highresistance bridges to ground or the positive rail voltage, or even another wire with avarying logical value, can also cause delay defects, without causing static defects.

Effects of Delay Defects

Delay defects cause a given transition to require more time to occur. More precisely,the time required to switch from the threshold voltage for a logical 0 to the thresholdvoltage for a logical 1 (or vice versa) is increased. Also, typically the time spent in theswitching zone between logic 0 and logic 1 increases. In this switching zone, the devicewill consume most of its power. For this reason, with older technologies of the past, IDDQtesting was adequate to locate problems which were actually delay defects. However,with todays technologies, the background level of power consumption and leakagecurrent is so high that performing IDDQ testing is quite difficult, and nearly impossible todiagnose even if a problem is located with this method.


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Delay defects do not always cause a functional device failure. Sometimes they cancause intermittent failures, failing only when a logical transition is excited through thedefect site and utilized down a very specific, complex path of logic. Some may notcause any functional failures, but could lead to early life failures of the product. Forexample, if a non-critical delay defect exists due to a high resistance, incorrectly formedwire, electromigration may occur as the product is used, leading to a large delay defectand eventually a static defect (as the wire continues to decompose).

Structural Delay Fault Model

A structural approach to the delay fault model is needed to detect and be able todiagnose delay defects. A delay fault (also known as a transitionordynamicfault)models a specific physical defect at a specific location. Delay faults may model thecondition where a data transition is slow to rise (transition from logical 0 to logical 1), orslow to fall (transition from logical 1 to logical 0).

Slow to Rise fault

Slow to Fall fault

Testing for a Delay Defect

To create a test for a delay defect, we must create a test pattern for the delay faultwhich models the given defect. To accomplish this, excite the conditions under whichthe defect will manifest itself and ensure that the transition resulting from theseconditions (known as the fault effect) reaches a location which can be easily measuredorobservedby the tester. Typically, these locations are scannable flops or primaryoutput pins. Primary outputs as observation points are generally not used for delay testsbecause they often require a large amount of time to switch (since they are usually large

metal pads, driving large wires with high capacitance). Flops are preferred because theycan capture a value at high speed.


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Conditions for Exciting the Defect

To excite a delay defect, we must create an appropriate transition at the defect site.This requires that circuit values are established in two separate timeframes: the initialand finalvalues of the transition itself. The period of time during which the initial value istransitioned to the final value is known as the releaseorlaunchtimeframe. The periodof time when the fault effect reaches an observable location is known as the capturetimeframe. Conditions to excite the transition can be established using scannable flopsand primary input pins. Similar to the argument against observing delay fault effects atprimary output pins, primary input pins are generally not used for the excitation of delay

defects due to their generally slow switching speeds.

Even defect-free gates can suffer from some uncertainty in their switching speeds, sodesigners will usually take into account a certain amount of guard band to account forthis. The capture clock and also functional clock speed are slowed down to account forthis guard band so that devices which can undergo the transitions in an acceptableamount of time will continue to function correctly.

Launching a transition fault can occur in one of two different ways: launch from capture(also known as functional release), and launch from shift(also known as last shiftlaunch). They both have their respective advantages and disadvantages.


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Launch from Capture/Functional Release

Launch from capture is the most commonly used technique in delay test patterngeneration. Logical values which are required to establish the initial value of the givendelay fault are loaded into scannable registers which directly feed the fault site. Logicalvalues which will result in the transition from the initial to the final value of the delay faultare back-tracked through one level of functional logic, such that when the launch clock

is pulsed, the flops which directly feed the fault site will create the transition from initialto final value at the fault site. In this way, the transition is launched from the circuitvalues which are captured by the release clock pulse (as opposed to scanned in).

The process of tracking the final value backward through functional logic expendssignificant processing resource and may not even be possible is some cases(depending on circuit topology). This method will increase ATPG runtime and potentiallyreduce the maximum possible test coverage in some cases.

The advantages become evident when examining the preceding timing diagram for thisscenario. The only values required to switch to achieve a high speed launch from

capture test are in scannable flops. These flops can launch and capture values at thefull functional speed of the device under test. There is no reliance on the timing of anyother primary input pins or potentially slow test-only logic paths. Logical paths that areonly active in test are usually not constrained to the same strict high frequencyrequirements as functional logic paths, and as such, usually are not capable of highswitching speeds required for delay tests. The launch from capture scenario for testingdelay defects eliminates all reliance on these typically slow paths.

CLK

IN1

SIDSE Q

SO SIDSE Q

SO

SIDSE Q

SO

SE

SIDSE Q

SO

Functional

Logic

Functional

Logic

SIDSE Q

SO

Last Shift Launch Capture

1-0-X

1-0-0 0-0-X

1-0-X

1-0-XFault Site

1-0-X(values after each

clock pulse)

X-1-0

Clock

Scan Enable

Clock

Scan Enable

f(x)-X-X


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Launch from Shift

Launch from shift is another technique for exciting a fault effect. The values needed toexcite the initial value of the fault are loaded into the scan chains. The values needed toexcite the final value of the fault are also loaded into the scan chains and shiftedbackward (toward the scan-in primary input) one bit position along the scan chains. The

transition fault effect is created by performing one final shift operation, followed by aswitching of the scan enable from the scan state to the functional state, and thenfollowed by the high speed capture pulse. In this scenario, the scan enable pin must beswitched in the middle of the high speed sequence of clock pulses so that the faulteffect value can be captured from functional logic. This requires that the scan enable iscapable of switching at functional speed and that the tree of logic which feeds the scanenable signal to all of the flops in the device is a well-balanced tree from a timingperspective. This also requires extra effort from the designer and adds extra test-onlyrequirements for the layout and timing tools.

The advantages to this methodology are that ATPG runtime can be significantly

decreased for delay tests created this way because the ATPG algorithm is no longerrequired to back-track the logical values through functional logic in order to excite thefault effect. Also, coverage may increase over launch from capture because it is notalways possible to achieve certain circuit values or combinations of values due to thecontent of the functional logic.

CLK

IN1

SIDSE Q

SO SIDSE Q

SO

SIDSE Q

SO

SE

SIDSE Q

SO

Functional

Logic

Functional

Logic

SIDSE Q

SO

Last Shift Launch Capture

1-0-X

1-1-0 0-0-X

1-0-X

1-0-X

X-1-1

Fault Site

1-0-X(values after each

clock pulse)

X-1-0

Clock

Scan Enable

Clock

Scan Enable

0-X-X


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Timing ConsiderationsThus far, we have discussed delay defects and delay tests independently of timing.While the general algorithms and methods for delay test are applicable regardless of thesize of the defect and frequency response of the device under test, the quality of a delaytest can be compromised if the operating frequency is not taken into account. Thissection discusses how timing information is taken into account for delay tests, and thebenefits of doing so.

SDF Information

A Standard Delay Format (SDF) file contains timing information created by a statictiming analysis (STA) tool which is used by Encounter Test and other tools to annotatedelay information to a circuit. For guidelines on creating an SDF from various STA tools,refer to the application note titled Creating SDF Files for Encounter Test True-Time.

The SDF contains propagation delay information as well as timing checks for eachlibrary cell in the device. It can contain up to three different sets of information at thesame time to indicate a range of possible delays: best case, nominal case, and worstcase. The best case delays are the smallest possible delay that a properlymanufactured chip, running within the correct voltage and temperature ranges, canexperience at the given location. Likewise, the worst case is the largest possible delaywhich can be observed at a given location on a properly functioning circuit. The nominalcase is the average delay that would be expected at this location for a working chiprunning at its intended voltage and temperature.

SDF delay information can take into account various factors that affect timing. Some

detailed factors, such as cross-talk, are often neglected because their effects can beminimal and the CPU time required to account for them can be expensive. Note thatmore complete information in the SDF can be required when creating test patternswhich run faster than at-speed. Even small delay effects can become significant atthese speeds.

All delay information is described in the SDF as being through or with respect to alibrary cell. This abstraction allows delay data to be more easily mapped to logicalrepresentations of the circuit, as long as the hierarchy of the physical circuit ismaintained in the logical model. Any locations where the cell boundary cannot bemapped from the SDF to the circuit model will not be able to hold delay information, so it

is important that the same circuit model is used when the SDF is created and the SDFannotation is performed in Encounter Test.

Best and Worst Case Timings

Best and worst case timings are primarily driven by two factors: temperature, andvoltage. Every chip is designed to operate correctly within a certain limited range oftemperatures and voltage levels. Attempting to operate the chip outside of these rangescan result in device failures due to logical values arriving at a location too slowly or even
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too quickly. Operating the chip far outside of these ranges can result in permanentdamage to the device.

The SDF delay information contains a range of voltages and temperatures in which thebest and worst case delays will occur for valid working devices. These ranges arespecified in the header of the SDF, and should be observed carefully when running testpatterns created using the SDF information on the tester.

Temperature has an inverse effect on the operational frequency of a chip. Lowtemperatures lower the effective resistance of the materials of the chip and thus allowfor higher operating frequencies without failures. The nominal functional speed ischosen based on the frequency at which the device works flawlessly at the highestoperational temperature (worst case temperature) chosen by the designer.

The temperature range can vary for different kinds of devices. For example, a chipwhich is intended to operate inside of a car engine will have to tolerate much more heatthan one that will go into a hand-held device. Some chips are designed to run in super-

cooled environments for maximum performance. Some have a narrow temperaturerange, requiring that they operate in areas where the temperature is well-controlled.


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Higher rail voltage can allow a device to safely run at a higher frequency, just as lowervoltage will increase the delays across a chip. In the past, when tester hardware wasused for at-speed clock generation (as opposed to the on-product clocking which isgenerally used today), delay tests were often run at low voltage to make up for the poorfrequency response of the tester. Low voltage conditions exaggerate the size of delaydefects and the delays throughout the circuit, effectively removing the slack created bythe slow tester-generated clock frequency. We will discuss the concept of slack later inthis document.

In Encounter Test, delay tests will take into account the best and worst case possibletimings when test pattern data is created. Encounter Test will ensure that no portion ofthe device is made to run outside of its range of operating speeds at the giventemperature and voltage ranges in the SDF.

Generation of the SDF for the conditions which will exist in the test environment iscritical, as is the accuracy of this information. Encounter Test must be aware of theaccuracy frequency response behavior of the entire circuit in order to guarantee that itcan create test patterns which will run without miscompares on good chips on the tester.

The SDF contains propagation delays and timing checks to describe the frequencyresponse of a circuit.


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Propagation Delays

Propagation delays describe the amount of time required for a given transition toproceed from one point in the circuit to another. They come in two forms in the SDF: IO

path delays and interconnect delays.

IO path delays are the amount of time required for a given transition to propagatethrough a library cell. The dashed lines in the preceding diagram represent IO pathdelays. IO path delays in terms of a transition on a given input pin of a library cell causea transition on an output pin of the same cell. The transition on the input side does notnecessarily have to match the transition that it causes on the output. For example,consider a two-input XOR gate, where an input transition from 1 to 0 can cause theoutput to transition from 1 to 0 or 0 to 1 based on the value present on the second input.In the case of a leading-edge flop, the output transition is considered to be caused bythe leading edge of the clock. Hence, the IO path delay from the output of the flop is

specified in terms of the delay between the leading edge of the clock and the time thatthe Q output observes a transition.

Interconnect delays are the amount of time required for a given transition to propagatethrough the wires that go between library cells, or wires leading to or from primaryinputs and outputs.


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Timing Checks

Timing checks are information in the SDF that specify the timings which are required bycertain elements within the circuit. They specify timing relationships which must bemaintained at all times for the given library cell to correctly function. They are typicallysetup time, hold time, and minimum pulse width specifications relating to flops, but canalso specify other timing relationships. These do not physically represent a delay whichis manifested on a given path, but instead are more like a set of rules in order for thecell to operate in its intended way. Encounter Test reads and understands these rulesand creates test patterns which avoid breaking these rules, so that these patterns willwork properly on the tester. In order to avoid breaking these rules, Encounter Test hasto build a safety margin in to the test pattern timings which take all of these checks intoaccount, increasing the effective path length. The effective path length is the amount oftime required for a data transition to successfully traverse a given combinational logicpath and be captured at a destination).

Setup Times

A setup timing check is a rule which specifies the minimum amount of time that a datatransition is required to settle before a reference pin can receive a given transition. Thetypical case for a setup check is the data input of a flop being required to settle a givenamount before the leading edge of a clock pulse transition reaches the clock pin (whichis the reference pin).

To reproduce the worst case scenario, a setup timing check should be tested with the

latest possible data transition arrival time and the earliest possible clock arrival time. Ifthe setup check passes in this case, then we can be certain that this device will functioncorrectly for all operating conditions in the given temperature and voltage rangespecified in the SDF.

Note that a setup time check is a two-timeframe check. In the first timeframe, the datatransition must be launched from another source. In the second timeframe the captureclock arrives and the setup check is performed.


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Hold Times

A hold time check is a rule which specifies the minimum amount of time that is requiredon a given input before a data transition arrives with respect to a reference pintransition. The typical case for a hold check is the data input of a flop being required tosettle a given amount after the leading edge of a clock pulse transition reaches theclock pin (which is the reference pin).

To reproduce the worst case scenario, a hold time check should be tested with thelatest possible clock arrival time and the earliest data transition arrival time. If the holdcheck passes in this case, then we can be certain that this device will function correctlyfor all operating conditions in the given temperature and voltage range specified in theSDF.

Note that a hold time check requires only a single timeframe. Because of this holdviolations can occureven during static tests. We will look at the consequences ofviolations of timing checks in more detail later in this document.

Minimum Pulse Width

Minimum pulse width timing checks also exist within the SDF as a rule on how tooperate each memory element within its specifications. In order for a given memoryelement to successfully capture data, the clock pulse must be a certain width of time,otherwise the write into the memory element will not have settled to its final value.

The worse case scenario for a pulse width check occurs when you compare the latestpossible arrival of the leading edge of the clock to the earliest possible arrival of thetrailing edge of the clock.


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Clock Skew

In addition to propagation delays and timing check safety margins, clock skew isanother factor which can add to the effective path length. Clock skew is the difference inarrival times of clock pulses at the launching and capturing flops. Designers try to

minimize this difference as much as possible by creating balanced clock trees, butperfectly balanced clock trees are not always possible. The worst case clock skew iscalculated by comparing the latest possible arrival of the clock leading edge at thecapturing flop (DFF2 in the diagram) to the earliest possible arrival of the clock leading

edge at the launching flop (DFF1 in the diagram).

Clock skew may help or hurt the timing of a given path. For example, if the clock takeslonger to arrive at the capturing flop than it does at the launching flop, then it creates


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slack in this path, allowing the data transition more time to reach its destination.However, if the clock takes longer to arrive at the launching flop than the capturing flop,the skew adds to the effective length of the path.

Minimum Required Clock Period

Given a path from flop DFF1, through combination logic, and arriving at DFF2, we wouldcalculate the minimum required clock period to safely measure this path as follows:

Clock Period (Skew from DFF2.CLK to DFF1.CLK) +(Combinational logic propagation delay) +(Setup time from DFF2.D to DFF2.CLK)

Timing Violations

Timing violations occur when a timing check specified in the SDF has been violated.Since the timing checks in the SDF describe the requirements for a given library cell tooperate correctly, if these requirements are violated then the behavior of the library cell

is undefined. As a result, instead of known values being captured and propagated in thegiven cell, an unknown (X) value will be generated and/or captured. The type ofviolation that occurs determines how much logic will be affected by the unknown value.


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Setup Violations

Setup violations occur when there is insufficient time between a transition on a datapath and the arrival of a capture clock. This can typically happen as the result of atransition propagating through a long path of combinational logic (with a largepropagation delay). If the propagation delay (taking clock skew into account) is largerthan the clock period minus the setup time, a violation has occurred. A violation resultsin the capturing flop (DFF2 in the preceding figure) capturing an unknown value. In atypical delay test, consisting of only a launch and capture clock pulse, the unknownvalue will be captured and will not propagate further. However, if a customized clocking

sequence is used with additional clock pulses, the unknown value can propagate intoother downstream logic.


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Hold Violations

A hold violation occurs when there is insufficient time after the arrival of a clock and atransition on the data path of a given flop. This can typically happen as the result of atransition propagating through a very short path of combinational logic (small

propagation delay) and a large clock skew between the launching and capturing flops. Ifthe propagation delay is smaller than the clock skew plus the hold time, a violation hasoccurred. Note that hold violations occur with respect to a single timeframe. The sameclock pulse which launches the transition causes the capture of an unknown value.Hence, even in a single-timeframe static test, a hold violation can occur. In a standarddelay test, where there are only 2 clock pulses in the capture sequence, the unknownvalue will propagate to more downstream logic. In the preceding figure, DFF2 is the flop

which has the hold violation, but everything that DFF2 feeds will also receive unknown


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Be aware that this method can have some serious drawbacks. As the Xpropagates through the circuit, it may interfere with EncounterTests ability to testother faults which feed into the same cone of logic and observable registers. In

the preceding diagram, an X which is captured in DFF2 causes many faults to

become untestable. The only fault that remains testable is the one which can bepropagated to a different observable flop which is not fed by the timing-generatedX. This method is safe, and fast to process, but can be quite costly in terms oftest coverage.

ATPG Transition Constraints

Another method for safely handling timing violations is by creating and enforcing ATPGtransition constraints. If the ATPG engine can prevent the creation of a transition whichcauses a timing violation, then no violation will occur and unknown values will not

propagate to downstream logic.

For example, if the path from DFF1.Q to DFF2.D was longer than the clock period due

to a large delay between DFF1.Q and OR1.A1, it would normally cause a timing

violation at DFF2.D and result in many untestable faults as we saw in the example from

the discussion relating to X propagation. However, if we scan load DFF1 to a 0, and

create a test pattern such that DFF1 will capture a 0 again after the first clock pulse,


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then we will never launch the transition which will cause the timing violation at DFF2.D.

In this way, we limit the number of faults which are not testable to only those in the coneof logic that are required to constrain the transition. All other faults feeding into DFF2.D

remain testable.

This method can be compute-intensive and more difficult to verify, but it will result inhigher delay test coverage even when aggressive timings are used.

Quality of Delay Tests

The quality of a test can be judged by how likely it is to detect the physical defects that itis targeting.

Some physical defects are not large enough to cause functional failures. If we plottedthe length of each flop-to-flop path in a given domain (the arrival time of a transition atthe destination flop versus number of paths), we might get a plot similar to the green

curve in the preceding figure. We also might have some small delay defects which addto the lengths of some paths, but do not affect functional performance of the device(yellow curve/Non-critical defects). Even if we add in the extra time required due to thesmall defects, it is not enough to push the arrival time of the transition past the nominalfunctional speed of the device (therefore the device will capture the correct logicalvalues and work as expected).

However, if there are some delay defects which do push the transition arrival time pastthe functional clock period, then the device will fail (red markings/Critical defects).

A high quality delay test can detect all defects which will cause a functional device

failure. Some of these physical defects may add only several picoseconds to the lengthof a long path and others may add a nanosecond or more to the delay experienceddown a given path. The smallest of the critical defects are the most difficult to detect.These small delay defects would require generating a test pattern which sensitizes theexact path of logic which would cause the largest path delay. Alternatively, they can bedetected down shorter (and usually less complex) paths if the slack is removed fromthese short paths.


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Slack in Delay Tests

Slack is the amount of time after a given data transition arrives at an observable flopbefore the capturing clock pulse arrives at the same flop. This is shown in the pinkhighlighting above. A certain amount of slack is necessary and unavoidable in designsbecause it allows for a margin of error in the timing operation of the functional circuit (sothat the device can operate at a variety of temperatures, or in spite of some voltagefluctuation, for example). However, for delay tests, slack is counter-productive.

The amount of slack in a given path is inversely proportional to the size of the defectwhich can be detected down this path. Assuming that DFF1, DFF2, and DFF3 reside in

the same clock domain, and the clock tree is well balanced, each of these flops will

receive its capture clock at approximately the same time. For this device to operatecorrectly, the clock period must grow to accommodate the longest of the paths in thisclock domain. This longest pathis known as a critical path, since its timing is a criticalcomponent to determine the timing for the entire domain.

In the context of delay test, a physical defect is most likely to be detected if the amountof slack is kept to a minimum on the path through which the fault effect is propagated. Ifthere is a minimum of slack, then even very small additional delays (due to a delay


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defect) down the path are likely to cause the faulty value to be captured (and hence thedefect to be detected). Slack can be minimized by creating faster than at-speed tests,which will be discussed in detail later in this document.


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Path TestsA path test is a very specific kind of delay test which is used to target critical paths in thedesign, where small delay defects can have large impacts on functional operation. Path

tests can ensure that these critical paths do not have small delay defects,. They canalso be used for speed binning, which would characterize parts based on the delaydefects (caused mainly by process variation) along the critical paths and how far out itpushes the domain timing. This allows a manufacturer to increase yield by acceptingsome parts with small delay defects as passing at a slower clock frequency than theintended design. Path tests are created for critical paths and are run at various clockfrequencies until a passing frequency is found.

Path Fault Model

The Encounter Test path fault model consists a set of path groups, each containing one

or more path faults. Path groups are given a user-specified name and are defined byspecifying one or more nodes along the path. Path faults are the individual topologicalpaths that define the path group, including the type of transition (rising or falling) whichis being propagated through a given node.

Path groups may specify one or more topological paths based on the way nodes arespecified in the group definition. All of the topological paths which pass through all of thenodes in the path group definition will become part of the path group as individual path


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faults. Also, all possible transitions through each topological path will become separatepath faults. Referring to the previous diagram, a group definition that only includes

topological Path 1 will contain two path faults: the first with a 0 to 1 transition on

DFF1.Q and the second with a 1 to 0 transition on DFF1.Q.

Some types of gates can cause more path faults to be created because the type oftransition on their output can be rising or falling for a single input side transition. Forexample, an XOR gate can cause a rising transition on its input to become a rising orfalling transition on its output based on the value on its other input. A mux can have asimilar effect. Encounter Test enumerates these transition possibilities as separate pathfaults, but will include them all in the same path group.

The following table lists examples of how the paths defined in the previous diagram willbe incorporated into path groups:

Path Group Definition #

PathFaults

Path1 Path2 Path3 Path4 Nodes in path

Group1 AND1.Y; 8 X X X X All nodes

Group2 OR2.Y;4 X X

DFF3.Q, DFF4.Q, OR2.A1,OR2.A2, AND1.A2, AND.Y,DFF2.D

Group3 DFF3.Q;

4 X X

DFF3.Q, OR1.A2, OR2.A1,OR1.Y, OR2.Y, AND1.A1,

AND1.A2, AND1.Y,DFF2.D

Group4 DFF3.Q OR2.Y;2 X

DFF3.Q, OR2.A1, OR2.Y,AND1.A2, AND1.Y,DFF2.D

Group5 OR1.Y OR2.Y; 0 No paths defined

Testing Path Groups versus Path Faults

When creating a definition for the path group, all of the individual path faults that areenumerated by the group can be addressed either individually or as a group. Likewise,path test ATPG can be targeted on individual path faults or on entire path groups. Whena path group is targeted by ATPG, the fault status of each individual path fault in thegroup is logically ORd to derive the fault status of the path group. In effect, if any pathfault within the group is tested, the entire path group is reported as tested. Once thepath group is marked tested, the ATPG engine moves on to the next path group and willnot attempt to create tests for other individual path faults within the path group. This isthe default behavior for path test in Encounter Test.

You can change this behavior by setting the threshold value for the number of faults thatare detected in a given group before the path group is marked as tested. Setting thisthreshold to a sufficiently high number can cause each individual path fault to betargeted by ATPG if this is the design intent. Generally, the default behavior is adequatebecause it does guarantee that the critical path is tested if the path group is correctlydefined.


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Path Test Quality

The quality of the test patterns created to target path faults can vary. Depending on yourrequirements, you may want to ensure that the transitions being propagated through the

critical paths maintain their integrity as they approach a capture flop. The ATPG enginewill have to use greater care to prevent glitches from corrupting the transition, and mayrequire more processing time and more care bits in the pattern itself. Even if yourrequirements for path test quality are low, it can be useful to measure the quality of agiven path test pattern based on the degree to which the transitions integrity ispreserved. There are four general categories to grade the quality of a path test: hazardfree robust, robust, nearly robust, and non-robust.

Hazard-Free Robust

A hazard-free robust path test will guarantee that the integrity of the transition iscompletely preserved and no glitches or hazards are created along the path. All gateinputs which are not part of the path must be at a steady non-controlling value for therelease and capture timeframes of the path delay test.


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Nearly robust tests are much more lenient than robust tests. Glitches are allowed on theinputs which are not part of the path, as long as the integrity of the initial value of thetransition and the integrity of the final value of the transition are preserved.

Non-Robust

Non-robust path tests represent the possibility that the desired transition reaches anobservable flop. This is the most lenient path test fault classification. Given thecombination of inputs on a primitive, if there is any possibility that the desired transitioncan propagate to the output, then the path is classified as non-robust. Looking at theAND1 gate as an example, if the path transition (inputA1) is 1 to 0, and theA2 input is

0 to 1, it is still possible for the 1 to 0 transition to be reflected in the output if the

transition onA2 arrives before the transition onA1. This will produce a glitch on the

output, where a logic 1 is briefly observed, and then the transition from 1 to 0 occurs.

For non-robust path tests, the only qualification is that the final value of the transitionmust be reflected in a stable way on the output.

Differences from Delay Test Generation

Structural delay tests are intended to cover an entire design with the fewest number ofpatterns. The propagation paths of delay faults are not considered as important as thenumber of delay faults which are covered. By contrast, in the realm of path test, the

pattern count is not nearly as important as the test quality. Test quality demands thatdelay faults are observed down paths which have the smallest amount of slack. So aspecific propagation path and specific timing (the expected arrival time of a transitionpropagating along the exact chosen path) are both required for optimal results.

Because of these differences, the overall process for delay testing differs from theprocess for creating path tests in the areas of merging test patterns, the number ofobservation points, and whether or not dont carescan bits are filled with random data.


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Pattern Merging

When a path test is used for speed binning, the amount of slack allowed in the path iscritical. Choose various frequencies to determine the highest speed at which the criticalpath can still capture the correct data. Ifcarebits from multiple path test patterns aremerged into a single pattern, then the observes for multiple paths will occur at the sametime during the capture clock pulse. However, these paths will most likely have differentamounts of slack. This will result in the path test for the shorter path becomingineffective for speed binning. For the purpose of speed binning, each path should betimed individually with as much of the slack removed as possible. If a path requires adifferent frequency to remove the slack, it should be in a unique test pattern, not mergedwith an existing pattern.

Measure Locations

By the same argument against merging test patterns, each path test should observeand compare values at the capture locations of the path itself. Propagating the path faulteffect to other observation points will result in different timing requirements for thesenew paths, invalidating their use for speed binning, and potentially even causingmiscompares if the paths to the new observation points are too long. For example, if a

measure occurs at DFF2 in the preceding diagram, it will cause a miscompare if thepattern was targeting the DFF4 to DFF5 path.

Another argument for limiting the number of measure locations is the ease ofdiagnosing on the tester. Tracing down the source of a miscompare is simplified if theonly measure location of a test pattern is the end of a single path. This can assist withdelay test pattern bring-up time.


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Effects of Random Fill Data

Random fill data can result in sensitizing other paths at the same time as the path whichis being targeted. This is effectively similar to merging test patterns, which again should

be avoided because the timing will not be customized for these other paths, leading toineffective tests and possible miscompares.

Compression Issues

The desirability to measure at only a single scannable flop for path tests createsdifficulties in hardware with compression test structures. Measuring at only a singlelocation will effectively result in a massive amount of Xs trying to reach yourcompression logic. All of these locations will have to be masked for each shift cycle,except the single location. Path test in compression hardware will require robustmasking hardware to allow this single value to be measured while all others aremasked.

Creating path tests in the compressed environment can still be quite beneficial, in spiteof these challenges. Since we would prefer that each path is tested in its own pattern, ifa large number of paths must be tested then the tester data volume in a full scan testmode can become problematic. Using a compression test mode allows you to reducethe tester data volume by the virtue of the shorter internal scan chains. This can be thedifference between being able to run a few critical paths and thousands of critical paths.


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Delay Faults on Scan-Only PathsIn a structural delay test environment, delay faults are enumerated at all possiblelocations, even areas of the design which will not be operating at high speeds. The most

notorious of areas that will not operate at high speed are scan-only paths. Using launchfrom capture test patterns, where the scan enable is off and two clock pulses are issuedto excite faults, it will be impossible to detect any faults on scan-only paths. Since delaytests are typically created in this environment, scan-only paths can account for a largenumber of untested faults in your fault population, which makes your delay testcoverage appear far worse than it actually is.

Detecting Scan-Only Delay Faults

Delay faults on scan-only paths can be targeted using launch from shift patterns,however, running a full ATPG job with launch from shift test sequences will mark off

many delay faults with test patterns that have to be run at much slower speeds thanequivalent launch from capture test patterns. This is undesirable because at slowspeeds we will only detect the very largest of delay defects with these test patterns.High speed patterns are required to detect smaller delay defects as discussed earlier.

An appropriate compromise for these problems is to create test patterns that target thescan-only paths without targeting functional logic which can be tested using faster testpatterns. This can be accomplished by creating a scan chain delay test. This is a test

pattern which loads up the scan chains with a marchstyle of pattern (1000111...) andcreates a double clock pulse on the shift clocks while the scan enable is held high toexcite and capture transition faults.

After creating a scan chain delay test, the delay faults which can only be tested usingslow test patterns that are marked off and the rest of the delay faults can be targetedusing launch from capture high speed test sequences.

Apriori Fault Mark-Off

Another way to deal with delay faults on scan-only paths is to assume that they arealready detected due to normal shift operations. It is very likely that within a set of evenseveral hundred test patterns, every combination of transitions has been exercised oneach scannable flop, so this is generally a safe assumption. You can instruct Encounter

Test to remove delay faults from the scan-only paths by performing an apriori faultmark-off. This process identifies the delay faults along the scan-only paths and marksthem as being testedso that future ATPG jobs will not try to target these faults. This hasthe advantage of saving the time required to fault simulate a scan chain delay testpattern and still results in realistic delay fault coverage. The disadvantage to apriori faultmark-off is that there will not be any stand-alone test patterns which test the integrity ofthe scan chain, so if a physical delay test failure does occur on the chain it will be moredifficult to diagnose on the tester.


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SummaryAll of the concepts discussed in this document are fully supported and understood byEncounter True-Time Delay Test. Refer to the application note True Time Delay TestMethodologyfor information about supported methodologies for delay test and anoverview of the True Time Use Model flow. Refer to Encounter Test documentation for acomplete reference of all available options for delay test

true time concepts an

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