Upload File

verilog tutorial, part deux - university of california ... · verilog tutorial, part deux by sat...

  • Home
  • Documents
  • Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int
21
1 Verilog Tutorial, Part Deux By Sat Garcia

Upload: hoangdiep

Post on 28-Aug-2018

238 views

Category:

Documents


1 download

Report

TRANSCRIPT

Page 1: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

1

Verilog Tutorial, Part Deux

By Sat Garcia

Page 2: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

2

Complete the quote

 “Good artists __________ . Great artists __________.” - Pablo Picasso

 The following slides are only slightly modified from those in the MIT 6.375 course  http://csg.csail.mit.edu/6.375/

copy steal

Page 3: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

3

Designing a GCD Calculator  Euclid’s Algorithm for GCD (in C):

int GCD( int inA, int inB) { int done = 0; int A = inA; int B = inB; while ( !done ) { if ( A < B ) // if A < B, swap values { swap = A; A = B; B = swap; } else if ( B != 0 ) // subtract as long as B isn’t 0 A = A - B; else done = 1; } return A; }

How do we implement this in hardware?

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 4: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

4

Take 1: Behavioral Verilog module gcdGCDUnit_behav#( parameter W = 16 ) // parameterize for better reuse ( input [W-1:0] inA, inB, output [W-1:0] out );

reg [W-1:0] A, B, out, swap; integer done;

always @(*) begin done = 0; A = inA; B = inB;

while ( !done ) begin if ( A < B ) swap = A; A = B; B = swap; else if ( B != 0 ) A = A - B; else done = 1; end

out = A; end

endmodule

What’s wrong with this approach?

Doesn’t synthesize! (notice that data dependent loop?)

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 5: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

5

Making the code synthesizable

 Start with behavioral and find out what hardware constructs you’ll need  Registers (for state)  Functional units

 Adders / Subtractors  Comparators  ALU’s

Page 6: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

6

Identify the HW structures module gcdGCDUnit_behav#( parameter W = 16 ) ( input [W-1:0] inA, inB, output [W-1:0] out );

reg [W-1:0] A, B, out, swap; integer done;

always @(*) begin done = 0; A = inA; B = inB;

while ( !done ) begin if ( A < B ) swap = A; A = B; B = swap; else if ( B != 0 ) A = A - B; else done = 1; end

out = A; end

endmodule

State → Registers

Less than comparator

Equality Comparator

Subtractor

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 7: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

7

Next step: define module ports

input_available

operands_bits_A

operands_bits_B

result_bits_data

result_taken

result_rdy

clk reset

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 8: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

8

Implementing the modules

 Two step process: 1. Define datapath 2. Define control/control path

Control

Datapath Data inputs

Data output

Control in/outputs Control in/outputs

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 9: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

9

Developing the datapath

B

A = inA; B = inB;

while ( !done ) begin if ( A < B ) swap = A; A = B; B = swap; else if ( B != 0 ) A = A - B; else done = 1; end

Y = A;

zero? lt

A sub

Also need a couple MUXs

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 10: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

10

Adding control

B

A mux sel

A reg en

B mux sel

B reg en A < B B = 0

zero? lt

A sub

A = inA; B = inB;

while ( !done ) begin if ( A < B ) swap = A; A = B; B = swap; else if ( B != 0 ) A = A - B; else done = 1; end

Y = A;

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 11: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

11

Datapath module module gcdDatapath#( parameter W = 16 ) (

input clk,

// Data signals input [W-1:0] operands_bits_A, input [W-1:0] operands_bits_B, output [W-1:0] result_bits_data,

// Control signals (ctrl->dpath) input A_en, input B_en, input [1:0] A_mux_sel, input B_mux_sel,

// Control signals (dpath->ctrl) output B_zero, output A_lt_B

);

B

A sel

A en

B sel

B en A < B B = 0

zero? lt A

sub

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 12: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

12

Implementing datapath module wire [W-1:0] B; wire [W-1:0] sub_out; wire [W-1:0] A_mux_out;

3inMUX#(W) A_mux ( .in0 (operands_bits_A), .in1 (B), .in2 (sub_out), .sel (A_mux_sel), .out (A_mux_out) );

wire [W-1:0] A;

ED_FF#(W) A_ff // D flip flop ( // with enable .clk (clk), .en_p (A_en), .d_p (A_mux_out), .q_np (A) );

wire [W-1:0] B_mux_out; 2inMUX#(W) B_mux ( .in0 (operands_bits_B), .in1 (A), .sel (B_mux_sel), .out (B_mux_out) ); ED_FF#(W) B_ff ( .clk (clk), .en_p (B_en), .d_p (B_mux_out), .q_np (B) );

2inEQ#(W) B_EQ_0 ( .in0(B),in1(W'd0),.out(B_zero) ); LessThan#(W) lt ( .in0(A),.in0(B), .out(A_lt_B) ); Subtractor#(W) sub (.in0(A),in1(B),.out(sub_out) ); assign result_bits_data = A;

Remember: Functionality only in “leaf” modules!

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 13: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

13

State machine for control

WAIT

CALC

DONE

input_availble

( B = 0 )

result_taken

Wait for new inputs

Swapping and subtracting

Wait for result to be grabbed

reset

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 14: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

14

Implementing control module

B

A sel

A en

B sel

B en A < B B = 0

zero? lt A

sub

module gcdControlUnit (

input clk, input reset,

// Data signals input input_available, input result_rdy, output result_taken,

// Control signals (ctrl->dpath) output A_en, output B_en, output [1:0] A_mux_sel, output B_mux_sel,

// Control signals (dpath->ctrl) input B_zero, input A_lt_B

);

Remember: Keep next state (combin.), state update (seq.), and output logic separated!

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 15: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

15

State update logic  Remember: keep state update, next state

calculation, and output logic separated

localparam WAIT = 2'd0; // local params are scoped constants localparam CALC = 2'd1; localparam DONE = 2'd2;

reg [1:0] state_next; wire [1:0] state;

RD_FF state_ff // flip flop with reset ( .clk (clk), .reset_p (reset), .d_p (state_next), .q_np (state) );

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 16: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

16

Output signals logic reg [6:0] cs;

always @(*) begin

// Default control signals A_mux_sel = A_MUX_SEL_X; A_en = 1'b0; B_mux_sel = B_MUX_SEL_X; B_en = 1'b0; input_available = 1'b0; result_rdy = 1'b0;

case ( state )

WAIT : ... CALC : ... DONE : ... endcase end

WAIT : begin A_mux_sel = A_MUX_SEL_IN; A_en = 1'b1; B_mux_sel = B_MUX_SEL_IN; B_en = 1'b1; input_available = 1'b1; end

CALC : if ( A_lt_B ) A_mux_sel = A_MUX_SEL_B; A_en = 1'b1; B_mux_sel = B_MUX_SEL_A; B_en = 1'b1; else if ( !B_zero ) A_mux_sel = A_MUX_SEL_SUB; A_en = 1'b1; end

DONE : result_rdy = 1'b1;

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 17: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

17

Next state logic always @(*) begin

// Default is to stay in the same state state_next = state;

case ( state )

WAIT : if ( input_available ) state_next = CALC;

CALC : if ( B_zero ) state_next = DONE;

DONE : if ( result_taken ) state_next = WAIT;

endcase end

WAIT

CALC

DONE

input_availble

( B = 0 )

result_taken

reset

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 18: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

18

Next step: define module ports

input_available

operands_bits_A

operands_bits_B

result_bits_data

result_taken

result_rdy

clk reset

Adapted from Arvind and Asanovic's MIT 6.375 lecture

Page 19: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

19

Wire them together

B

A sel

A en

B sel

B en A < B B = 0

zero? lt A

sub

Adapted from Arvind and Asanovic's MIT 6.375 lecture

module gcd#( parameter W = 16 ) (

input clk,

// Data signals input [W-1:0] operands_bits_A, input [W-1:0] operands_bits_B, output [W-1:0] result_bits_data,

// Control signals input input_available, input reset, output result_rdy, input result_taken

);

wire[1:0] A_sel; wire A_en; …

gcdDatapath#(16) datapath ( .operand_bits_A(operands_bits_A), … .A_mux_sel(A_sel), … )

gcdControl#(16) control ( .A_sel(A_sel), … )

Page 20: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

Wire them together module gcd#( parameter W = 16 ) (

input clk,

// Data signals input [W-1:0] operands_bits_A, input [W-1:0] operands_bits_B, output [W-1:0] result_bits_data,

// Control signals input input_available, input reset, output result_rdy, input result_taken

);

Page 21: Verilog Tutorial, Part Deux - University of California ... · Verilog Tutorial, Part Deux By Sat Garcia . 2 Complete the quote ... Euclid’s Algorithm for GCD (in C): int GCD( int

But wait, there’s more

 Build test bench a la lab 1  Test thoroughly, debug  Measure cycle time, optimize, etc.


iRC2570 31xx Series Gtc Gcd

VERILOG - RWTH Aachen Universityhpac.cs.umu.se/teaching/sem-hpsc-14/presentations/Verilog slides.pdf · What is Verilog ? Verilog is a hardware description language(HDL) Verilog is

Verilog Fundamentals · 2016. 8. 30. · verilog fundamentals hdls history how fpga & verilog are related coding in verilog

Polynomial Division, Remainder,GCD

Pune-Cocoa: Blocks and GCD

GCD 2015 Day 1

GCD Series DimensionsandLandPatterns. UNIT:mm · 2017. 11. 29. · gcd kt270 27 k 1khz/0.25v 0.4110 0.325 0.680 0.930 GCD KT330 33 K 1KHZ/0.25V 0.5330 0.408 0.625 0.840 GCD KT390

GCD of n Numbers

Word Problems LCM and GCD

Dealer Agreement GCD

By Conor Buckley. Index What is Golf Coach Direct? The Team behind GCD My Experience Working for GCD Highlight of my work for GCD Q&A

Gcd cc-150205

VHDL,Verilog and Advanced Verilog

Verilog – Sequential Logic - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/Verilog for synthesis - sequential logic rev... · Verilog – Sequential Logic Verilog for Synthesis

GCD Infographic

2013 GCD Studios Master Catalog

GCD & LCD VII

Verilog Fundamentals · Verilog Fundamentals. VERILOG FUNDAMENTALS ... Verilog is a HARDWARE DESCRIPTION LANGUAGE. ... Level 2 : Design a digital system using Verilog . (weightage

GCD Costa Daurada

7 Math-M... · 2016. 7. 13. · ˚ - % ˆ1" xy, + *˚5- gcd , a b ax by ˆ˙" ˜* : 1. gcd 758,242 758 242 x y 2. gcd 726,275 726 275 x y 3. gcd 237,81 237 81 x y 4. gcd 616,427 616

Recursive GCD Demo

Euclidean Algorithm for GCD and

GCD Woofstock logo

Algorithm Design: GCD - People at VT Computer Sciencepeople.cs.vt.edu/.../Algorithm_Design.pdf · Barbara G. Ryder Spring 1998 2 Algorithm Design: GCD(12) How to find the GCD of 2

High Frequency - Global Manufacturing...You have purchased a GCL-4400/GCD-4400, GCL-5000/GCD-5000, GCL-5500/GCD-5500, or GCL-6500/ GCD-6500 High Frequency vibrator manufactured by

Polynomial GCD Algorithms

GCD: VLSI's Hello World Overview

Grand Central Dispatch (GCD)

GCD Daily Day 3

Verilog Fundamentals Verilog 1 - Fundamentalscsg.csail.mit.edu/.../handouts/lectures/L02-Verilog-Fundamentals.pdf3 6.375 Spring 2007 • L02 Verilog 1 - Fundamentals • 5 Designers

Brush Country GCD, Feliz Saenz

Panola County GCD DFC Evaluations

Division and GCD

Kenedy County GCD, Mary Sahs

Introduction to Discrete Mathematics AB C a = qb+r gcd(a,b) = gcd(b,r)