vhdl file

EXPERIMENT NO.1

AIM:Design of a combinational circuit 2-4 decoder and encoder and a binary to gray converter.

1) 2x4 DecoderVHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec_24 is Port ( input : in STD_LOGIC_VECTOR (1 downto 0); output : out STD_LOGIC_VECTOR (3 downto 0));end dec_24;

architecture dec_arch of dec_24 is

beginoutput<="0001" when input<="00" else

"0010" when input<="01" else "0100" when input<="10" else "1000" when input<="11";

end dec_arch;

SIMULATION

SYNTHESIS

TRUTH TABLE

A B Y0 Y1 Y2 Y3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

BLOCK DIAGRAM

2) 4x2 EncoderVHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity enc_42 is Port ( input : in STD_LOGIC_VECTOR (3 downto 0); output : out STD_LOGIC_VECTOR (1 downto 0));end enc_42;

architecture enc_arch of enc_42 is

beginoutput<="00" when input<="0001" else

"01" when input<="0010" else "10" when input<="0100" else "11" when input<="1000";

end architecture;

SIMULATION

SYNTHESIS

BLOCK DIAGRAM AND TRUTH TABLE

3) Binary to Gray Code Converter

VHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity converter is Port ( input : in STD_LOGIC_VECTOR (3 downto 0); output : out STD_LOGIC_VECTOR (3 downto 0));end converter;

architecture convert_arch of converter is

beginoutput(3)<=input(3);output(2)<=input(3) xor input(2);output(1)<=input(2) xor input(1);output(0)<=input(1) xor input(0);

end convert_arch;

EXPERIMENT NO. 2

AIM : Model a flip-flop, register and a latch in VHDL. Implement with asynchronous and synchronous reset.

a) D flip-flop : SynchronousVHDL CODE :

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff isport (d,clk,rst : IN std_logic; q : OUT std_logic);end dff;

architecture Behavioral of dff isbeginprocess(clk)beginif (clk='1' and clk'event) thenif (rst='1') thenq <= '0';elsif (rst='0') then q <=d;end if;end if;end process;end Behavioral;

SIMULATION :

RTL SCHEMATIC :

b) D flip-flop : ASYNCHRONOUS

VHDL CODE :

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity DFFASR isport (ASR,D,CLK: IN STD_LOGIC;

Q :OUT STD_LOGIC);end DFFASR;architecture Behavioral of DFFASR isbegin

process(CLK,ASR)begin

if(ASR='1') thenQ <= '0';

elsif(CLK'EVENT and CLK ='1') thenQ <= D;

end if;end process;

end Behavioral;

SIMULATION :

RTL SCHEMATIC :

c) LOADABLE REGISTER : Synchronous

VHDL CODE :


entity LRSR isport ( Din: in std_logic_vector(7 downto 0);

Qout: out std_logic_vector(7 downto 0);Load,clk,reset: in std_logic );

end LRSR;

architecture Behavioral of LRSR issignal NS, PS : std_logic_vector(7 downto 0) := "01010101";beginabc:process(clk) beginif(clk'event and clk='1')then

if(Reset='1') thenPS<= "00000000";elsePS<=NS;end if;

end if;end process abc;

def:process(Din, Load, PS)beginNS<=PS;if(Load='1') thenNS<=Din;end if;end process def; Qout<=PS;end Behavioral;

SIMULATION :

RTL SCHEMATIC :

d) LOADABLE REGISTER : Asynchronous

VHDL CODE :


entity LRASR isport( Din: in std_logic_vector(7 downto 0);

Qout: out std_logic_vector(7 downto 0);Load,clk,reset: in std_logic );

end LRASR;

architecture Behavioral of LRASR issignal NS, PS : std_logic_vector(7 downto 0) := "01010101";beginabc:process(clk,Reset) begin

if(Reset='1') then

PS<= "00000000";elsif(clk'event and clk='1')thenPS<=NS;end if;

end process abc;

def:process(Din, Load, PS)beginNS<=PS;if(Load='1') thenNS<=Din;end if;end process def; Qout<=PS;end Behavioral;

SIMULATION :

RTL SCHEMATIC :

e) LATCH

VHDL CODE :


entity latch isport (d,rst : IN std_logic; q : OUT std_logic);end latch;

architecture Behavioral of latch isbeginprocess(d,rst)beginif (rst='1') thenq <= '0';elsif (rst='0') then q <=d;end if;end process;end Behavioral;

SIMULATION :

RTL SCHEMATIC :

EXPERIMENT NO. 4

AIM : Model a Serial in parallel out (SIPO) shift register using VHDL.

VHDL CODE :


entity SIPO isport(clk,x: in std_logic; q : out std_logic_vector(3 downto 0));end SIPO;

architecture Behavioral of SIPO issignal q1: std_logic_vector(3 downto 0):="0000";

beginprocess(clk)beginif clk'event and clk='1' thenq1(3)<=q1(2);q1(2)<=q1(1);q1(1)<=q1(0);q1(0)<=x;end if;end process;q<=q1;end Behavioral;

SIMULATION :

RTL SCHEMATIC :

EXPERIMENT NO. 5

AIM : Model a Binary counter, Ripple counter and BCD counter using VHDL.

1) BINARY COUNTER

VHDL CODE :library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity binarycounter isPort ( CLK : in STD_LOGIC; OUTP : out STD_LOGIC_VECTOR (3 downto 0); DIRECTION : in STD_LOGIC);end binarycounter;

architecture Behavioral of binarycounter issignal count: STD_LOGIC_VECTOR (3 downto 0) := "0000";beginprocess(CLK) begin

if (CLK='1' and CLK'event) then if DIRECTION='1' then count <= count + 1; else count <= count - 1; end if; end if;end process;OUTP <= count;end Behavioral;SIMULATION :

RTL SCHEMATIC :

(a) RIPPLE COUNTER

VHDL CODE :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ripple is

Port ( CLK : in STD_LOGIC;

OUTP : out STD_LOGIC_VECTOR (3 downto 0));

end ripple;

architecture STRUCTURAL of ripple is

component TFF

port

(T,CLK: IN STD_LOGIC;

Q :out STD_LOGIC

);

end component;

signal OUTP1: STD_LOGIC_VECTOR (3 downto 0):="0000";

begin

G1: TFF port map('1',CLK,OUTP1(0));

G2: TFF port map('1',OUTP1(0),OUTP1(1));



OUTP<= OUTP1;

end STRUCTURAL;

SIMULATION :

RTL SCHEMATIC :

(b) BCD COUNTER

VHDL CODE :


entity bcdcounter isport(CLK : IN STD_LOGIC;OUTP: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));end bcdcounter;

architecture Behavioral of bcdcounter isCONSTANT SO: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";CONSTANT S1: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";CONSTANT S2: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";CONSTANT S3: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";CONSTANT S4: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";CONSTANT S5: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";CONSTANT S6: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";CONSTANT S7: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";CONSTANT S8: STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";CONSTANT S9: STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";SIGNAL PS, NS: STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";begin

PROCESS(CLK)begin

if(clk'event and clk='1')thenNS<=SO;if(PS=SO) thenNS<=S1;elsif(PS=S1) thenNS<=S2;elsif(PS=S2) thenNS<=S3;elsif(PS=S3) thenNS<=S4;elsif(PS=S4) thenNS<=S5;elsif(PS=S5) thenNS<=S6;elsif(PS=S6) thenNS<=S7;elsif(PS=S7) thenNS<=S8;elsif(PS=S8) thenNS<=S9;elsif(PS=S9) thenNS<=SO;end if;

end if;end process;OUTP<=PS;PS<=NS;end Behavioral;

SIMULATION :

RTL SCHEMATIC :

EXPERIMENT NO. 6

AIM : Model an ALU using VHDL.

VHDL CODE :

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity ALU isPort ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); rst : in STD_LOGIC;

sel : in STD_LOGIC_VECTOR (2 downto 0); carry : out STD_LOGIC; o : out STD_LOGIC_VECTOR (3 downto 0); en : in STD_LOGIC);end ALU;

architecture Behavioral of ALU isbeginprocess(sel)

beginif rst='1' then

o<="0000";elsif (en='1') then

case sel iswhen "000"=> o<=(A or B);when "001"=> o<=(A and B);when "010"=> o<=(not A);when "011"=> o<=(A xor B);when "100"=> o<=(A+B);

if (A+B = "1111") thencarry<='1';

else carry<='0';

end if;when "101"=> o<=(A-B);

if (A<B) thencarry<='1';

elsecarry<='0';

end if;when "110"=> o<=(A+1);

if(A="1111") thencarry<='1';

elsecarry<='0';

end if;when "111"=> o<=A;when others => o<=A;

carry<='0'; end case;end if;

end process;end Behavioral;

SIMULATION :

RTL SCHEMATIC :

Experiment 3To check whether an input stream of bits is divisble by 5.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mod5 isport(num :in std_logic_vector(7 downto 0);

div :out std_logic);end mod5;

architecture Behavioral of mod5 isbeginprocess(num)type states is (s0,s1,s2,s3,s4);variable state: states;variable counter : integer ;beginstate := s0;for counter in 7 downto 0 loop

if(num(counter) ='1') thenif(state = s0) then

state := s1;elsif(state = s1) then




state :=s4;end if;

elsif(num(counter)= '0') thenif(state = s0) then





state :=s3;

end if;

end if;end loop;

if(state = s0) thendiv <= '1';

elsediv <= '0';end if;

end process;end Behavioral;

Output:

Experiment 7Design of a traffic light controller using VHDL.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity traffic isport(yellow : out std_logic;

green : out std_logic;red : out std_logic;reset : in std_logic;

clock : in std_logic);end traffic;

architecture Behavioral of traffic istype states is (s0,s1,s2,s3);begin

process(reset,clock)variable count :integer range 0 to 10:=0;variable state :states;

beginif(reset ='1') then

state := s0;count := 0;red<='1';

elsif(clock='1' and clock'event) then

if(state =s0) thenif(count = 5) then

state := s1;count := 0;

elsered<= '1';yellow<='0';green<='0';count := count+1;

end if;

elsif(state =s1) thenif(count = 3) then



end if;

elsif(state =s2) thenif(count = 5) then



end if;

elsif(state = s3) thenif(count = 3) then



end if;

end if;end if;

end process;

end Behavioral;

Output:

vhdl file

Documents

library ieee use

2x4 decoder vhdl code

gray converter

combinational circuit

port input