VLBA Technical Report No. 40VLBA Output Rate Synthesizer

Module L123Alan E.E. Rogers

October 1988

VLBA OUTPUT RATE SYNTHESIZER - MODULE L123

Alan E.E. Rogers October 1988

Table of Contents

Drawing List .............................................Specifications ..........................................General Description.....................................Theory of Operation.....................................Circuit Details..........................................Front Panel Monitor.....................................Input and Output Connections and Power Levels. . .Test Procedures..........................................Replacement Instructions ..............................Parts List ...............................................Data Sheets...............................................

Drawing List:

Drawing Number

542305003542305004 5423 0S005 54230M009 54230M008 54230M001 5423ORATE 5423 0RATEDIV 542101002 54210M010

Title

Module Block Diagram Output rate Synthesizer Synthesizer divider Output rate Synthesizer Outrate syn. divider Front Panel Synthesizer PC Board Syn. divider PC Board Front Panel Mounting plate

Type

Block Diagram Circuit Diagram Timing Diagram Drilling Plan Drilling Plan Drilling Plan PC Artwork PC Artwork Silkscreen Drill plan

Specifications:

Output Frequency

Auxilliary output

Input Reference Frequency

189 MHz, 190.072 MHz and these divided by 2,4,8,16,32 at freq above divided by 21 5 MHz

1

General Description:

This module derives the frequency needed to take the data out of the formatter. Thus the required frequency is somewhat higher than the data rate on each track by an amount needed to add the extra "overhead" bits. In the case of a Mark III format the overhead is an added parity bit every 8 data bits. For example when MK III data is recorded at 8 Mbits/sec per track 9 MHz is needed to clock the data out of the formatter and 9x21=189 MHz is needed for the bit synchronizer reference in the recorder. If the proposed VLBA non-data-replacement format is used the overhead is increased so that 190.072 is needed for bit synchronizer reference.

Theory of Operation:

A crystal oscillator is divided to 1 kHz and phase locked to a 1 kHz reference derived from 5 MHz. The loop filter is designed using the same general principles as used in the baseband converter synthesizer.

Circuit Details:

The MC14152 PPL frequency synthesizer chip is the heart of the circuit. Either a Vectron 189 MHZ VCXO (for MKIII) or 190.512 VCXO (for VLBA) is selected by a diode switch. The oscillator signal is then divided by 21 before passing to the PPL SYN which operates with a divide by 32/33 swallow counter external to the 14152. The 5 MHz reference is divided to 8 kHz and is divided further to , 1 kHz in the 14152. The OP-27EN provides the loop filter/amplifier. Division by factors of 2 is provided in a separate submodule.

Front Panel Monitors:

The front panel BNCs provide buffered outputs of both the high frequency and the frequency divided by 21.

I/O Connections:

Pin # Function

1 Ground2 +5v (50 ma)3 5 MHz Input + 13 dB Nominal4 Synthesizer output5 divide by 21 output6 NC7 NC8 NC9 NC

10 NC

2

11 NC12 NC13 NC14 NC15 +I5v (200 ma)16 VLBA/MK III cntr.17 Control 113 Control 219 Control 320 NC

Test Procedures:

Check the output on a scope for frequency and phase stability. Check the divide by 21 output.

Replacement Instructions

Try to isolate problem. The divider submodule can be independently tested. Use "solder wick" to remove defective component.

Parts List:

Data Sheets:

Vectron VCXO

MC145152P1 MC12 019P MC12015P

3

DC II. k DC SCRIP riON

.213 DIA. THRU 90° CSK. TO .062 DEEP FARSIOE (4 ) "d" HOLES.

.166 DIA. THRU 82° 2°CSK.TO .284 DIA. (4 ) "C* HOLES.

SEE DETAIL "A"(2 ) "D" HOLES DETAIL "A ”

.375 _ n .343

C U T - O U T FOR K IN GS-1 53 BNC

CONNECTOR

c

o

NOTES .125 THICK ALUM. 6 0 6 1 -T 6 REMOVE ALL BURRS AND SHARP EDGES.

FINISH ANP/QR h e a t tr e a tm e n t

YELLOW CNROMATE CONVERSION ALL OVER

SHOP NOIES: UNLESS OTHERWISE SPECIFIED

1. DIMENSIONS ARE IN INCHES 1. TOLERANCE ON DIUIN20NS

FRACTIONAL t 1 /C4 DECIMAL XX 1 .01 OCClMAL XXX i DOS ANGULAR t 0'30‘

J. SURFACE ROUGHNESS PER M IL-S IO -IO

4 NEMOVt BURKS AND fWtAK SHARP EDGES </64 MAX.

5 SCREW TilHlAOS PER M i l -$ r D -»6. a il Dimensions TO a p p l y

BEFORE PI*1ING OR CON- COA Ti;

**T ASUMUur

FULLCKSWlCAIlOK

A.E. ROGERS

ML ft PMOCUf

1 / 3 8

NORTHEAST RAOIO OBSERVATORY CORPORATION HAYSTACK OBSERVATORY

WESTFORD, MASSACHUSETTS

DRILLING PLAN FOR O UTPUT RATE SYNTHESIZER

FROMT PANEL

B B 2 3 0 B H

2 >-

15 > -

+ 5V (50m a)

+ 15V( 2 0 0 m a )

V LB A/ MK I I I CONTRO

GND189MHz

190.072MHz

16 o ) -

5MHz

SYN. SUB - MODULE

NOTES:

CHANGELETTER

DWNBY

CHK'DBY

APP'DBY

DATE D.C.N. 4c DESCRIPTION

17- ^ contrl

1 8 - ^ C ° N t r 2

DIVIDER SUB - MODULE

SELECTOR

19 CONTR3+ 5V

(100m a) -r 32

-r1 -2 -4 + 8 16

•21

* 21I______

MODCONTR.

i

VCXO

5 B IT - A 10 - B IT - N

MC1451521 KHz

PHASE/FREQ

DET

ROM

J

ELECTRONIC NOTES: UNLESS OTHERWISE NOTED:

RESISTORS:

CAPACITORS:

INOUCTORS:

USED ONDRAWN FOR:

A.E.ROCERSDATE:

1 / 8 8

DRAWN BY:

A.P.HEBERT 1 / 8 8

CHECKED BY:

SCALE NONE ^ I PROJECT

■ | H E n c i r ^ ^ i

SYNv-------OUTPUT

-fo F.P. MONITOR

— 21 ; ° 5 OUTPUT

" ( p P.P. MONITOR 21

NORTHEAST RADIO OBSERVATORY CORPORATION HAYSTACK OBSERVATORY

WESTFORD. MASSACHUSETTS

OUTPUT RATE SYNTHESIZER BLOCK DIAGRAM 2 WIDE MODULE

■■^ER/»Sil0ClJfP] USOSO

-54230

S003

DC*, t PC SCRIPT [ON

~ 3V. (TYP .)

16

VECTRON VCXO 1

189 MHz C O - 484V-8X

OIOOE SW MINI-CIRCUITS

P S W -I2 II2

8+ 15

16

vcxo 2190.512 MH2

5 +6dBm

317.4.

/ \

47 0 dBm ■A M /-------------- 1B9/I90.512 MHz

0.1 +1

"Hi— };MC12019P 0.1

'I

MC12015P + 5

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6X I'I 1 «•

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74HCT390N

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116 116

9 4•4- 25 7 -T - 25

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220K 0 47

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4 OP-27EN

10,2.4.3.6 28 3

PPL FREQ SYN

r 19 17 15 13 11 24 2120181614 12252223

63S081

23/23

63S081

10 28/70

I 8.11.12.13.14.15 X 8.11.12,13.14.15

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O U T P U T RATE SYNTHESIZER

>ER\OU TSYN TH Ih h i 2 30500-1

CHANGELETTER

OWNBY

CHK'OBY

APP'DBY

DATE D.C.N. ic DESCRIPTION

MC10H115P LINE RECEIVER

M C10H016P +5

H.F. INPUT °-

C3 C2 C1 -i- RATIO

0 0 0 10 0 1 20 1 0 40 1 1 81 0 0 16

DWG. LAST CHANGED 1 1 / 1 4 / 8 8

NOTES:1. All res is tors are 3 30 1 /8W excep t when

otherwise noted.2. All capac itors are O.OluF except when

otherwise noted.

ELECTRONIC NOTES:

UNLESS OTHERWISE NOTED:

RESISTORS:

CAPACITORS:

INDUCTORS:

USED ON

SCALE NONE

DRAWN FOR:A E.ROGERS

DRAWN BY:A P.HEBERT

CHECKED BY

1 | PROJECT

TrTTiitiBBj

1/88

NORTHEAST RADIO OBSERVATORY CORPORATION HAYSTACK OBSERVATORY

WESTFORD, MASSACHUSETTS

OUTPUT RATE SYNTHESIZER DIVIDER SUB - MODULE

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NOTES

d ffla i-w iu /a g MCAr..i” i m i u m

S«OP NO It 5: UNI ESS 0T>»£RWISC SPECIFIED

1. 0«MfNSJCrfiS AWE IN INCHES2. TOt FRANCE ON OiMCNSiONS

FRACTIONAL * 1/64 DECIMAL XX 1 .01 DECIMAL XXX i 005 ANGULAR t O'iO'

3. SURFACE ROUGHNfSS PER M lL -i l0 -» 0

4. RfMOvf B'JKRS AND BREAK SHARP 10CFS 1/t4 MAX.

V SCRf* lliHfADS PCR M lL-STP -96 AIL DIMENSIONS 10 APPLY

UCFORL PiATlriC OR CON- VtftStON COATING.

“ ,*’N ' “ a .e .r o c e r so.it

.1/08 NORTHEAST RADIO OBSERVATORY CORPORATION HAYSTACK OBSERVATORY

WESTFORO. M ASSACHUSETTS

W‘ ,H A P.HEBERT i/tecxuto ar

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DRILLING PLAN FOR OUTPUT RATE SYNTHESIZER DIVIDER

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NOTESSHOP NOTCS: UNLtSS OTV«CRwJ»LC SPlClflfO

1. OlMCriSKffS ARC IH INCMtS2. fOlCftAflCC OH bIMlNSJONS

FRACTIONAL ± 1/64 DCCIMAI XX i .01 DCCIMAL .XXX i OOS ANCUl AH i O'JO'

3. SUNTACC ROUCHt i£SS PI* MU - S ID-10

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V SCRfW 1HRCA0S PCR M U.-STD-*« ALL OlMfNSJOMS TO APPLY

PLATl^CCA II

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A.E.ROCERS

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M*ri_ t p*ucti%

NORTHEAST RAOIO OBSERVATORY CORPORATION HAYSTACK OBSERVATORY

WESTFORD. M ASSACHUSETTS

DRILLING PLAN FOR OU TPU T RATE SYNTHESIZER

[ C~

5423

0M00

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Page No. 111/25/88

PARTS LIST FROM DBASE FILE:PARTS.DBF

REF SU3MOD PART DESC MFR COST QTY TOTAL COST

MP RATE-A 1105-7521-003 SMC CABLE PLUG AEP 2.49 7 17. 43HP RATE-A 200458-1 BLOCK AMP 3 . 00 1 3.00MP RATE-A 200833-4 GUIDE PINS AMP 0.36 2 0.72MP RATE-A 200835-4 GUIDE SOCKETS AMP 0.48 2 0.96MP RATE-A 201142-2 SPRING AMP 0.05 10 0.50MP RATE-A 201143-5 COAXICON PIN AMP 2.70 3 8.10MP RATE-A 202394-2 HOOD AMP 1.04 1 1.04MP RATE-A 202422-1 POWER PINS AMP 0.50 4 2.00MP RATE-A 328666 FERRULE AMP 0.08 3 0.24SS RATE-A 542301002 F.P.SILK SCREEN NYES 100.00 1 100.00MS RATE-A 54230M001 FRONT PANEL HAYSTACK 100.00 1 100.00MS RATE-A 54230M009 BOX DRILLING HAYSTACK 20.00 1 20.00MS RATE-A C53306M013-2UA FRONT PANEL PREC.MACHINE 20.00 1 20.00MS RATE-A C53306M014-2UA PERFORATED COVER PREC.MACHINE 20.00 2 40.00MS RATE-A C53306M015-2UA MODULEREAR PANEL PREC.MACHINE 20.00 1 20.00MS RATE-A C53306M016 BAR SUPPORT PREC.MACHINE 10.CO 2 20.00MS RATE-A C53306M017 SIDE PLATE PREC.MACHINE 10.00 2 20.00MS RATE-A HAY45030 BOX WITH COVERS PREC.MACHINE 45.00 1 45.00MP RATE-DIV 1019-1511-000 SMC BULKHEAD AEP 1.77 5 8.85MP RATE-DIV 1250-003 FEED THRU ERIE 1.53 5 7.65Q RATE-DIV 2N3904 2N3904 1.00 1 1.00MS RATE-DIV 54230M008 BOX DRILLING HAYSTACK. 20.00 1 20.00MS RATE-DIV HAY45030 BOX WITH COVERS PREC.MACHINE 45.00 1 45.00U RATE-DIV MAR-7 AMP MINICIRCUITS 5.00 2 10.00U RATE-DIV MC10H016P 10016 MOTOROLA 1.00 3 3.00U RATE-DIV MC10H115P MC10115 MOTOROLA 1.00 1 1.00U RATE-DIV MC12019P 12019 MOTOROLA 10.00 1 10.00MP RATE-SYN 1019-1511-000 SMC BULKHEAD AE? 1.77 4 7.08MP RATE-SYN 1250-003 FEED THRU ERIE 1.53 2 3.06U RATE-SYN 63S081 PAL 1.00 2 2.00U RATE-SYN 74HCT14N 7414 1.00 1 1.00u RATE-SYN 74HCT390N 74390 1.00 2 2.00u RATE-SYN 75140P 75140 1.00 1 1.00MP RATE-SYN CO-484V-BX 190.512 MHZ VCXO VECTRON 100.00 1 100.00MP RATE-SYN CO-484V-BX 189 MHZ VCXO VECTRON 10.00 1 10.00U RATE-SYN MC12015P MC12015 MOTOROLA 1.00 1 1.00u RATE-SYN MC12019P MC12019 MOTOROLA 1.00 1 1.00u RATE-SYN MC145152P1 PPL FREQ SYN MOTOROLA 10.00 1 10.00u RATE-SYN OP-27EN OP-27 ANALOG DEV 10.00 1 10.00MP RATE-SYN PSW-1211 DIODE SWITCH MINICIRCUITS 24.00 1 24.00*** Total ***

697.63

1

m o t o r o l aMC145152-1

^Advance Information

X . 2

P A R A L L E L IN P U T PLL F R E Q U E N C Y S Y N TH E S IZ E R

device features "consist ** Para" e' 'nputs ' Thedivider, tw o o utput phase d e c ' e c ' ^ O b T o ' ” '” ’ Se,ec,3ble"''eference co unter and 6 -b it procram m *hfo 1 a program m able drvide -by-N

loop filter and V C O the M C1451S2 1 C 0 U n te r. W h e n co m bm ed w ith a

q ue n cy limit. For hicner V C O frpn 9 UP t0 Ihe dev,ce's fre-

dual m o d ulus p S e r l t ' 3 d ° W° ™ ef ° r 3M C U 5 1 5 2 - I . 56 US63 between the V C O and

M o d u s ': C o m r o l ^ ° u ! r u V T v T ^ a r ^ anCe ^ * * MCK5152-

s s i r been , m— —

• General Purpose A pplications-

C A T V T V Tu n in g A M / F M Radios S ca nn in g Receivers T w o -W a y Radios A m a te u r Racio

• L o w P o w e r C o nsum ption

• 3 0 to 9 0 V S u c o ly Range

• O n - or O ff -C h .p Reference Oscillator Operation• Lock D etect Signal

• D ual M odulus/Parallel P ro gram m ing

• 8 U ser-S electaole ■+• R Values ~ 8 f ->c- c ,20^3 • U 3 ’ 25°- 5 :2 - 1024. 1160.

• « - N Range = 3 to 1023. - A Range = 0 to 6^

• C h ip C om plexity: 8000 F £ T S or 2003 Equ.valen, Gates

high*performanccCMOS

L O W -P O W E R C O M P L E M E N T A R Y M O S

S I L I C O N G A T E

P A R A L L E L IN P U T P L ' F R E Q U E N C Y S Y N T H E S IZ E R

11 j l 2 j i j l ] 4 j l 5 j i 6 | l 7 j i 3 j ; 9 j 2 0 j-

NO N2 N4 N5 N7 N9

This d ocum ent c o m j.n s .n lo rm jn o n Cn a new n ,r,n c !-------- -------- ----------------------- ------------------------- -are 5u0i«*:t to change w itnout not.ce U ^ ce c ' 'Cat*ons and information herein

V o D ^ P m 3 Vss = Pm 2

N ote: N O th ro u g h N9. A O th rough A S and R A O th ro u g h R A 2 have PU||U0 res,stofs n o t s h o w n .

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MC145152-1

M A X IM U M RATIN G S* tVoitsgn Fcfe/enced to V 5 5 I

S>mbul Parameter Valua Unit

v DO OC Supply Voltage - 0 5 to ♦ 10 V

V . V Bv' Input o/ Output Voltage (O C or Transient) - 0 5 lo Vq q ♦ 0 5 V'in. 'out Input or Output Current lUC Of Transient!, p«r Ptn X 10 rnA

'DD - 'SS Supi#l/ Current. V ^ q or V 55 pms l 30 rnA

f o Power D^vpation, p*r Package! 500 m W^Stq Storage Temperature - 65 to t 160 •c

I *>aJ Ien.ptrature IB Second Solderingl 2U0 •c

IPowe* Dissipation Tampurature DentingPlast* • P” Pack sge - 12 mW/ *C from 66 *C 10 85 #C C « u r r K " I " Package N o derating

ELECTRICAL CHARACTERISTICS IVolUQai RtlirmcMl to V55I

Thu duvice contains circuitry to protect the inputs agamst dameQe due 10 high SUt»C voltages or electric liolds, however, it is advised that normal precautions be Uktm lo a</ord applications of any voltage higher Inan maximum ratvd voltages to lias high impcdance circuil. For proper operation if is recommended that V,„ and ^out ke COnsirainud lo tha ranga V S S S «V ,n or VOu|l s V 0 0

Unuw d mpuis must always ba tiad to an appropriate logic voltage level la 9 . euhor V ^ s or V q q I.

Characteristic Symbol V o o

-4 0 °C 25 *C 86 »CMm Maa Min Typ Maa Mm Man

Powe/ Supply Voltage Range v n n - 3 9 3 - 9 3 9Outpul Voltage 0 level ^O L 3 - 0 06 _ 0 001 0 06 _

V«n • 0 V or Vq0 5 - 005 - 0 001 0 06 006•out * 0 *A 9 - 0 06 - 0 001 006 - 00 6

1 lava! v O H 3 2 % - 2 % 2 y y j _ 2056 4 - 4 % 4 *JQ _ 4 96 _9 H 96 - 8 % 8 cS rt _ 8 95 _

Inpul Voyage O l eve* Vlt 3 - 0 9 _ 1 35 0 9 _v o o t -0 5 Vor V0 0 - 0 5 V s - 1 5 _ 2 25 1 5IA* Outputs Eacept O S C ^ , ! 9 - 2 7 - 4 06 2 7 _ 2 7

1 Laval VIM 3 2 1 - 2 I 1 66 _ 2 16 3 t - 35 2 75 _ 3 69 0 3 - 8 3 4 95 - 8 3 _

Output Currant - Modulus Conuoi -------- T ------V * u l -2 *V Souica 3 - 0 6 0 _ -0 5 0 - 1 6V0ul - 4 6 V S - o w - - 0 75 - 2 0 _V o u f « 5 V 9 - 1 50 - - 1 25 - 3 2 - - 0 80 _^out • 0 3 V Smk 'OL 3 1 JO - 1 10 5 0VOu, - 0 4 V 1 & 1 CO _ 1 70 8 0 ,

. VO U l* 0 i V 9 380 - 3 30 10 0 _ 2 10 _Output Currem - OiUf (X iip uti •o h

^o ul “ 2 7 V Souic* 3 - 0 44 - - 0 35 - * 0 _ - 0 22V 0U, - 4 # V 5 - 0 64 - -0 5 1 - 1 2 _ - 0 38V i - i l v 9 - 1 30 - - 1 00 - 2 0 - - 0 70 _

V o u i - O I V S « l 'O t 3 0 44 - 0 U5 1 0 _ 0 22V o u | - 0 « V 6 064 _ 0 51 \ 2 _ 0 36v ^ - o & v 9 1 30 - 1 uo 2 0 _ 0 70 _

Inpul Cu<iwnl - lin, OSC,„'s; . 9 - 1 50 - 1 10 125 _ 122

Inpul C u u «n l - Oirmi Inpuls.'ill. _ 9 - 0 3 - 000001 0 1 _ 1 0•it, 9 - -4 0 0 - -9 0 -2 0 0 _ - 170

Inpul Cupacitanca__ c -.n - - 10 - & 10 _ 10

Qu<«kc«fti Curieol / >00 3 - 800 - 200 ttLlO 1600v , „ . 0 V o . V D0 - 5 - 1*00 - 300 1200 _ 2400*i>ul “ 0 ^ A 9 “ If 00 “ 400 16u0 - 3200

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MC145152-1

S W IT C H IN G C H A R A C T E R IS T IC S i T a . ? v c . c , - M p H

Characteristic Output Rive Tirne Modulus Conuoi (figures 1 and 5l

Symbol

•fLHv OO

3

Min Typ

50Maa

115

Units

59

* 3020

6040

Output Fall Time. Modulus Contiol Ifigum i 1 and 5)«T H l 3 - 25 60

59

“ 1715

34

Outpul Hue jna f.l l !im «. 10. « v . « R if,g u n s 1 jra) 51« t i h 3 - 60 140 ns■1MI 5

9~ 40

3080

Propagation Delay Tune

•m to Modulus Control (figures 2 and 5l ‘PlM.'P H I

359

:554025

12580

ns

#R. #V with fR m Phase W uh fv figures 3 and 51'w ie i 3

59

25

2010

1006040

175

100ns

0 5 C I(V f^ (figure 41 'r «l 359

:2052

52

0 5

**

m m * : m \ m w 4 m ^ w

m M m mf b & l ' i r j t l - v L < v ■*’ r 1

11:1* i® if s /<$$$& ;•!!$#>»

iiikv-jLLLh

MC145152-1

G RAPH 1 - O S C ^ AN O f,n MAXIM UM FREQUENCY VERSUS T O TA L DIVIDE VALUE

GR APH 1A - V q q ■ 3 V GRAPH IB - V q d - S V

jr

I\3

j

GRAPH 1C - V D 0 * * v

GRAPH 2 - OSC,n AN D I*, M AXIM UM FREOUCNCY VERSUS TEM P IR ATU H E fOR SINE AN D SQUARE W AVE INPU1S

G R A P H 2A - T O T A L OIVIDE VALUE - 3. 4. OR 6 GRAPH 26 - T O TA L OIVIOE VALUE 2 6

r-:

3 y

\

9 V

\ V\

V3 V 4v i V1

i

•Data UNHUkJ "Tvp K :»r it not to be o«m1 tot d e v jn purposes. but i *<hJ*cJiioo ol Itm 1C t poHoimanco

’I; w ;

' !\V ;

K - : . .* * . v

MC145152-1

PIN D E S C R IP T IO N S

tin <P»n I I ~ ‘n p u l to the positive *<10# triggered * N and ♦ A counters. is typically derived from a dual modulus prescaler and ts A C coupled into Pin 1 fo r larger amplitude signals (standard C M O S logic levels! D C coupling niay be used

Vss ,Pln 2 > - C*cuil Ground

V q q I Pin 3) - Positive pow er supply

RAO. R A 1 , R A2 (Pina 4, 6. end 6 ) — These thre« inputs establish a code defining one of eight possible divide values for the total reference divider. The total reference divide values are es follows:

Reference Addreea Code

Total Divide Value

R A J RA1 RAO0 0 0 60 0 1 640 1 0 I2tt0 1 1 2141 0 0 &I21 0 1 10241 1 0 1160

1 204*

♦ r . # V I Pina 7 and 8) - Those phase detector outputs can be com bined enternally for a loop error signal

If frequency fy is greater than fR or if the phase of fy *s leading. then error information is provided by # y pulsing tow 4 r remains essentially high.

If the frequency of l y is less than » r or if the phese of fy 'S lagging, then error information is provided by pulsing tow # y remains essentially high

If the frequency of f y - f R and both ere m phase, then both ^ y end 4R remain high except for a smuU m inim um time penod when both pul^e low m phase.

M O D U L U S C O N T R O L (Pin 91 — Signal generated by the on chip control log*c circuitry lor controlling an extern*! dual modulus prescaler The modulus control level vwill be low at

the beginning of a count cycle end will rtm am low until the ♦ A counter has counted d o w n from its program m ed value

A t this time, m odulus control goes high and remains high until the ♦ N counter has counted the rest of the w ay d o w n from its program m ed value (N — A additional counts since both ♦ N and ♦ A are counting d o w n during the first portion o l the cycle). M odulus control is then set back lo w . the counters preset to their respective program m ed values, and the above sequence repealed This provides for a total pro­gramm able divide value (N t ) - N »P ♦ A where P and P ♦ 1 represent the dual m odulus prescaler divide values respec­tively for ruyh,eod-‘o*» m odulus control levels. N the number program m ed m io the ♦ N counter and A the num ber pro- gramm ed into the * A counter.

N IN P U T S (Pina through 20) — Th e N inputs provide trie data that is preset mto the ♦ N counter when it reaches the count of zero. NO is the least Significant digit and N9 is the most significant Pullup resistors ensure that inputs lelt open remain at a logic one and require only a S P S T sw itch to alter data to the lero state

A IN P U T S (Pins 23. 21. 22. 24. 25. 10) - Th e A inputs define the number of clock cycles of f ^ that requue a io^*c »e»o on the m odulus control output See page 0 for e x p i r a ­tion of dual m odulus prescaling The A inputs all have inter­nal pullup resistors that ensure that inputs lelt open will re mam at a log»c one

O S C o o t. O S C in (Pina 2® and 77) — These pms form an on chip reference oscillator w h en connected to terminals ol an external parallel resonant crystal Frequency setting capacitors ol appropriate value must be connected Irom O S C ,n lo g round »m j O S C q o , to g ro und O S C ,n nv»y ilso •eiv« <> input lot » n a »t«fn «lly garmfatad lalaram a j.gr.al T h u Mgnjl will lyptcally ba A C COupUid IO O S Cm . but lo< la.goi au.pl,tud* i.g n a lj U n n d j r d C M O S -lo g ic le-.olsl D C coupling m ay a lio be used In tfi# a x la .n .l rtile.enia n iu Ju no connaction i t toguusd to O S C ^ ,

L D (Pin 28) — lo c k d «t«c to r n g n »l High l*vol w h en loop if lockud IIh . IV o l i t in * p lu t* »n d lr»q u «n c y l P u l i . i low w h in loop il Out ol lock

PMASC LOCKED 1 0 0 ^ - IO W PASS FH .TI* DESIGN

I / S\ NCRt

^ N « 2C2

Attufmng A it very Ihtn

f l „ . * 1 9 i o ­n ic s

N O U E o m ..lm .. X I lla p lil t a l o l * . , . , l tlo , , , . ch H I 4 2 A c .p .c lto . C C I. th .n p f.c .4 l,o.n th . midpoint I . (pound to lurth ., *v • n'1 4H T ,“ , , l u * 101 C C •liuukl ba lu th tli»t th . CO ..... t.aquam y ol llua natwo.k doaa not aignll.cantly allact u N

DEFIN ITION S: N ■ Total Dtv^aioo Ratio in feedback loop

Ka - V d D '2 *

k v c o - c aa v v c o

lo< • typical dai.Qn ■ I J « / l Ol I, lat phaa. dalacto. Input!C “ >

6-7Gfi-77

,%f r * ' V . »» v •• * u • * * ? , v > v ; > v . \ i t • p . \ . y

' '•* Y»vP*<1;•'•«t'Ci'hK' ■'*•’!•'> ': "■ '»■

MC145152-1

SW ITCH IN G W AVEFORMS

AnyOutput

♦n. # v

11, m ph«M wth l¥

10%

- v Do

•Vss

' . ... •'•■ •! • ' •' ■;• ’ >

I ' . v .

l i . i . k i i i . O i i . . «

MC145152-1

. ' I n c . n■ -«' __I L

R«le/«mc*lOu.

f#*<36*Ch L • «».n * N» . ■ ■ . ' '

FIGURE 0PHASE D E TEC TO R O U T P U T W AVEFO R M S

n _____ f l nn _

~ U u

¥

u If ¥NOTE lh# Pq output »t»t* a •pp«o»ifTv»lely •goal to »lh* r VoQ °* V SS wt^ n *cttv« When not «cliv«. lh« out pvt 4 *mp«<jjr* « j n j t r«

voJIrf^a *1 irv»l JHH is OnlouiMfwd by th# k>w p*u» l.ittr C«P*CitOf

RECOM MENOEO FOR READING:

G»»dntw. Floyd M . Phss»/ock Techruquet iUKO/xt ibttonl New Yo*k. W.»#v lnl«»*c»«nc*. 1079Mtfn«i:*vviivch VAiJwn. SVrnyutocv Sy/1(A»S’/0O Umory end Design lu 'c o n j eebfort New Yoik. Witoy InUftoonca. I960 BUrtctwd. AU*n. P/as# locked loov* Appitcetron to Coherent A rc***' Dtfvyn New Yoik. Wiley inieiuw fK*. 1976 Et>*o. W'il'tffn F . frequency Syn ttusit t>v P h js t lo t k New Yo*k. Wilry lntu»>ti<jr>t.e I9dl

UlitCh I . D>yt*/ H i frequency Synthtmten thi-ory end Don^n Inglewood Clilts. N J. Prentice He*. 1903 MeiMi. Howard M . Dv%iyn of fh jse locked loop Circuits, wif/l iMpe'tmems Indmnpofci. Howeid W S*ms »nd Co . 1978 Kiniuy. HrffOkl. The H i Synth*%uer Cookbook blou R»d»j** Sumirwt PA. !*b Books. I'JbO

MC14 5152-1

DUAL M O D ULUS PRESCALING

The technique of dual m odulus prescaling is well estab­lished as a method ol achieving high performance frequency synthesizer operation at high frequencies Basically, the ap proach allows relatively low frequency program m able counters to be used as high frequency programmable counter* w ith speed capability ol seveial hundred M H z This is possible without the sacrifice m system resolution and per­formance that would otherwise result il a fixed Isingle modulus! divider was used lor the prescaler

In dual modulus prescalmg, the lower speed counters must be uniquely configured Special control logic is necessary lo select the divide value P or P ♦ 1 m the prescaler lor the required amount o l time (see m odulus control defini­tion) T he MCI45152- 1 contains this feature and can be used with a variety ol dual m odulus prescalers to allow speed, complexity and cost to be tailored to Itie system re­quirements Prescalers having P. P ♦ 1 divide values in the range of * 3 / » 4 to ♦ 6 4 / -6 5 can be controlled by the

MC145152 1Several dual m odulus prescaler approaches suitable for

use with the MC145152 1 Q'v«° ,n 7 lh e aPproaches range from the lo w cost ♦ 15/* 16. MC3393P device capable o* system s(>oeds m excess of 100 M H i to the M C 12000 series having capabilities extending to greater than 500 M H z Syniht*si/ei> featuring tr»e M C 14 b l5 2 I and dual modulus prescalmg are sh ow n m figures 8 and 9 lor two

typical applications

DESIGN GUIDELINES APPLICABLE TO TH E MC145152-1

The system total divide value IN|0la |l will be dictated by the application • e.

^ __ frequenc y tnto the prescalor___ _ n * P * A,0,a* " frequency into lhe phase detector

0 The penod of fvC0 divided by P must be greater thanthe sum of the tirnos.a Propagation delay through the dual modulus

prescalerb. Prescaler setup or release time relative to its

modulus control signalc Propagation time Irom fin to the modulus control

output lor the MC145152 1

A sometimes useful simplification in the M C 145152-1 pro­gram m ing code can be achieved by choosing tho values lor P ol 8 . 16. 32 or 64 fo r these cases, the desired value lot N|0 tai will result w hen N ,otd| in binary is used as the p<o- grarn code to lhe * N and * A counters treated in (ho foflcrw- ing manner:

A Assume the ♦ A counter contains " b " bits where 2b - P.

6 Always program all higher order * A counter bits above "b " to zero

C Assume the ♦ N counter and the * A counter (w ith all the higher order bits above "b " ignored) com bined in­to a smgie binary counter of 10 ♦ b bits m length. The M S B ol this "hypothetical" counter is to correspond to the M S B ol * N and the I SB is to correspond to t h e lS B o l * A The system divide value, N|0 iai. now results wtion the value ol N lolai m binary is used to progrjtn (he ’ N e w ” 10 ♦ b bit COuntei.

FIGURE 7 - HIGH FREQUENCY D U A L M O DULUS PM LSCAtEHS FOR USE W ITH THE MCI45I52 1

MC12COJ + 5/ + 6 440 M H i MmMC12011 + 8 / +■ 9 UO M ill MmMCI2013 + 10/ + 11 WO M H i MmM CI 2015 ■+■ J2/ + 33 225 M H i MmMC120IQ + 40/ 41 225 M H i MmMC 12017 64/ 65 225 M ill Mm

• MC 12018 ■f l?8/ 129 5?0 M H i MmMCXTM 15/ 16 140 M H i 1 VP

N is the number pro gram m ed *nto the * N counter. A is the number programmed into the - A counter P and P ♦ 1 are the tw o selectable divide ratios available in the two modulus prescalers To have a range of Ntoial values in se quence, the ♦ A counter is programm ed Irom zero through P - I lor e particular vaiuo N in the divide N counter N is then incremented to N * 1 and the * A is sequenced from lero through P - I again

There are minimum and m axim um values that can be achievod lor N ,ol4| These values are a function of P and the Size of the * N and * A counters lh e constraint N i A always applie* If A p r ^ - P - T then N rrw n fc P -1 Then N l0 ta l- m m - I P - II P ♦ A Of IP - II P *nce A n true to assume the value of zero.

N | o ta l-m a « • ? ♦ ^m a*

To maximize system frequency capability, the dual modulus prescaler's output must go Irom low to high alter each group ol P or P ♦ I input cycles The prescaler should divide by P when its m odulus control line is high and by P ♦ 1 wl*on us modulus control is low

for the maxim um frequency inio ll*e prescalef Ifvco nta*). the value used for P m ust be large enuugh such that

A lvCO max divided by P m ay r.ot exceed the frequency

capatnlity ol Pin I of the M C I45152 I

By using two devices. »ral dual modulus values are achievable

NOTE MC17UOO. MC12011 and MC12011 are pm equivalent M C I 2015, M C I A ) 16 and M CI AM / jru pm equivalent

6-80

1: ! •

t . ' i .v ( • ; 5 v

4 • /

••V. • ‘ •t •

f ,

MC145152-1

FIGURE I - A IR CR AFT N A V RECEIVER SYN TH ESIZER D E M O N S TR A TE S A IO W C O S T D U A L M O D U LU S S Y S TE M EM PLOYING THE MC145152 1

v OO

NOTE*1 ( « - 6 0 kHi. . R -6 4 . 22 0 M H i low ude ejection. N f O T A L - 1720 ~ 19192 Usetg 22 0 MHz lor tt* receiver I F damunitiatos how tlie choice ol I F value can «on»etime$ reduce the number ol * N t>?» that must be

piograrnrned Uim g the n*><e coonnon 21 4 M H i I F. would ie<|u*e Six iaU»e« liven lout « N progiammmg inputs

FIGURE 9 - SYN TH ESIZER FOR LA N D MOBILE RADIO UHF BANO COVERAG E D E M O N S TR A TE S USE OF THE MCI45152 1 IN S Y S TE M S OPLR ATIN G TO SEVERAL HUNDRED M H i

* 64/ - 65 Ow«l Modutut PitKaier

N O T IS1 N |0 | a l - N » W » A -3 ? 4 0 O »o 37600. N -5 0 7 to 587. A - O 106 I

2 »A - 12 5 k ill, • R - 1024 (code 10113 Hie p«atcalmg appioach can t « civusen lor iha application to enhance economy e g . tingle ch»p M CXW iP to appioximaieiy 100 MHt

MC 12011 or MC 12013 with dual hip Hup to a p ixo .-n jttly 250 M ill MC 120)1 04 MC 12013 with MC 101 7d to o*«i t/XJ M m

fi R 1

M C 14 5152-1

C R Y STA L O S C IL L A T O R C O N S ID E R A T IO N S

Th e following options may be considered to provide a reference frequency to Motorola's C M O S frequency syn ­thesizers Ihe most desirable is discussed lust

U S E O F A HYBRID C R Y S T A L O S C IL L A T O R

Commercially available tem perature''om pensafed crystal oscillators l lX C O s ) or crystal controlled data clock oscillators provide very stable reference frequencies A n oscillator capable o l smkmg and sourc>ng 5m) * A at C M O S logic levels may be direct or dc coupled to O S C ,n In general, the highest frequency capability is obtained utilizing a direct coupled squaie w a ve having a rail to rail (V q q to V $ § ) voltage swing II the oscillator does not have C M O S logic levels on the outputs, capacitive or ac coupling to O S C in m a y be u>ed 0 S C O u j. an unbuffered output, should be left floating

For additional information about T X C O s and data clock oscillators, please contact M otorola Inc . Com ponent Pio ducts. 2t>S3 N Edging ton St . Franklm Park. IL 60131. phone (3121 451-1000

D E S IG N AN OFF C H IP REFER EN CE

Th e user may design an off chip crystal oscillator using ICs specifically developed for crystal oscillator applications, such as the M C I2060. M C 12061. M C12560. or M C l2 b 6 l M E C L devices The reference signal from the M E C l device is ac coupled to 0S C,n For large am plitude signals (standard C M O S logic levefsl. d c coupling it used O S C ^ t . an unbul fered output, should be left floating In general. Ihe highest frequency capability is obtained w ith a direct coupled square w a v e having rail to-rail voltage sw ing

U S E O F THE O N -C M IP O S C IL L A T O R C IR C U IT R Y

Th e on chip amplifier (a digital inverter) along with an ap p/opnete crystal m ay be used to provide a reference source frequency A fundarnenUl mode crystal, parallel resnnanl at the desired operating lr«quer»cy. should bo connected as s h o w n in Figure A

For V f)0 « 5 V . the crystal should be specified lor a loading capacitance. Cj_. which does not exceed 32 pF lor frequencies to approximately 8 M H z . 20 pF lor frequencies in

the area ol 8 to )5 M H z, and 10 pF for higher frequencies These die guidelines that provide a reasonable com prom ise between 1C capacitance, drive capability, sw am ping vane tions m stray and 1C input/output capacitance, and realistic C i values 1 he shunt load capacitance. C l . presented across the crystal can be estimated to be

C ,nCn

CaCO

C l and C2

5 pF (see Figure Cl6 pF (see Figure C )5 pF (see Figure C)The crystal's holder capacitance

(see Figure 01 External capacitors (see Figure A )

The oscillator can be "trim m e d " on frequency by making a portion or all ol C ) variable Th e crystal and associated com ponents m ust be located as close as possible to the 0 S C ,n and 0 S C OU{ pms to m inimize distortion, stray capacitance, stray inductance, and startup stabilization time In some cases, stray capacitance should bo added to the

values lor C ,n and C 0 ut Power is dissipated m the effective series resistance ol the

crystal. R„. m Figure B The drive level specified Ihe crystal manufacturer is the m axim um stress that a crystal can withstand without dam age o« excessive shift in frequency. Rl m Figure A limits the dnve level The use ol R1 m ay noi Ihj necessary in some cases, i e R 1 - 0 ohm s

T o verify that the m axim um d c supply voltage does not overdrive the crystal, monitor Ihe o utput frequency as a function of voltage at O S C ^ i (Care should be taken to minimize loading I Th e frequency should increase very slightly as the dc supply voltago is increased A n overdriven crystal will docroase in Inrquency or becom e unstable with an increase m supply voltage The operating supply voltage must be reduced or R ) m usi he increased m value il Ihe over driven condition exists Th e user should note that the oscillator start up tune is proportional to Ihe value ol R l

Thro u gh the process ol supplying crystals lor use with C M O S inverters, m a n y crystal m anufacturers have developed expertise in C M O S oscillator design with crystals Discussions with such manufacturers can prove very hi.-lplul Soo Table A

TABLE A - PARTIAL LIST O f CR Y STAL M AN UFACTURERS

NAME ADDRESS PHONE

Urwied Stales Crystal Co*p C'ykie* Crytiai Slit A Co<u

3t'Ob McCail Si . Ft Worth. TX 10 10U0 Crystal Or . Ft Myers. F l Irju tj 51? N Mi>n St . OurVK CA 9?UjH

181/1 OJt 3013 IB 131 9 to 2U/J 17141 610 7BI0

R E C O M M E N D E D FOR R E A D IN G

Technical Note T N 24. Staiek C o rp

Techn*caf Note T N -7 . Statek C o rp

E Mafner. "Th e Piezoelectric Crystal Unit Definitions and M ethod ol Measurement". P/OC tE E i. Vof 07. N o 2. Feb . I u9

D Kem per. L Rosm e. ‘'Quart/ Crystals for Frequency Controf". tk rc tro -1 ethnology. Ju ne . 1‘jG9

P J O ttow itz. " A Guido to Crystal S elo cno n". l/cctronic O esyn. M ay. 1006

i

v. 'i - '.

. . . .• . a c V l d . i t i J i

MC145152-1

FIGURE A - PIERCE CR Y STAL OSCILLATO R CIRCUIT

FIGURE ( - EQUIVALEN T CRY STAL N {T W O R K S

B S >S c s

t[]l-O ~

Co

v*lu «l t ie Supplied 6» crytKI rninuUtlufkt Ip .'JIItl m o n iffl ClylK 'l

FIGURE C - PAR ASITIC CAP ACITAN CES OF T m E A M P llF ltR

--1-----II*?:c- i -fi

i2 fifn

t1 U TH T A B L E

*i

1

1 0 1 0 1 1 i ! i

1 0 I 1 |

1

0 1 . ’ 1

' ' 1

- 1 - i - 1

i---- I . 1

- H - H : . i. • 1

M O T O R O L A MC12015MC12016MC12017

lO W -P O W E R T W O -M O D U L U S P R E S P a , „The MC12015. MC12076 and M C 12017 C A L E R

scalers which will divide by 32 and 3? I n two' m odu^ s pre- fesoectivpiu :____ . y and 33, 40 and 41. anrt ^

S u p p ly Voltage 0 " # 771

MECL PLL C O M P O N E N T S

L O w - p o w e r

MC12019

O M PO N EN TS

2 3 / 1 2 9

'• P O W E R

M O D U L U SS C A L E R

M ECL PLL C O M P O N E N T S

L O W -P O W E R

T W O — M O D U L U S P R E S C A L E R

+ 20/21

m o d u l u s

P SU FFIXI A S T I C P A C .< A G E

C A S E 526

P SUFFIX P LA S TIC PACKAG i

C A SE 62S

D SU FFIX

P A C K A G E

O C X D I A G R A Mm a x i m u m r a t i n g s

,r>cteristicP o w e r S u p p ly y 0 |,age P|n ?

O p e ra tin g T e m p e ra tu re Rang

S to ra g e Te m p e ra tu re R angeB L O C K D I A G R A M

c h a r a c t e r i s t i c s CpntrolInputC ha ra c te ri s e S ym bo l

To g g le F req u e n cy (S in e w a v e tnputl

S u p p ly C u r re nt

C o n tro l Input H ij ( - 20)

C o n tro l Input Lov l~2t)l

O u tp u t V o lta g e S -O u tp u t

P L L R e spo n se Ti (M otes 1 an d 2

r»nte«»d to b* Ser^wn .1 osing apoi.eo to pm S.

'■3 a jourc* of regulate*}modulo*