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EL 511 VLSI Design 1 EL 511 VLSI Design Instructor: Mazad S. Zaveri Faculty Block – 4, Room 4206 Email: [email protected] http://intranet.daiict.ac.in/~mazad_zaveri/

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  • EL 511 VLSI Design1

    EL 511 VLSI Design

    Instructor: Mazad S. Zaveri

    Faculty Block 4, Room 4206Email: [email protected]

    http://intranet.daiict.ac.in/~mazad_zaveri/

  • EL 511 VLSI Design2

    N-type substrate (or body) In P-channel MOSFET

    Depending on the applied gate-voltage MOS Cap could exhibit the

    following conditions: Flat band (VG = 0) Accumulation (VG > 0) Depletion (VG < 0) Onset of inversion (VG = VT) Inversion (VG < VT)

    VLSI systems work at 0 to +ve Volts. How do we give ve voltages to P-MOSFET?

    MOS Capacitor with N-type substrate - Under Various Bias Conditions

    0VT

    Applied Volt. VG

    Inversion Depletion Accumulation

    Onset of Inversion Flat band

    (VG < 0)

    (VG < 0)

  • EL 511 VLSI Design3

    Ei (surface)

    Ei (bulk)

    Equations (according to Pierrets book) Numerical Examples

    Consider NA = 1018 cm-3 What is surface potential at inversion?

    Consider ND = 1018 cm-3 What is surface potential at inversion?

    Draw the approx. band diagram ?

    [ ][ ]

    1 ( ) ( )

    1 ( ) ( )

    ln

    ln

    2

    S i i

    F i F

    AF

    i

    DF

    i

    S F

    E bulk E surfaceq

    E bulk E bulkq

    NkTq n

    NkTq n

    =

    = = =

    = At the depletion to inversion transition point

    P-type semiconductor

    N-type semiconductor

  • EL 511 VLSI Design4

    Equations (from Pierret)

    1/ 2

    0

    1/ 2

    0max

    0

    2

    2 2

    SS

    A

    SF

    A

    A

    S

    KWqN

    KWqN

    qN WK

    = =

    =E

  • EL 511 VLSI Design5

    MOS Cap: P-type substrate Similar in functioning to the n-type substrate MOS Cap

    But the relation of applied gate voltage to the various exhibited MOS Cap conditions are reversed

    0 VT

    Applied Volt. VG

    InversionDepletionAccumulationOnset of InversionFlat band

  • EL 511 VLSI Design6

    P-type substrate: Flat Band Condition When VG = 0 (No applied

    bias) Metal Fermi-level and substrate

    Fermi-level are aligned No band bending

    Assuming that the workfunction of metal and semiconductor are equal (ideal condition)

    The characteristics of the substrate (concentration of holes) is the same everywhere (in the bulk and near the surface)

    Block charge diagram No generated charges

    Surface

    Bulk

  • EL 511 VLSI Design7

    P-type substrate: Accumulation When VG

  • EL 511 VLSI Design8

    P-type substrate: Depletion

    When VT> VG >0 Relatively

    Metal Fermi-level goes down (relative to substrate EF) Band bending will be such that

    Ei (surface) moves closer to EF The concentration of holes decreases at/near the

    surface How? Holes near the surface are repelled (due to applied +ve

    bias on gate); i.e. electron from bulk will be attracted, and will fill up missing bonds (holes) at acceptor atoms

    Hence, these acceptor atoms become -ve charged ionized acceptor atoms (fixed charges), and create a depletion region.

    Block charge diagram +ve charge on the gate

    Leads to a -ve charge (ionized acceptors in depletion region) near the surface

    arpitUnderline

    arpitUnderline

    arpitUnderline

  • EL 511 VLSI Design9

    P-type substrate: Onset of Inversion and Inversion When VG >= VT (VG = VT at Onset of Inversion)

    Relatively Metal Fermi-level continues to go down (relatively to substrate

    EF) Band continue to bend (same direction as VT> VG >0)

    Ei (surface) crosses the EF level, and continues to move down Hole concentration continues to decrease near the surface Electron concentration continues to increase near the surface

    When Ei(surface) = EF, we have p(surface) = n(surface) = ni When Ei(surface) < EF, we have n(surface) > p(surface), and

    n(surface) < p(bulk) When EF - Ei(surface) = Ei(bulk) - EF, we have inversion of the

    surface We have n(surface) = p(bulk), majority carriers at surface are

    now electrons Also, in other words, Ei(bulk) - Ei(surface) = 2[Ei(bulk)- EF], at

    inversion Block charge diagram

    More +ve charge on the gate Leads to a -ve charge (ionized acceptors in depletion region) near

    the surface Depletion region width grows (assume max. at inversion)

    Leads to increase in -ve charged electrons at surface

  • EL 511 VLSI Design10

    MOS Cap Structure: Summary

    Depending on the applied gate voltage MOS Cap exhibits:

    Accumulation Depletion Inversion

  • EL 511 VLSI Design11

    NMOS transistor aka N-Channel MOSFET Cut-off Region

    When 0

  • EL 511 VLSI Design12

    Ideal IV Equations (NMOS)

    Linear or

    Resistive or

    Un-saturated

    Saturation

  • EL 511 VLSI Design13

    Ideal IV Characteristics NMOS What is the meaning of this

    plot? Vds

    DC (fine) sweep from 0 to 1.8V Vgs

    DC (step) sweep 0.6, 0.9, 1.2, 1.5, 1.8

    Where are linear and saturation regions in the plot? Boundary condition

    Vds >= Vgs-Vt Can we approx verify this

    graph, with the given equations?

    Can we find the resistance of the transistor in linear/resistive region from this plot?


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