week 5 - university of waterloopami.uwaterloo.ca/~basir/ece124/week5-2.pdf · 5-variable function...

WEEK 5.2

ECE124 Digital Circuits and Systems

5-Variable Function


Factoring as Disjoint Decomposition

a b c d e F


0

1

2

3

' . '. ' . '. '

'. '. '. .

'. . ' . '.

. . ' . .

G c d e c d e

G c d e c d e

G c d e c d e

G c d e c d e

0 1 2 3.(').('..').(')()HGbGababGaGba

G

c d e

H

Multiplicity?

a b


Multiplicity? 4. Therefore we can encode G using two lines: x and y.

0 1 2 3.( ') .( '. . ') .( ') ( )H G b G a b a b G a G b a

G

c d e

H

x

y

a b


0

1

2

3

'. '. ' . '. ' '. '

'. '. '. . '.

'. . ' . '. . ' '.

. . ' . . .

G c d e cd e d e

G c d e c de c e

G c de cd e de d e

G cde cde cd

00 01 11 10

0 0 0 0 1

1 0 1 1 1

c

de

00 01 11 10

0 0 1 1 0

1 0 0 1 1

c

de

x=de’+ce

0

1

2

3

00 '. '. ' . '. '

01 '. '. '. .

10 '. . ' . '.

11 . . ' . .

G xy c d e cd e

G xy c d e c de

G xy c de cd e

G xy cde cde

y=cd+c’e

H = (x '.y ').(b ')+ (x 'y).(a '.b+ a.b ')+ (x.y ').(a ')+ (x.y)(b+ a)

0 1 2 3.( ') .( '. . ') .( ') ( )H G b G a b a b G a G b a


(10101)

. ' 0 1 1

' 0 0 0

( '. ').( ') ( ' ).( '. . ') ( . ').( ') ( . )( )

0 0 (1).(0) 0 0

abcde

x de ce

y cd ce

H x y b xy ab ab xy a xy b a

H


4-to-1 from 2-to-1


f1=a’.f(a=0,b,c)=b.c f2=a.f(a=1,b,c)=b+c


𝑓 = 𝑎′. 𝑏′𝑐 + 𝑐′𝑏′ + 𝑎. 𝑐

𝑓 = 𝑐(𝑎 + 𝑎′𝑏′) + 𝑐′𝑏′

Call it c-mux

0 1

c

b’

a+a’b’

Now e can add an a-mux

𝑓 = 𝑐(𝑎 + 𝑎′𝑏′) + 𝑐′𝑏′

𝑓 = 𝑐(𝑎(1) + 𝑎′(𝑏′)) + 𝑐′𝑏′

0 1

a

b’ 0 1

c

b’

1


Sequential circuits

Circuits with simple logic gates are known as combinational circuits. These are the types of circuits we have talked about up to this point in the course.

We can include storage elements into a circuit that act like memory and store a system state. Now, we have a sequential circuit!

inputs outputscombinatorial

circuit

memory

elements

state

Outputs are then a function of both the current circuit inputs and the system state (i.e., what happened in the circuit before… history is present!).


Types of sequential circuits

There are two main types of sequential circuits. The classification depends on when things occur in time.

Synchronous sequential circuits:

circuit behavior is determined from the knowledge of signal values at discrete instances in time.

Asynchronous sequential circuits:

circuit behavior is determined by signals at any instant in time and the order in which input signals change.


Clock signals

Clock signals are particularly important to understand for designing synchronous sequential circuits (aka clocked sequential circuits).

A clock signal is used to control the behavior of a circuit at discrete instances in time; it does this by controlling/determining how and when memory elements can change their outputs.

inputs outputscombinatorial

circuit

storage

elements

state

clock/

control

clock/

control


Clock signals

Clock signals are periodic signals (so they have a frequency and a period).

We can use clocks to control when things happen in a circuit because their transitions from 0->1 and 1->0 occur at discrete instances in time.

The 0 -> 1 transition is often called the rising edge of the clock.

The 1 -> 0 transition is often called the falling edge of the clock.

clock1

0

rising edge (0->1

transition)

falling edge (1->0

transition)


Storage Elements

There are two types of storage elements: 1) Latches and 2) Flip-flops.


Latches

Latches are one type of storage element.

They are level sensitive storage elements – what does level sensitive mean?

Level sensitive mean that latches operate (i.e., they perform their function) when a control signal is at either logic level 0 or 1 and not at logic transitions from 0->1 or 1->0.

Latches are not necessarily useful for clocked sequential circuits, but they are useful for synchronous sequential circuits.

They also help to understand the behaviour of flip-flops (another type of storage element which is useful for clocked sequential circuits).

There are different types of latches.


SR latch (NOR implementation) (1)

Consider the following circuit built from two NOR gates. Note the “cross-coupled” gates that introduce a combinational loop into the circuit.

Q

!Q

R (reset)

S (set)


SR latch (NOR implementation) (2)

In general, the outputs are complements of each other (this is why they are labeled Q and !Q):

When S=1, R=0 the output is Q=1, !Q=0 and the circuit in the set state.

When S=0, R=1 the output is Q=0, !Q=1 and the circuit in the reset state.

S=1 (active high) implies set (Q=1) and R=1 (active high) implies reset (Q=0).

When S=0, R=0 the output holds at its previous value (storage).

Exception: When S=1, R=1 the output is Q=!Q=0 which is not desirable and we should avoid this combination of inputs. We always want to complementation property at the outputs.


S’R’ latch (NAND implementation) (1)

Consider the following circuit build from 2 NAND gates. Again, note the cross-coupled gates and the combinational loop.

Q

!Q

S (set)

R (reset)


S’R’ latch (NAND implementation) (2)

In general, the outputs are complements of each other (this is why they are labeled Q and !Q):

When S=0, R=1 the output is Q=1, !Q=0 and the circuit in the set state.

When S=1, R=0 the output is Q=0, !Q=1 and the circuit in the reset state.

S=0 (active low) implies set (Q=1) and R=0 (active low) implies reset (Q=0).

When S=1, R=1 the output holds at its previous value (storage).

Exception: When S=0, R=0 the output is Q=!Q=1 which is not desirable so we want to avoid this combination of inputs since we always want the complementation property at the outputs.

So, it works similar to the NOR implementation, but the input values are reversed for each of the different cases.


Gated latches (1)

We can add an additional control input that acts as an enable signal. The purpose of the enable signal is to control whether or not the latch functions (vs. just “holding its current state”).

Consider adding some extra NAND gates in front of an S’R’ Latch.

Q

!Q

S

R

C


Gated latches (2)

Q

!Q

S

R

C

When the control input C=0 the inputs to the latch are both 1 which puts the S’R’ latch into its hold state. So, the latch outputs will not change regardless of the S and R values.


Gated latches (3)

Q

!Q

S

R

C

When the control input C=1 the S and R inputs will reach the latch and we can analyze the behavior.

The NAND gates at the input to the latch result in active high inputs:

S=1 (and R=0) causes a set (Q=1).

R=1 (and S=0) causes a reset (Q=0).


D latch

We sometimes had an undesirable situation where we cannot determine the latch output (both outputs had same value).

To avoid this situation we can construct a latch where S and R can never be the same value.

Q

!Q

D

C

We still have the set and reset states. Notice that because of the control signal, we still have a hold state too. But, we avoid the undesirable situation in which the outputs of the latch are the same (and break the complementation property).


Schematic symbols (1)

S Q

R

S Q

R

C

Latches with active high inputs; i.e., we set when S=1 (and R=0) and we reset with R=1 (and S=0).

Latches with active low inputs; i.e., we set when S=0 (and R=1) and we reset with R=0 (and S=1).

S Q

R

S Q

R

C


Schematic symbols (2)

For a D Latch, the control input is required, since it is via the control input that we have the hold state.

D Q

C


Potential issues with latches

Latches do not allow for precise control because they are level sensitive; e.g., consider a d-latch with a clock signal connected to the control input – the output of the latch can change anytime while the clock is high.

This creates an interval in time over which the state, or output, of the memory element can change rather that an instant in time at which the state, or output, of the memory element can change.

It would be better to only allow the output to change when the clock edge makes a transition from 0 -> 1 (rising edge triggering) or 1 -> 0 (falling edge triggering). This gives even more precise control!


Flip-flops

Recall that latches are level sensitive devices and do not give precise control with respect to when their outputs change.

We want changes only in the instance of time when some clock signal makes a transition from either 0 -> 1 (rising edge triggering) or 1 -> 0 (falling edge triggering).

Flip-flops are storage elements that are edge-triggered.


What does triggering mean?

Response to positive level (a latch) – large window of time for output to change.

Positive Edge Triggering. The input to the flip-flop just before the clock changes from 0 -> 1 causes the output to change just after the clock changes from 0 -> 1.

Negative Edge Triggering. The input to the flip-flop just before the clock changes from 1 -> 0 causes the output to change just after the clock changes from 1 -> 0.


Master-slave DFF (negative edge-triggered)

Consider a circuit constructed with 2, D-Latches (one master and one slave):

D Q

C

D Q

C

D Q

CLOCK

D Latch

(master)

D Latch

(slave)Y

While CLK=1, Y will follow input D via the master latch, but Q will not follow Y (it is in hold state) and will hold its current value.

When CLK=0 (at the moment of change), Y will be disconnected from D and will hold its current value. Q will follow Y via the master latch.

The effect is that the value of D just prior to the falling edge of the clock will get “transferred” to the output Q just after the falling edge of the clock.


Master-slave DFF (positive edge triggered)

We can make a positive edge triggered DFF simply by changing the inversion of the clock signal

Output of master latch, Y, follows D when clock is low (slave in hold).

Output of slave latch, Q, follows Y when clock is high (master in hold).

D Q

C

D Q

C

D Q

CLOCK

D Latch

(master)

D Latch

(slave)Y


Schematic symbols for DFF

D Q

D Q

Positive edge-triggered:

Negative edge-triggered:


Sets, resets and enables

Flip-flops can have additional control signals that will force the output Q to a known value.

An asynchronous signal that forces Q=1 is called an asynchronous set or preset.

The output will remain 1 as long as the set/preset input is active (changes in D and CLK are ignored).

An asynchronous signal that forces Q=0 is called an asynchronous clear or reset.

The output will remain 0 as long as the clear/reset input is active (changes in D and CLK are ignored).

A signal that prevents the clock from causing changes in Q according to D is called a clock enable.


Additional schematic DFF symbols

Active low set and reset signals.

Active high set and reset signals.

D Q

R

S

D Q

R

S


Characteristic tables and equations for DFFs

We can describe the behavior of a flip-flop via a characteristic table. The characteristic table shows what the next flip-flop output value will be given the current flip-flop input value after the clock makes its active edge transition.

We can also write this as a characteristic equation:


Toggle flip-flops (TFF)

Another type of flip-flop that has a different behavior when compared to a DFF.

Symbol for a positive edge-triggered TFF:

T Q

T Q

Symbol for a negative edge-triggered TFF:


Characteristic tables and equations for TFFs

The characteristic table for the TFF:

The characteristic equation for the TFF:

So with a TFF, the output toggles (or flips) its value if the input is T=1, otherwise it remains the same.


Making a TFF from a DFF

D QT

Q

CLOCK

T Q

We can actually build a TFF using a DFF and a 2-input XOR gate.


JK flip-flops (JKFF)

J Q

K

Another type of flip-flop that has different behavior compared to a DFF or to a TFF.

Positive edge-triggered JKFF:

J Q

K

Negative edge-triggered JKFF:


Characteristic tables and equations for JKFFs

The characteristic table for the JKFF:

We can derive the characteristic equation for the JKFF (I find it easy to explain via a K-Map):

JK

Q(t)

0

1

00 01 11 10

0

1

0

0

1

1

1

0


Making a JKFF from a DFF

We can actually build a JKFF using a DFF and some other gates.

J Q

K

D Q

J

Q

CLOCKK


Timing analysis with flip-flops

There are some important things to understand when we go to actually make and implement a circuit with flip-flops.

In reality, it takes time for gates to change their output values according to the input values – i.e., there are propagation delays due to resistance, capacitance, etc.

Changes in flip-flop outputs occur at the active clock edge.

There are three timing parameters that are especially important:

Setup Time (TSU).

Hold Time (TH).

Clock-To-Output Time (TCO).


Definitions for timing analysis of flip-flops

Setup Time (TSU):

The setup time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) PRIOR to the arrival of the active clock edge.

Hold Time (TH):

The hold time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) AFTER the arrival of the active clock edge.

Clock-To-Output (TCO):

The clock-to-output time of a flip-flop is the amount of time it takes for the output to become stable (at its new value) AFTER the arrival of the active clock edge.


Comments

If these timing specifications are not met, then it is possible that the flip-flop will not behave as expected.

That is, if we don’t observe setup and hold times at the data inputs, then our output might not change as expected.

That is, if we don’t wait long enough (clock-to-output time) for the output to change, then we might use an incorrect value.

If we violate any of these timing parameters, then we have a timing violation.

These timing parameters (as we will see later) have an influence on how fast we can clock a circuit.


Illustration of timing parameters (for a DFF)

CLOCK

D

Q

TSU TH

D should not change in this interval

TCO

Q not stable (trustworthy) until this interval ends

D Q

week 5 - university of waterloopami.uwaterloo.ca/~basir/ece124/week5-2.pdf · 5-variable function...

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