Work in Progress --- Not for Publication26 April 2001 1

Interconnect Working GroupInterconnect Working Group

ITRS 2001

27 April 2001

Grenoble

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Attendees• Hans Barth - Europe

• Joaquin Torres - Europe

• Hyun Chul Sohn - Korea

• Ahihiko Ohsaki - Japan

• R Aoki - Japan

• C Case - US

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Agenda• Section updates:

–Conductors –Dielectrics –Planarizaation –Etch –Reliability –System and performance –SOC

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Agenda contd.• Crosscut updates:

– Modeling and simulations – Defect reduction – Metrology – ESH – Design

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Nucleation/Conductors update• Expanded description of ALD

• Spin etch planarization (CEP) (metal)

• Cu ECD combined with planarization

• Need for novel/potential cleans– Conductors, etch, dielectrics and planarization

• Reconciliation of new node info with wiring data

Work in Progress --- Not for Publication26 April 2001 6

Wiring updates

2001 2002 2003 2004 2005 2006 2007 2008 2010 2013 2016

Number of metal levels 7 7–8 8 8 8–9 9 9–10 10Global wiring WIRE A/R 2.4 2.5 2.6 2.7 2.7 2.8 2.9 3.0Barrier thickness nm based on 2.2 14 13 12 11 10 7 5 4

Local wiring pitch (nm) 405 365 330 295 265 185 130 95Intermediate wiring pitch (nm) 520 465 420 375 340 240 165 115Minimum global wiring pitch (nm) 850 765 690 620 560 390 275 190# local levels 2 2 2 2 2 2 2 2# intermediate levels 3 3 3 3 3 3 3 3# global levels 2 3 3 3 4 4 5 5Chip size cmt - hi perf MPU at ramp 3.40 3.56 3.72 3.90 4.08 4.67 5.36 6.14

Area coverage local 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33Area coverage intermediate 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33Area coveage global 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33Max interconnect length m/cm2 4310 5231 5792 6474 7759 11077 17077 24240Interconnect length in m (total for chip) 14654 18624 21546 25249 31659 51730 91532 148835

#levels*10E5*areacoverage/fullpitch(nm)repeat above for each type of level

FITS/m based on 5 FITS 0.34 0.27 0.23 0.20 0.16 0.10 0.05 0.03

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Nucleation/Conductors update• Expanded treatment of opto/electrical on chip

materials needs– in System and Performance sections

• Add doped Cu conductors– unknown impact on resistivity vs dimension– allows higher current density, accommodates higher wire

temp at local/inter levels

• Changed Cu resistivity for global wires (2.2 cm)

• New intermediate/local wiring Cu conductivity

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Dielectrics update• To address confusion on definition of “effective” k

– add text that effective k includes all integration needs including cap, etch stops, hard masks

• Adding “physical” metrics on mechanical properties of porous materials from models so that text can support issues of using these weak materials

• options such as composites, fiber reinforcement included in text

• May add high k Tech Requirement “k” metric – material must meet temperature budget

– still under consideration

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Dielectrics update• Add thermal properties

– still under discussion

• Model effective k calculation that also includes crosstalk – with and without trench etch stop

• Photoresist poisoning of low k materials - text

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Planarization update• More detailed discussion of CEP• Schematic and calculation for new

dishing/erosion/thinning metrics• Porous low k will require either alternative

planarization or stopping layer/structural enhancements to be compatible with existing planarization techniques - text

• Addressing planarization of thick metal for inductors

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Etch update• New Potential Solutions figure

– Distinguished by level and function– MRAM, FERAM– passives – De-emphasize HDP

• Etch is now driven by new materials and integration schemes

• Etch section - includes potential solutions with and without etch stops

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System and Performance update• Including resistivity increase (change) in

performance calculations

• Agreement on current density - all regions agree 04/01

• Include Raphael calculation and schematic for low k scenarios - for effective k and crosstalk

• Include in appendix some references on process variability effect on performance

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SOC update• Expanded detail on passives - create new

technology requirements– thick metal thickness for inductors – Fe cores – Resistors – Capacitance per unit area metric - fF/micron2

– Q factor

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Cross Thrust ESH• Chemicals, Materials and Equipment Management

– add reuse and recycle for CMP and ECD– ULV chemical dispense

• Climate Change Mitigation– add PFC POU abatement

• Workplace Protection

– address ClF3, VOC from low k and POU abatement, PM schemes for hazardous chambers

• Resource Conservation– Alternative clean gases– Cu waste (CMP plus ECD) and water reclaim

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Cross Thrust Metrology• Dielectrics

– porosity - size, distribution etc• max pore diameter 10% of spacing

• average pore size 5% +- 3 sigma of spacing

– k anisotropy -edge effects, - text

• Interfacial issues - contact to high k - text

• Conductors – voids - adding metric similar to dielectric but using metal half pitch

– Cu ECD bath metrology - CVS, etc.

• Planarization– which of the new Technology Requirements need new metrology? – Cross section feature volume per unit length

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Cross Thrust Metrology• Etch

– 3DCD• sidewall CD, possibly post planarization

• trench bottom profile

– diagnostics for run to run stability

– end point for low k (etch stops)

– High A/R contacts (DRAM) - • 3DCD

• endpoint for contact

• SoC – High k measurements - thickness, composition, k non-uniformity

– R and L measurements - thick metal thickness

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Cross Thrust Design• Crosstalk metric - also Modeling

• Review the resistivity vs wiring level quandry - also modeling

• Capacitance per unit area metric - fF/micron2

• Q factor

Work in Progress --- Not for Publication26 April 2001 18

Cross Thrust Modeling• Crosstalk metric

• Review the resistivity vs wiring level quandry - also modeling

• Capacitance per unit area metric - fF/micron2

• Q factor

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Cross Thrust PIDS

• Al on Cu for bonding pad

• Joe Adam had these problems

• Operating temp for harsh environments

• MEMS and interconnect

• Embedded epi in interconnect - possibly compound semi for emitter/receiver pairs

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Cross Thrust Modeling• Thermomechanical simulations issues

request to modeling

• Thermal cycling in operation for multi-level structures

• Stress voiding

• Crosstalk at cell and higher effects, steadystate and operating

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Difficult ChallengesDifficult Challenges

• New materials• Reliability• Process integration• Dimensional control• Interconnect

process with low/no device impact

• New materials and size effects

• Process complexity • 3DCD• Aspect ratios for fill

and etch• Solutions beyond

copper and low

Long termNear term

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Remaining issues• Adequate treatment of Cu resistivity

impacts

• Need to agree on number of interconnect levels with respect to global wiring

• Proposed structural changes to potential solutions table