xilinx logicore animation and connect6 game development on remote fpga student - stephen conway...
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Xilinx LogiCore Animation and Connect6 game development on
Remote FPGAStudent - Stephen Conway
Supervisor - Fearghal MorganCo-Supervisor – Martin Glavin
Overview
LogiCore Background & Generation
Goals (Phase 1 & Phase 2) Phase 1: Animate Xilinx LogiCore Modules Phase 2: Implement Connect6 game on Remote
FPGA lab
Tasks Completed (Phase 1)
Future Work (Phase 2)
Summary
LogiCore Background
PlanAhead Design & Analysis Suite.
IP Core
IP Catalogue
Core Generation
LogiCore Generation
Goals Phase 1: Animate Xilinx LogiCore Modules
Learn and apply Xilinx LogiCore IP block generator.
Simulate and implement basic IP block apps on local FPGA.
Implement and animate IP blocks on Remote FPGA Lab.
Integrate RAM IP Core into automated client application GUI (separately under development).
Use the RFL to shadow the animation of internal RAM contents
Phase 2: Implement Connect6 game on Remote FPGA lab
Functionally correct, high performance, winning player on RFL
UA
RT
UA
RT
PC FPGA
Referee (P1)
Maintain a view of game. (Arrays)
Processor (P2)
Tasks Completed (Phase 1)
Generation. (Add_Sub, FIFO, Multiplier)
I/O Width
Chip Enable
Flags/Warnings
Integration.
Tasks Completed (Phase 1)Simulation. (Testbench)
Local Implementation. (Add_Sub)
BitStream
Tasks Completed (Phase 1)Implementation on FPGA Lab
RAM_IP Core
Interactive GUI.File I/O.
Internal Memory Display
Future Tasks (Phase 2)
Review Connect6 Instructions.
Download/Run referee. (Player 1)
Connect Referee to another PC via Serial Port.
Implement several Player 2 variations. (Next Slide)
PC-based ‘C’ program. (enables full understanding of connect6 and referee operation)
Develop an embedded Microblaze (logiCore IP block) processor. / UART system and port ‘C’ code to run on Microblaze.
Future Tasks (Phase 2)
UA
RT
UA
RT
PC FPGA
Referee (P1)
‘C’ Code
MicroBlaze (P2)
Future Tasks (Phase 2)
Perform a full digital design of the connect6 game player (FSM, memory, etc)
Integrate connect6 game with client app GUI (separately under development)
FPGA
Summary
LogiCore Background & Generation
Goals (Phase 1 & Phase 2) Phase 1: Animate Xilinx LogiCore Modules Phase 2: Implement Connect6 game on Remote
FPGA lab
Tasks Completed (Phase 1)
Future Work (Phase 2)
Questions?