yms sm07 lores
DESCRIPTION
ÂTRANSCRIPT
yms yieldmanagementsolutions
www.kla-tencor.com/ymsmagazineSummer 2007 | Issue 2
The 45nm Innovation ChallengeThis issue of YMS magazine features a range of articles related to 45nm inspection and metrology, from the latest in mask inspection technology to unique cases involving the application of specialized metrology wafers
Article TopicsDefect ManagementMetrologyFab EconomicsMaskData StorageProduct News
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Featured articles
A New Approach to Identify Large, Yield Impacting Defects on Polished Si Wafers Hynix Semiconductor Corporation and KLA-Tencor Corporation
Etch Process Monitoring by Electron Beam Wafer Inspection Powerchip Semiconductor and KLA-Tencor Corporation
Enabling Manufacturing Productivity Improvement and Test Wafer Cost Reduction KLA-Tencor Corporation
Wafer-Level Metrology Expands Process Applications at 45nm KLA-Tencor Corporation
Spectroscopic Ellipsometry Film Metrology Braces for 45nm and Beyond KLA-Tencor Corporation
Reducing Cycle Time Has Many Benefits KLA-Tencor Corporation
Field Results from 45nm Die-to-Database Reticle Inspection Toppan Printing Co., Ltd, Advanced Mask Technology Center GmbH & Co and KLA-Tencor Corporation
Applications of a Laser-Assisted Defect Detection System for CMP Slurry Development in Rigid Disk Polishing KLA-Tencor Corporation
Product News
Contents
3
Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions www.kla-tencor.com/ymsmagazine
For literature requests, visit: www.kla-tencor.com/products
©2007 KLA-Tencor Corporation. All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation. Products in this document are identified by trademarks of their respective companies or organizations.
Editor-in-ChiefCharles Lewis
Contributing WritersBecky PintoReeti PunjaLisa Garcia
Production EditorRobert DellaCamera
Art Director andProduction ManagerInga Talmantiene
Production ConsultantJovita Rinkunaite
Circulation EditorCathy Silva
8
11
14
19
24
27
34
42
Defect ManageMent
Metrology
fab econoMics
Mask
Data storage
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
A New Approach to Identifying Large, Yield-Impacting Defects on Polished Si WafersKerem Kapkin, KeunSu Kim, Jason Saito, Hyosik Suh – KLA-Tencor CorporationChung Geun Koh, Dae Jong Kim, Byeong Sam Moon, Seung Ho Pyi – Hynix Semiconductor Corporation
identify and sort out wafers with LLPDs before beginning device processing.
Wafer manufacturers need to detect, accurately identify and separate these defects from the background population of large particles, which may be cleaned or reworked, while avoiding unneeded wafer rejection. Also, since LLPDs are a result of various wafer manufacturing process issues, wafer manufactur-ers must quickly identify the LLPD root cause and implement fixes to prevent unnecessary wafer scrap.
In this article, we demonstrate a method for classifying these critical LLPDs by utilizing a new unpatterned wafer inspection system, the Surfscan SP2XP. The system’s latest technologies of GC (global composite) and RBB (rules-based binning) have proven effective for both the wafer manufacturers’ final inspec-tion step and IC device manufacturing IQC (Incoming Quality Control) applications.
For 45nm-generation wafers, innovations in bare wafer inspection technology provide enhanced capture and
classification of large, shallow defects. New classification technology, combined with multi-channel processing, enables
wafer manufacturers and IC device makers to find and separate these defects into categories based on whether they are
cleanable, or require scrapping the wafer. Identifying these defects early in the manufacturing process enables improved
product quality and higher yield.
As devices continue to shrink, wafer surface condition, defect size, shape and type are becoming increasingly important factors in device yield, performance and reliability. ITRS (Inter national Technology Roadmap for Semiconductors) guidelines stipulate a sensitivity to critical defects on a bare wafer surface of a size equal to one-half the design rule.
At the same time, IC manufacturers have been reducing the specification for the total number of defects allowed for accep-tance of incoming wafers and are now specifying limits on the number of large light point defects (LLPDs). These LLPDs are large but very shallow: they may be several microns wide but have a height of only a few nanometers. LLPDs are generated both during single-crystal silicon ingot growth and during the subsequent wafer-making and surface-preparation pro-cesses. These LLPDs manifest themselves on incoming bare silicon wafers in the form of faceted pits or bumps, air pockets and polishing scratches, and have a very high likelihood of becoming yield killer defects. Thus, IC manufacturers must
Particle COP Residue Scratch
0.1µm 0.1µm 0.1µm 0.1µm
Figure 1: Conventional defects or LPDs (Light Point Defects) which require increased sensitivity for detection and classification.
feature story
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Wafer Defect Types and Their Sources
Conventional small (sub-micron) defects that impact device yield include particles, COPs (crystal originated pits or particles), residues and scratches, and are well characterized. Examples of these defect types are pictured in Figure 1. Large particle defects on the wafer may originate from handling contamination, process equipment, or from the cleanroom’s ambient environment. Many of these can be removed with various cleaning processes.
LLPDs are more challenging to identify and characterize. A typical simplified Si wafer production scheme is shown in Figure 2. The source of faceted LLPD defects can be divided into two primary groups: the crystal-growing process and the wafering process.
Previously, the full spectrum of LLPD defects could not be separated by type or source and could only be categorized as one group based on their darkfield scattering signatures. However, their identification and classification by individual type is very important. Wafer manufacturers can use this infor-mation to isolate various process-related problems and crystal growth issues, then implement corrective measures. IC device manufacturers can use classification information to create their incoming wafer quality acceptance specifications based on specific LLPD type, defect size and number.
Conventional technology and methods in use by IC manufac-turers for testing incoming wafer quality are as follows: 1st Step - Unpatterned inspection tool – 1st sampling 2nd Step - Manual visual inspection for confirmation 3rd Step - SEM verification
Until now, wafer manufacturers have been unable to identify and classify LLPDs effectively, especially the separation of an
important defect type on bare Si wafers — faceted LLPDs (Figure 3). The most critical faceted LLPD is the air pocket defect, which forms during the crystal-pulling process and is distributed across the wafer within the silicon substrate. The size of the air pocket exposed to the surface is a function of its location and how much has been revealed during cutting and polishing of the wafer. While exposed air pockets can be measured in various sizes as pits, the buried ones in the bulk remain as voids.
Other types of faceted defects are created by either mechanical or chemical damage during etching or polishing steps. Although they are limited to the wafer surface and do not exist within the substrate, they can affect implant profile, device topogra-phy and electrical properties, which can destroy a die. Some faceted LLPDs can be reworked with further polishing and etching if caught during inline process monitoring.
Methods to Detect and Classify LLPD to Prevent Yield Impact
Wafer manufacturers require a production-worthy inspection technology that allows inspection of all outgoing wafers for all defects of interest (DOIs), with high throughput and economi-cal operating cost. It is necessary to capture the full range of DOI types and to automatically classify them with the highest accuracy and purity. This will prevent out-of-spec wafers from reaching the IC device manufacturer and eliminate unneces-sary wafer rejection and scrap due to false positives.
feature story
Crystal
LLPD (Crystal) LLPD (Wafering process)
Wire Saw Lapping Etching Polishing Inspection
Figure 2: Simplified Si wafer manufacturing process and faceted LLPD.
Large defects (~16µm)
Figure 3: Emerging (faceted) LLPD defects (polishing related defects, air pockets and etch-related defects, respectively).
The Surfscan SP2XP inspection system can identify large light point
defects by type, size and number.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
The most important goal of the first inspection step is to capture complete surface optical information with the highest possible sensitivity at a production-worthy throughput. As shown in Figure 4, the new system illuminates the bare Si wafer with both normal and oblique incidence 355nm UV laser beams to provide darkfield (DF) detection of DOIs. The light scattered from the various defect types is collected by both wide and narrow detectors, enabling further analysis and classification. This architecture results in four distinct light collection channels (oblique narrow, oblique wide, nor-mal narrow and normal wide).
In addition to the multi-channel darkfield collection, the sys-tem also employs a new brightfield (BF) illumination channel to capture other defect types or surface characteristics. This BF technology utilizes differential interference contrast (DIC) to
capture a phase difference, which reveals height or slope in-formation, as shown in Figure 5. This DIC technology allows detection of defects that are large, flat or shallow and may not be detected by darkfield channels.
After complete optical information of the wafer surface has been captured, it is analyzed using a new algorithm known as rules-based binning (RBB). RBB allows the user to compare mathematical or logical conditions between the five defect channels (BF DIC, DF Normal Wide, DF Normal Narrow, DF Oblique Wide, DF Oblique Narrow), as shown in Figure 6.
The results of these logical comparisons can be used to classify the defects of interest. All darkfield channels can be combined as the darkfield composite and all five channels, including brightfield, can be combined as the grand composite. The grand composite and brightfield channels serve to identify
Wide
BrightFieldDIC
Narrow
ObliqueIllumination
ScanRotatingWafer
Normal and BFIllumination
Collector
Figure 4: Surfscan SP2XP illumination and optics technology.
Time
Signal
Beam motion Arbitrary surface
A0
B C D E
Convex Step Concave
BA C D E
Figure 5: Brightfield (BF) illumination and differential interference contrast (DIC) technology.
NormalOblique BF DIC
Wid
eN
arro
w
Figure 6: Surfscan SP2XP creates five (5) channels of information for each defect.
feature story
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
LLPD defects, and RBB is used to further separate LLPD de-fects into particles, air pockets, polishing pits and etch defects. Schematic analysis is shown in Figure 7.
The data used in Figure 8 were obtained from seven 300mm wafer inspections. The DF channel information (oblique narrow and wide, normal narrow and wide) was merged into one DF composite plus BF. When the DF composite and BF defects were overlaid, the common defects were revealed as LLPD defects. SEM analysis verified 100% purity of this automatic classification.
Once the LLPD defects were identified, it was possible to further identify and separate the large particles, air pockets, polishing pits and etch defects precisely using BF (DIC) infor-mation combined with DF channel data through RBB.
A comparison of LLPD results using conventional methods versus new technology with RBB
Case Study 1: Twenty 300mm wafers
Twenty 300mm wafers obtained from various wafer manufac-turers were inspected, and the scan results were combined to compare the conventional method versus the new approach. SEM review showed a total of 29 LLPD defects.
The conventional method identified a total of 28 LLPD •
16 LLPDs were correctly identified -12 particles were incorrectly classified as LLPDs -13 LLPD defects were missed -
The results of this case study are shown in Figure 9.
The conventional method would have caused a 43% increase in false wafer rejection at the wafer manufacturer’s final inspec-tion step due to particles being reported as LLPD defects. Additionally, 45% of the total LLPD population was missed, passing the risk to the IC manufacturer’s customers.
The new RBB-based approach was able to detect all 29 LLPDs; only one particle was misclassified as an LLPD.
Case Study 2: Twenty-three 200mm wafers
In this case study, twenty-three 200mm wafers obtained from various wafer manufacturers were similarly scanned and the results combined for comparison of the conventional method versus the new RBB approach. SEM review confirmed a total of 28 LLPD defects on these 23 wafers.
The conventional method reported a total of 65 LLPDs •
20 LLPDs were classified correctly -45 particles were misclassified as LLPDs -8 LLPDs were not detected at all -
The results of this case study are shown in Figure 10.
The conventional method would have caused a 69% increase in false wafer rejection due to misclassification of particles as LLPD defects, and a 29% miss rate on LLPD defects which could have caused an unexpected device yield impact at the IC device manufacturer.
The new approach detected all of the 28 LLPDs successfully, as verified by the SEM review.
Electrical Analysis of LLPD Defect Types: Large Particles (LPDs) versus Large Pits (LLPDs)
In order to analyze the yield impact of various types of LLPD defects, an incoming prime wafer was inspected for LLPD defects. Two LLPD defects were captured on this wafer. SEM analysis
feature story
Darkfieldcomposite
An overlay of inspection data from seven 300mm wafers
8950 DFC Defects 56 BF Defects 17 LLPD Defects
oblique + normal common defects
Grand compositeLLPD : DF & BF
Brightfield
LLPDCluster
LLPD
LLPD LPD Purity
LLPD 17 0 100%
LPD 0 8950 100%
Accuracy 100% 100%
Figure 8: Grand composite of DF and BF(DIC) for LLPD classification.
True LLPD
Missed LLPD
Particles classified as LLPD
Missed LLPD
LLPD
Conventionalmethod
Newapproach
Identified LLPDby review
12ea.
16ea.
1ea.
29ea. 29ea.
13ea.
Figure 9: Current challenges with faceted LLPD in 300mm wafer manufacturing.
Grandcomposite
Defect classification
Classification with rules-based binning
LPD
LLPDcrystal
LLPDwafering
LLPDwafering
Grand compositewith RBB
Grandcomposite
Darkfieldcomposite
Brightfield RBB
Figure 7: Rules-based binning classification results.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
identified them as a large particle and a polishing pit. This prime wafer was allowed to proceed through complete process-ing for 80nm DRAM memory devices. Electrical test results of the die built on the LLPD defect locations revealed that both had yield-related issues, although at differing levels of severity. While the large particle generated a few bad memory cells, the polishing pit completely destroyed the memory device, as shown in Figure 11.
Further analysis of the failure mechanism caused by the polished pit revealed that after the CMP process, the SiO2 STI (Shallow Trench Isolation) film was not completely polished and removed over the Si3N4 etch stop. Therefore the subse-quent wet chemical Si3N4 removal process was unsuccessful in and around the pit, preventing formation of the working transistor structure necessary for the memory cell.
Conclusions
Although shrinking device design rules are driving sensitivity requirements to capture smaller critical size defects, large, yield-impacting defects have been growing in importance.
Wafer manufacturers require a better method to capture and accurately classify LLPDs to prevent unnecessary false wafer rejection or shipping of defective wafers to IC device makers that do not meet IQC specifications. Capturing and correctly classifying these defects early in the wafering process has the additional benefit of rapid root-cause identification that allows wafer manufacturers to quickly implement corrective measures at the right process steps to ensure consistent product quality.
The new wafer inspection technology has demonstrated the ability to address the challenges faced by both wafer manufac-turers and IC device manufacturers and has provided a solution for improving product quality, cost and productivity. The new rules-based binning technology, combined with multi-channel processing, gives wafer manufacturers and IC device makers dramatically increased effectiveness in defect capture and accurate classification for both conventional defect types and yield-killer LLPDs. This achieves the goal of improving wafer quality, an important factor in overall yield, ultimately improving the fab’s financial bottom line.
Acknowledgments
The authors would like to thank the engineering and applica-tions staff at Hynix Semiconductor Wafer Engineering Group, and KLA-Tencor’s Surfscan division for their valuable contri-butions to this original work and team effort.
This work also would not have been successful without the direction, information and strong support from wafer manufac-turers across the globe.
References
1. International Technology Roadmap for Semiconductors 2005 Edition,
Yield Enchancement, pp. 7–10.
2. C.G. Koh, D.J. Kim, Hynix Technical Report, A06041883, Evaluation
Result of SP2 SSIS - 200mm Wafers, UNPUBLISHED.
3. C.G. Koh, B.S. Moon, D.J. Kim, Hynix Technical Report, A06095565,
Evaluation Result of SP2 SSIS - 300mm Wafers, UNPUBLISHED.
Before CMP
After CMP
STI
Si
Device failure area
Figure 12: Device failure caused by remaining oxide and the unstripped nitride film due to patterning and CMP issues of the faceted LLPD.
90
778M
1A1A 1A
778793
2104
K
1A46
1C 1C
LLPD Wafering
Killer Device Yielding Die
300mm prime wafer inspection before device processing
Large Particles
s
Figure 11: DRAM device memory cell bitmap; yield impact of faceted LLPD vs. large particle on 80nm DRAM in IC manufacturing.
feature story
Missed LLPD
LLPD
Conventionalmethod
Newapproach
Identified LLPDby review
45ea.
20ea. 28ea. 28ea.
8ea.
True LLPD
Missed LLPD
Particles classified as LLPD
Figure 10: Current challenges with faceted LLPD in 200mm wafer manufacturing.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Etch Process Monitoring by Electron Beam Wafer InspectionLuke Lin, Jia-Yun Chen, and Wen-Yi Wong – Powerchip SemiconductorMark McCord, Alex Tsai, Steven Oestreich, Indranil De, Jan Lauber, and Andrew Kang – KLA-Tencor Corporation
the end of processing can provide confirmation. However, this approach can have several drawbacks. For instance, uncon-trolled variables can add uncertainty to the data, especially if the defect signature used to determine the optimum process setting is subtle. These variables can include changes in prior layer processes, changes in the lithography, changes in etch process (or tool/chamber), and the stability variance in the inspection tool. For electron beam inspection, differences in the residual surface charge or atmospheric molecular contamination (AMC) between wafers can also affect the inspection results.
For these reasons, it would be preferred to use a single wafer in order to determine the optimum etch process condition. In this study, we have developed such a technique, and have successfully used it to optimize etch process conditions.
Experimental Approach
Three full-flow DRAM wafers with 0.11µm design rule were used in this study. All wafers were processed normally up to the contact etch step. On each wafer at the transistor contact etch level, various dies received either nominal etch process condition or one of several different etch conditions, as shown in Table 1. The dies were arranged to facilitate die-to-die comparison of nominal and test dies in an automatic wafer inspection tool. Columns of test dies were alternated with two
Table 1: Summary of the etch process conditions used for different die on each wafer.
Using E-beam inspection to establish defectivity levels from contact etch, Etch Process Window Qualification (Etch-PWQ)
can provide accurate yield data to help users center the etch process within the process yield window, then monitor the
etch process condition.
Process Window Qualification is a technique commonly used with optical and electron beam wafer inspection to keep the lithography process centered within the process window. Different dies across the wafer are exposed with varying focus and dose parameters. An inspection is used to determine the defectivity of the dies with different exposure conditions, and special software is used to analyze the results.
For etch processing, it is also critical to center the process within the process window. For instance, under-etch on a contact layer can result in blocked or resistive contacts, while over-etch can cause shorts between source, drain, and/or gate on the transistor. Traditionally, wafer splits are used to deter-mine optimum etch process conditions. Two or more wafers are used, and each wafer is processed with a different etch condition. Optical or electron beam inspection can then be used to compare overall wafer defectivity. Electrical test at
Defect ManageMent
Test 1
Test 2
Test 3
Figure 1: Wafer die layout showing location of nominal dies and dies with different etch process conditions.
Etch condition Gas flow Over-etch time
Nominal 20 sccm 69 seconds
Test 1 21 sccm 55 seconds
Test 2 19 sccm 69 seconds
Test 3 19 sccm 75 seconds
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
columns of dies processed using the nominal condition. In this way, each test die could be compared to two adjacent nominal dies. In addition, the various test dies were distributed across the wafer so that the process signature could be distinguished from any wafer level signature that might be present. The wafer layout of nominal and test dies is shown in Figure 1.
In order to process the various etch conditions on different dies on a single wafer, multiple lithography steps were utilized. First the nominal dies were exposed and etched, while the test dies were protected by blank resist. Then the lithography and etch process steps were repeated for each of the different etch process conditions on the test dies, while the nominal dies were protected by unexposed resist. In this way, the various process conditions were all placed on a single wafer. Figure 2 shows a flow chart of the lithography and etch processing steps.
Following the etch process steps, wafer #1 was checked for contact size using a CD-SEM, then continued with normal processing through electrical test. Wafer #2 was removed from the process flow and inspected first with an eS31 electron beam inspection tool, then with an eS32 electron beam inspection tool. Wafer #3 was held after the contact etch step for poten-tial further study, such as FIB or TEM.
Results
Initially wafer #2 was inspected on an eS31 electron beam in-spection tool using a landing energy of 1000eV, beam current of 212nA, and a pixel size of 100nm. Field conditions were set up such that underetched contacts would appear brighter than normal contacts, which are dark. The inspection failed to show any significant correlation between the etch conditions and the die defectivity. However, end-of-line bit failure testing on wafer #1, which continued with normal processing, showed a definite yield loss correlated with the etch process conditions. The bit yield map is shown in Figure 3; slashes indicate dies with poor bit yield results.
At this point, the wafer was re inspected using an eS32, which has improved sensitivity and a wider range of optics settings. The inspection care area was extended to the very edge of the array, where it was found that most defects were occurring.
Defect ManageMent
Wafer preparation and photo exposure shot edit
Overlay measurementin spec?
Condition 1~N etchPR strip & wafer clean
CD measurement
Scan by e-beam inspector
PR coating and etch Condition 1~N
Shot exposure/development
Photo rework
Repeat1~N Yes
No
Figure 2: Process flow for creating dies with multiple etch conditions on a single wafer.
Using a 70nm pixel to increase sensitivity
and a precharge step to enhance contrast, subtle under-etch defects
were detected that correlated with both the etch condition
and with the end-of-line bit yield results.
Figure 3: End-of-line bit failure map showing correlation with both etch process die split and in-line defect inspection map.
Figure 4: Defect inspection map of etch wafer showing variation in defectivity with etch process condition.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
A special precharge step was implemented to bring the wafer surface voltage to a condition that enhanced the contrast of the defective contacts. Finally, the inspection pixel size was reduced to 70nm in order to further increase sensitivity. This time, subtle under-etch defects were detected that also cor-related with both the etch condition and the end-of-line bit yield results. The defect map is shown in Figure 4. A good correlation was found between inspection defect density on wafer #2 and electrical bit yield on wafer #1. A review image
from the inspection tool containing some defective contacts is shown in Figure 5.
ePM is a new eS32 algorithm currently under development at KLA-Tencor that can be used to find out-of-tolerance wafers more quickly than standard e-beam inspection. Images are taken from identical locations on each of a selected number (or all) dies on the wafer. The average gray level of each image, which correlates to the average secondary electron yield, is computed and mapped. Because slight process variations can cause a significant variation in secondary yield, this technique can be used to establish process tolerance limits on etch or other process steps. Figure 6 shows the ePM gray level map of the wafer, clearly indicating differences between nominal and test die. Figure 7 shows a comparison between the contact CD measured on wafer #1 and the average gray level seen by ePM, for each of the four etch process conditions. Again, there is excellent correlation between the two measurements. As expected, underetch conditions resulted in a brighter average gray level because the normal contacts are darker than the surrounding oxide.
Conclusion
Etch Process Window Qualification (Etch-PWQ) has been shown to be a promising technique for establishing defectivity levels from contact etch and for providing accurate yield data to center the etch process within the process yield window. By placing the experimental design on a single wafer, data uncertainty caused by wafer process variations or inspection tool drift is avoided. In order to see subtle under-etch defects from marginal etch process conditions, it was necessary to use a precharge step and to select optics conditions to optimize sensitivity. Good correlation was seen between the inspection defectivity and the electrical bit yield. Finally, ePM, an electri-cal process monitor capability on the eS32 inspection tool that measures secondary yield across the wafer, shows promise as a tool for monitoring the etch process condition.
Acknowledgements
The authors gratefully acknowledge the support of Jason Lim and Kumar Raja for their help in this study.
Defect ManageMent
Figure 5: Review image from the eS32 inspection showing a cluster of under-etched contacts.
2
4
6
8
10
12
2 4 6 8 10 12 14
Figure 6: Gray level ePM map of wafer showing correlation between etch process condition and gray level intensity of images.
CD (nm)
nominal test 1 test 2 test 3
0.195
0.190
0.185
0.180
0.175
0.170
0.165
0.160
0.155
CD (nm)
Gray level
nominal test 1 test 2 test 3
60
70
80
90
100
110
120
Gray level
Figure 7: Comparison between measured CD and average image gray level for the different etch test conditions.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Defect ManageMent
Enabling Manufacturing Productivity Improvement and Test Wafer Cost ReductionMing Li, Lisa Cheung, and Mark Keefer – KLA-Tencor Corporation
Use of a Surfscan SP2 inspection system can cut production costs by extending the reuse lifetimes of some monitor
wafers and reducing the need for new test wafers. For a large foundry, this new technology can increase the in-house
recycle rate and decrease the repolish rate by 15%, which translates to over $3M in annual savings.
Today’s wafer fabrication plants must carefully balance the need to increase productivity while simultaneously reducing variable costs. There are a couple of main areas where process control (metrology and inspection) equipment can help minimize variable cost. The first is reducing consumables – minimizing the number of wafers that are processed for non-revenue operations, i.e., test wafers. Second is process equipment productivity improvements, by reducing the number of maintenance cycles per year and the associated time lost due to resolving process excursion false alarms. This article will explore these ideas in more detail, to determine an effective method for reducing test wafer cost in a leading-edge 65nm design rule foundry.
Process Tool Monitoring
Particle counts on unpatterned test (or ‘monitor’) wafers are typically used to monitor the health of process tools, either after preventive maintenance (tool qualification) or prior to running production wafers, after a specified number of hours or at the beginning of each shift (tool monitoring). Process tool qualification occurs after preventive maintenance or to requalify the tool after unscheduled downtime. Tool monitor-ing is used to quickly detect process tool excursions. Addi-tionally, unpatterned wafer inspection tools can be used for engineering analysis work, either to characterize new process tools or diagnose specific contamination problems that led to a process tool being removed from production (‘tool-down’ problems).
Process tool monitoring uses a single unpatterned test wafer for each process chamber, with higher grade wafers used for front-end-of-line processes, where critical dimensions are smaller and greater inspection sensitivity is required. The test
wafer is inspected, passes through the process tool (with or without activating the process chamber) and is reinspected. Added defects are calculated using a traditional post- minus pre-count calculation, or a more sophisticated map-to-map defect overlay comparison (reference 1). Post-scan inspection results reveal any defects added by the process tool, expressed as particles per wafer pass (PWP) added.
The Process Tool Monitoring Procedure
The first step of the process tool monitoring procedure is to assign the test wafers into bins by grade. Grade (usually A, B or C) refers to the quality of the test wafer appropriate for different monitoring applications, in this case its surface roughness, since smaller-size particles can be more reliably detected on smooth wafers than on rough wafers. Surface roughness is normally measured by using the inspection tool to detect haze, the low-frequency, low-amplitude component of the light scattered from the wafer surface. Haze is measured in ppm, a ratio of the average surface scattering intensity to the incident laser beam intensity. For bare wafers, haze is strongly correlated with surface roughness. (When a transparent film is present, haze also includes film parameter variation.)
The second step is the actual process tool monitoring step: comparing pre- and post-processing inspections and quantify-ing the added defects. In order to re-use the test waters, they are chemically stripped to remove any film layers and particles that were added by sending them through the process tools. The chemical stripping results in higher surface roughness or haze (the upper loop in Figure 1), and the test wafers must be regraded. After a certain number of recycle steps the test wafers fail the roughest grade specifications, and are then sent for re-claim (repolished) or scrapped (the lower left loop in Figure 1).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Extending the Useable Life of Monitor Wafers
Defect detection sensitivity is determined by the ratio of the defect signal to its back-ground. As the background level (haze) approaches the detection threshold, the signal-to-noise ratio decreases (Figure 2, left). To ensure that defects can be detected with-out the occurrence of false alarms, it is desirable to keep a high defect signal-to-noise ratio, typically above 3.
However, as the number of chemical strips (recycles) increases the surface roughness and haze of the test wafer, the signal-to-noise ratio for detection of small defects on the wafer surface decreases. Manufacturing considerations such as matching one inspection tool’s results to other tools dictate that the inspection sensitivity threshold remains at a fixed value. This means that the detection threshold cannot simply be increased to mitigate the increased back-ground noise, as suggested in Figure 2 (right). Hence, the number of recycle steps that can be performed on any given test wafer is limited by this increase in surface roughness.
What is needed is a way to increase the inspection signal- to-noise ratio for small defects on rough wafers. The current generation wafer surface inspection system, the Surfscan SP2, has a smaller spot size than the previous- generation SP1, which means that less background is included when the spot is focused on a small defect. This gives the Surfscan SP2 better sensitivity on rough wafers than the SP1. Figure 3 shows a comparison of the same high-haze wafer, recycled many times, scanned using the Surfscan SP1 (left) and SP2 (right) systems. The SP1
Defect ManageMent
Surfscan SP1 Surfscan SP2
Test wafers
PWP < XSP1Inspection
Grade A, B, C ProcessPre SP1
Inspection Post SP1
Inspection
New wafers
Scrap $300/wfr Re-polish $30 / wfr
Regeneration area
Grade
Reclaim 1 Reclaim 2 Reclaim 3
Roughness
A B C
GradingA < X1 counts <Y1 ppm
B < X2 counts <Y2 ppm
C < X3 counts <Y3 ppm
In-house chemical clean
Figure 1: Process monitoring loop using test wafers
Threshold Threshold
Scan positionScan position
Lase
r sc
atte
rin
g s
ign
al (
pp
m)
Lase
r sc
atte
rin
g s
ign
al (
pp
m)
Haze Haze
Noise
Figure 2: Relationship between wafer surface roughness (haze) and inspection sensitivity, for a wafer having a low haze value (left) and a high haze value (right). Note: Noise is proportional to the haze.
S/N
Rat
io
Defect Size (µm LSE)
18
0.06
15
0.07
12
0.08
9
0.09
6
0.10
3
0.11
0
0.12 0.13
SP2 HT Mode S/N vs. Wafer Haze Level
0.150.14
Low HazeMedium HazeHigh Haze
S/N
Rat
io
Defect Size (µm LSE)
18
0.06
15
0.07
12
0.08
9
0.09
6
0.10
3
0.11
0
0.12 0.13
SP1 HT Mode S/N vs. Wafer Haze Level
0.150.14
acceptable inspection window
acceptable inspection window
Low HazeMedium HazeHigh Haze
Figure 4: Signal-to-noise vs. wafer haze level comparison (Surfscan SP1 left, SP2 right) for defects of varying size. The acceptable inspection window has S/N ratio above 3, and defect size below 88nm LSE.
Figure 3: Rough wafer sensitivity comparison. Surfscan SP1 map on left shows predominantly false defects, while SP2 map on right shows predominantly real defects, with the smallest defects having a S/N > 3.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
map shows a significant population of false defects caused by the low signal-to-noise value. The inspection threshold, set to capture the real defects, is also capturing the peaks of the haze signal. On the other hand, the SP2 map shows significantly fewer false defects, since its superior sensitivity allows the scan threshold to be set well above the haze level. The capability of the Surfscan SP2 to enhance signal and better suppress noise enables this type of inspection, in turn allowing test wafers to be recycled for a longer period of time before they are re-claimed or scrapped.
Figure 4 shows signal-to-noise analyses for SP1 and SP2 on wafers of varying haze levels. The acceptable “inspection window” is at the upper left portion of the chart (better than 88nm sensitivity at S/N ratio ≥ 3). The SP1 high throughput mode cannot meet the 3:1 signal-to-noise requirement at the required 88nm defect sensitivity on high-haze wafers. SP2’s enhanced sensitivity and background noise suppression is able to meet the required sensitivity, even when using high-haze wafers, in high-throughput mode.
Economic impact
Figure 4 shows that the Surfscan SP2 can achieve sufficient sensitivity and signal-to-noise on rougher wafers; as a result, a dedicated SP2 inspector was placed into the in-house reclaim
center in the fab where these measurements were taken. Wafers that would have been in the Grade B category for Surfscan SP1 inspection are now in the Grade A category for SP2 inspection. Conse-quently, wafers can be recycled more times – the recycle rate in the in-house chemical clean center was estimated to have increased by 15%. This higher recycle rate corresponds to a decreased reclaim (repolish) rate (Figure 5).
Using these new recycle rates, we can estimate the cost sav-ings as follows, for a 300mm foundry running 25K WSPM, with test wafer usage equal to 3x the production rate,
or 75K WSPM. Surfscan SP2 implementation increases the in-house recycle rate and decreases the reclaim rate by 15%, which translates to approximatly $3M in annual savings for this case ( Table 1). The model can be adjusted to accommo-date different wafer starts, test wafer usage, etc.
Summary
Wafer fab productivity benefits from reduction of variable costs. Test wafer lifetimes directly impact their usability for process tool monitoring. Using a Surfscan SP2 inspection system instead of a previous-generation tool has been shown to enable further reuse of some monitor wafers, which also reduces new test wafer purchases. In addition to the quantifi-able economic impact of test wafer cost reductions, fab manu-facturing productivity also increases, while disruptions due to false excursion alarms resulting from unstable inspection results of roughened reclaimed wafers are minimized.
Acknowledgements
This material was originally presented at the KLA-Tencor Yield Management Seminars in Shanghai (August 2006) and Beijing (September 2006).
References
1. Lorrie Houston, Motorola; John Anderson, Motorola; Rhonda Stanley, KLA-Tencor; “Process tool qualification using SP1TBI automated overlay feature,” KLA-Tencor Surfscan Applications Note (2002).
Defect ManageMent
Test wafers
PWP < XSP2Inspection
Grade A, B, C
Process Pre SP2
Inspection
SP2
Post SP2 Inspection
New wafers
Scrap $300/wfr Re-polish $30 / wfr
Regeneration area
Grade
Reclaim 1 Reclaim 2 Reclaim 3
Roughness
A B
In-house chemical clean$5 / water recycle
Recycle rate from 70% to 85%
$75K/month
20% 5%10%
Figure 5: Net increase in wafer recycle rate
Wafer Type Recycle Reclaim Scrap Total Test
Wafer CostWafer Cost $5 $30 $300
Wafer Volume (total =75K)
52.5 > 63.75K 15.0 > 3.75K 7.5K
Recycle Rate (SP1) 70% 20% 10% $2.96M
Recycle Rate (SP1+SP2)
85% 5% 10% $2.68M
Cost saving per month $56,250 $337,500 no change $0.28M
Table 1: Estimated monthly cost savings from increased wafer recycle rate: $0.28M, for an annual savings rate of $3.36M.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
One of the outcomes of the continuing trend to smaller geometries is the need to incorporate real-time tool data with other forms of metrology data.1 The semiconductor industry defines metrology data in terms of its relation to the process tool: offline (apart from), in-line (attached to for measurement immediately before and after) and in-situ (integrated into, for measurement during processing). The subject category “off- line/in-line/in-situ metrology” will be included in the ITRS Metrology and Factory Integration sections beginning with the 2007 revision.2
Instrumented substrates straddle the categories described above in that they gather real-time information from inside the process (in-situ), simultaneous with spatial information (off-line); yet these instruments can be read immediately before and after the process (in-line). The sections below describe a range of 45nm node-relevant application examples showing the use of instrumented substrates.
Physical Vapor Deposition (PVD): Copper Barrier / Seed Chamber Matching with Temperature
With the addition of copper to the semiconductor metalliza-tion portfolio came the need for careful attention to seed layer and barrier growth. With the attendant reduction in deposi-tion temperatures, wireless sensor wafers became a viable method to characterize these processes and provide a means for chamber matching.
Two production Cu seed chambers were investigated for vari-ous RF power and chuck temperature conditions.3 Low-and high-power conditions were evaluated in a matrix with room, low, and ultra-low cathode temperature conditions. Baseline conditions (low power, low temperature) are depicted in Figures 1a and 1b. Immediately visible are differences in thermal uniformity and mean temperature. Chamber A shows high non-uniformity at the edge near the notch. Chamber B shows a concentric, uniform pattern with tighter range. Spatial temperature data from the SensorWafer runs were examined and modeled with respect to the RF power and chuck tem-perature parameters. The source of the mismatch was localized to the area near the notch and was determined to be due to non-uniformities in RF power delivery.
Chemical Vapor Deposition (CVD): Plasma Nitridation
The properties of these CVD films are strongly dependent on the temperature of the substrate during deposition. Substrate temperature is controlled by power input to the substrate through the source and bias electrodes, as well as temperature control within the electrostatic chuck or heated plate.
Smaller feature nodes have reduced the temperature budget of CVD processes. Thermal process CVD furnaces have historically operated in the regime of 600–1000°C. With the addition of plasma enhancement (PECVD), the substrate temperature
Metrology
Wafer Level Metrology Expands Process Applications at 45nmPaul MacDonald, Greg Roche, Mark Wiltse -– KLA-Tencor Corporation
Instrumented wafers, including KLA-Tencor’s Integral™ SensorWafers™, are increasingly being used to optimize,
troubleshoot and monitor many different process applications. These specialized substrates contain complete
metrology instrumentation that can provide high-precision, time-sequence measurements that show a wafer’s response to
the dynamic process environment.
Mean 81.121Range 47.365
Mean 71.807Range 33.599
a) b)
Figure 1: Low power, low temperature Cu Barrier deposition: a) Baseline 2-D thermal profile of chamber A (left); b) Baseline 2-D thermal profile of chamber B.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
dropped to the 250–550°C range. Subsequently, with the 45nm node, substrate temperature has dropped even further with the advent of “ultra low-k dielectrics” as well as some “high-k gate” structures. Recently, PECVD films have been developed as ultra low-k barrier layers using substrate tem-peratures in 30–50°C range.4 Plasma nitridation has come into use for adding insulating or barrier properties to some high-k gate materials.5
In Figure 2, a plasma nitridation process was characterized with the maximum temperature ~40°C. The initial tests gave some insight into the temperature uniformity and behavior as the substrate approached its peak temperature. The spatial tempe-rature profile is shown in the right portion of the figure.
Next, an experiment was run in a low-temperature plasma nitridation system to determine the effect of seasoning wafers on wafer temperature profile. Here the SensorWafer was run before and after every series of three seasoning wafers (Figure 3). The chamber appeared to reach steady-state temperature after nine seasoning wafers. Interestingly, the across-wafer temperature profile changed during the course of the seasoning (Figure 4).
Chemical Mechanical Polish (CMP)
Chemical mechanical polishing (CMP) is a process of film removal that combines both physical and chemical aspects of abrasives in a slurry with a polishing pad on the surface of the wafer. Tempera-ture is not controlled for this process, but is a function of several key control parameters: polishing head rotation speed, platen rotation speed, head pressure and slurry flow.6 SensorWafers were used to study the wafer surface during polishing as a function of process conditions.
Figure 5 shows the temperature versus time trace as collected by the Integral SensorWafer. Interesting temperature data fea-tures are visible in the traces: global temperature, across-wafer variation, and rotational effects.
Lithography Direct CD Tuning with Temperature
Lithography is one of the most important application areas of SensorWafer metrology. With each node, the processes within lithography have become progressively more temperature sensitive, placing a strain on hardware matching and control in the litho cell. For example, the SensorWafer is frequently used to adjust the temperature profile, both spatially (across a bake plate) and temporally (temperature rate of change), and from plate to plate. Temperature profiles are then stored in the litho tool. The tool is then monitored with a SensorWafer on a routine basis, after PM, and by exception.
In this study, the SensorWafer output was used to adjust the CD directly. That is, the processed wafer CD was optimized by ad-justment of the photoresist bake plate temperature profile. The adjustment of the temperature profile occurs in three steps:
collect baseline temperature information;1) calculate optimal control inputs and provide 2) adjustments to bake plate; verify temperature performance.3) 7
Metrology
Time (s)
Tem
per
atu
re ˚C
Figure 2: Temperature response of a room temperature plasma nitridation process. Each trace represents one temperature sensor, so the spread across the traces is indicative of spatial non-uniformities.
Cumulative seasoning wafers
Temperature profile vs. seasoning wafers
Tem
per
atu
re m
ean
(˚C
)
Tem
per
atu
re r
ang
e (˚
C)T-mean
T-range
0 5 10
6
5
4
3
2
1
6
39
38
37
36
35
3415 20
Figure 3: SensorWafer mean temperature and range as a function of chamber seasoning.
Figure 4: Temperature spatial profile before seasoning (left) and after 9 wafers seasoning (right).
20C
2C /1sec
4C
Global temperature rise during polishingAcross-wafer variation by radial zoneRotation effectsEdge variation due to rotation is much greater than the center
Figure 5: Temperature versus time trace for CMP characterization experiment using an Integral™ wafer.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
In this example, a 48nm CD process with a seven-zone PEB plate was adjusted in one run, utilizing specialized software (AutoCD™) to calculate the control inputs. Figure 6 shows the results for the wafer mapped CD before and after plate adjustment. The pre/post range improvement was 22%.
Plasma Etch
Plasma etch is one of the most important applications for SensorWafers. Plasma etch processes are extremely complex; the processed wafer results are a strong function of the process controls as well as the materials and topology of the devices being etched.8 Further, conditions in etch chambers are not constant; chamber surfaces change over time due to physical and chemical exposure. The etch results are typically very temperature dependent, and temperature is, in many cases, a good metric for conditions of the plasma at the wafer surface. Commercial reactors typically have power delivered to source and bias electrodes. Below are four examples of key applica-tions for SensorWafers.
Plasma Etch Example 1: Chamber Periodic Maintenance Qualification with Temperature
Etch processing chambers require frequent preventive mainte-nance (PM) activities to achieve consistent device performance. SensorWafers provide a useful, mobile platform for verification of chamber health.
Figure 7 provides a representation of chamber health during a clean cycle. Temperature range (maximum temperature minus minimum temperature) was measured periodically to under-stand chamber health. When the temperature range deviated above the upper control limit (UCL), a PM was executed. The UCL chamber deviation was inspected spatially and the devia-tion was found at the wafer edge. After the PM was completed, chamber performance was verified and the chamber was placed back into production.
Plasma Etch Example 2: Chamber Matching with Temperature
Chamber matching for critical etch processes continues to be a challenge. Shrinking geometries and increasing aspect ratios demand that subtle chamber differences be identified and resolved to achieve the desired level of performance. To isolate the source of a yield-limiting deviation, two chambers were compared.9 Critical response knobs were characterized in a golden chamber and a problem chamber (Figure 8). The response of each critical process knob was characterized with a combination of SensorWafer data and advanced analysis software.
Table 1: Plasma etch control variables with associated response for temperature SensorWafer.
Metrology
Recovered Chamber
Chamber Deviation
Time Units
20T - Range [All]
UCL
Nominal
16141210 8 6 4 2 0
11.55
10.13
8.70
7.27
5.84
4.41
Figure 7: SPC chart of SensorWafer temperature, with details of spatial temperature profile.
PM1Golden chamber
Model A Model B Difference
Model A Model B Difference
Model A Model B Difference
PM2Problem chamber
Difference
LowerelectrodeRF powerincrease
Edge Hecooling
Center Hecooling
5.00E-02 2.50E-02
-2.50E-020.00E+02
5.00E-01 7.00E-01
-3.00E-01-5.00E-01
0.00E+00 3.00E+01
-2.00E-00-5.00E-00
Model A Model B Difference
Lowerelectrodetemp
1.70E+00 3.00E+01
-7.00E-007.00E-00
Model A Model B Difference
Chamberpressure
1.00E+01 5.00E+02
-1.00E-01-2.00E-00
˚C /
˚C
˚C /
˚C
˚C /
T
˚C /
T
˚C /
T
˚C /
T
˚C /
W
˚C /
W
˚C /
mt
˚C /
mt
Figure 8: Comparison of golden chamber and problem chamber. Each plasma reactor subsystem was characterized with PlasmaRx software. A spatial analysis engine determined the lower electrode temperature to be the source of reactor deviation.
Process variable and response - Summary
Process Variable Response to Increased Process Variable
Lower Electrode RF Power Increase Increases Heat to the Entire Wafer
Edge Helium Cooling Decreases Heat at the Edge of the Wafer
Center Helium Cooling Decreases Heat at the Center of the Wafer
Lower Electrode Temperature Increases Heat to the Entire Wafer
Chamber Pressure Radial Effect
CD
Pre CDMean: 48.56 nmNormalized 3σ: 1
Mean: 48.83 nmNormalized 3σ: 0.78
Validation
–50.97
– 46.65
– 48.02
–49.50
Figure 6: Wafer level CD maps for pre - (left) and post - (right) temperature profile adjustment.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Process variables for both reactors responded as intuitively expected (Table 1). To identify the source of the performance issue, shape-matching algorithms were applied to each response. Through this approach, the lower electrode temperature was targeted for fast repair as the source of the chamber mismatch.
Plasma Etch Example 3: Problem Troubleshooting with Temperature
In-line defect inspection maps revealed unacceptable perfor-mance levels localized to specific die with self-aligned contact (SAC) etch.10 The SensorWafer (PlasmaTemp™) was run
through the tool, showing that observed temperatures were elevated approximately 3˚C at the wafer’s center. Spatial data review clearly revealed a strong local pattern of the problem in the two-dimensional maps of the temperature profiles (Figure 9). The faulty temperature pattern correlated directly with lift pin locations. The lift pins were examined, and it was discovered that their retraction heights were set incorrectly. Subsequent analysis of the probe data confirmed that the localized SAC under-etch was limited to the die located over the lift pins. The hardware problem was repaired, and the resulting temperature signature closely resembled the baseline temperature profile, indicating the fault was repaired. Probe results upon resumption of production confirmed this finding.
Plasma Etch Example 4: Plasma Process Monitoring with SensorWafer Electrical Measurement
Although temperature has proven to be a good metric for plasma etch characterization, in some plasma etch environ-ments it is not enough. In this example, measurement of voltage at the wafer surface (PlasmaVolt™) provided a more useful diagnostic.
The example in Figure 10 shows the drifting down of Vpp as measured by the tool and a corresponding detection by PlasmaVolt of the drift downward. However, the temperature wafer reported a steady state as the thermal inertia of the process and the lesser power created opposing thermal flux and resulted in relative equilibrium.
The increased sensitivity of electrical measurements allowed enhanced characterization of subtle process effects that were not temperature-related. In this production fab example, the electri-cal measuring SensorWafer was called into use to help diagnose an etch CD issue that had been localized to chamber E.11 In this situation, existing testing methodologies were unable to identify any functional differences between the two chambers. Comparing data traces from bad chamber E and good chamber D, the SensorWafer electrical measurement indicated instability during the etch step (Figure 11). Since it is a voltage measure-ment, it was logical to assume that this instability was located in the RF power delivery system. The problem was soon found to be a faulty power delivery cable. After cable replacement, follow-up metrology wafers were run and the CD values were found to have returned to normal.
Conclusions
Some examples of in situ wafer level metrology have been pro-vided. It is evident that instrumented silicon wafers, including KLA-Tencor’s SensorWafers, have shown great utility in aiding the understanding of semiconductor processing. Some of the key trends identified here are:
Shrinking process windows with concomitant manufac-•
turability issues will continue to create demand for in situ wafer level metrology.
Reduced process temperatures and thermal budget favor •
the use of wireless SensorWafers.
Electrical measurements provide powerful augmentation •
to temperature for plasma systems.
Metrology
Faulty
Hot spot
Normal
-11.0-7.0-3.0-0.0
-11.0-7.2-3.6-0.0
Figure 9: 2D normalized temperature profile. Faulty condition where hot spot caused by lift pins is discernible (left panel); after fault was corrected (right panel).
Temperature Data
Reported Chamber Vpp
PlasmaVolt Data
850
2000
4000
6000
60
40
80
100
0 900 950 1000 1050
50 100 150 200 250 300
Time (s)
Time (s)
RF
Vo
ltag
e (V
)Te
mp
erat
ure
(C
˚)
Figure 10: Plasma etch chamber time synchronized data. PlasmaVolt (top); Vpp as reported from bias power delivery system (middle); SensorWafer temperature data (bottom).
Chamber D Chamber ENominal CD
Time (s) Time (s)
“bad” CD
RF
Vo
ltag
e (V
)
420 440 460 480 500 520 300 320 340 360 380 400
2900
2800
27002600
2500
2400 RF
Vo
ltag
e (V
) 2900
2800
2700
2600
2500
2400
Figure 11: PlasmaVolt traces for two plasma etch chambers, each providing nominal and out-of-specification CD performance.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SensorWafers
Wireless instrumented wafers (generically SensorWafers) have the advantage of being run through standard semiconductor equipment robotics. SensorWafers are limited by the tempera-ture of on-board electronics, which is typically on the order of a sustained 140°C. Each semiconductor roadmap node has brought with it lower processing temperatures and smaller thermal budgets, which has aided the use and acceptance of the wireless metrology. Most SensorWafers measure temperature. More recent additions measure voltage.
The image above shows an Integral™ wafer with a 10µm poly- imide coating. The polyimide is transparent to visible light, thereby allowing a view of details of the electronics and temperature sensor locations. All sensors and electronics lie beneath the plane of the wafer surface. There are several pos-sible alternative configurations of this temperature SensorWafer, which include having a cover layer of silicon, silicon dioxide, or an other customer-specified material. Depending on configura-tion, these instrumented wafers find use in wet processing, CMP, lithography low temperature CVD, PVD, and plasma etch.
The image below shows a 300mm PlasmaVolt™ wafer with electrical sensors and measuring electronics visible on the sur-face. Sensors and electronics have a profile 3.4 mm or less above the wafer surface. With this profile these SensorWafers can be loaded with standard robotics through most 300mm production vacuum equipment. The entire wafer is covered with polyimide, which is chemically very similar to photoresist. These types of SensorWafers find use primarily in plasma etch.
References
1. International Technology Roadmap Semiconductors 2006 Update, Li-thography. http://www.itrs.net/Links/2006Update/FinalToPost/08_Lithogra-phy2006Update.pdf.
2. M. Janakiram, “ITRS Factory Integration Presentation,” Presentation to Create, Arizona State University, January 2007, http://create.asu.edu/calen-dar2/pdfs/ITRS_Factory%20Facilities_Jan2007.pdf.
3. P. MacDonald,“In situ thermal measurements for Cu barrier seed deposi-tion,” OnWafer Technologies, Inc., 2005.
4. L. Zambov, K. Weidner, V. Shamamian, R. Camilletti, U. Pernisz, M. Loboda, G. Cerny, D. Gidley, H Peng, R. Vallery, “Advanced chemical vapor deposition silicon carbide barrier layer technology for ultralow permeability applications,” JVST A Vol 24(5) September 2006 pp. 1706–1713.
5. A. Callegari, P. Jamison, D. Deumayer, F. McFeely, J. Shepard, W. An-dreoni, A.Curioni, C. Pignedoli, “Electron Mobility dependence on annealing temperature of W/HfO
2 gate stacks: the role of interfacial layer,” Journal of
Applied Physics, Volume 99, 2006.
6. H. Hocheng and Y.L. Huang, “In situ endpoint detection by pad tempera-ture in chemical mechanical polish of copper overlay,” IEEE Transactions on Semiconductor Manufacturing, Vol 17, No 2 May 2004 pp. 180–187.
7. S. Wang, P. MacDonald, M. Kruger, C. Spanos, M. Welch, “CD uniformity improvement and IC process monitoring by wireless sensor technology,” IEEE 2004.
8. I. Husala, K. Enke, H. Grunwald, G. Lorenz, H. Stoll, “In situ silicon wafer temperature measurements during RF Ar-ion plasma etching via flouroptic thermometry,” J. Phys D Applied Physics 20 (1987) pp. 889–896.
9. P. MacDonald and M. Kruger “Component health monitoring and diagnos-tics in plasma Etch Chambers using in-situ temperature metrology,” SEMI® Technical Symposium: Innovations in Semiconductor Manufacturing (STS: ISM) 2004.
10. Brown, T. Schrock, K. Poolla, M. Welch, P. MacDonald “Rapid diagnostics of etch processes in high-volume production using temperature metrology,” Semiconductor Manufacturing. Volume 4(10), pp.140–156, October 2003.
11. G. Roche, P. Arleo, P. MacDonald, “Wafer based diagnostics for dielectric etching plasmas,” Northern California AVS, Meeting of Plasma Etch Users Group, May 2007, http://www.avsusergroups.org/peug_pdfs/PEUG_07_5_
Roche.pdf.
Metrology
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
With the advent of new materials and structures at the 65 and 45nm nodes, demands on thin film metrology are increas-ing in complexity while metrology budgets get tighter. In several key processes, it is no longer sufficient to monitor just thickness and refractive index for process control. One must measure or infer composition, porosity, and other parameters for effective process control. Using the systematic variation of optical properties with these parameters, recent advances in the application of spectroscopic ellipsometry (SE) have led to the successful adoption of this technique in R&D and produc-tion for monitoring composition in varied materials like high-k gate dielectrics, nitrided gate oxide and boron-doped silicon germanium (SiGe:B). There are important process control
challenges and requirements for handling new materials and complex structures, and new applications data and potential solutions using optical thin film metrology will be discussed.
Multiple-Front Challenges
There is almost universal agreement that at the 65nm and 45nm nodes, films metrology is getting more complex and intensive (Figure 1). Along with the usual tightening of pro-cess windows and metrology budgets (a general rule of thumb is that the total films’ metrology budget should be <10% of the process budget), this is driven by two other factors: the introduction of many new materials and innovative structures1-5 in both the front end and the back end, and the migration of metrology from proxy measurements of films on monitor wafers to measurements on product wafers.
At the front end, many new materials introduce new chal-lenges for metrology and process control. The challenges begin with the gradual migration from Si to silicon-on-insulator (SOI) substrates. These changes generate new requirements: SOI substrates require monitoring of the thickness and uni-formity of the thin superficial silicon layer and buried oxide. The use of SOI substrates also makes it much more difficult to measure gate dielectrics and multilayer structures. The fact that superficial Si is transparent at HeNe wavelength (633nm) makes this a multiparameter measurement (simultaneously measuring gate oxide, superficial Si, and buried oxide), which is impossible with standard fixed-angle, single-wavelength ellipsometry (SWE).
Multiple approaches are being pursued to introduce strain in the Si channel. These include the use of SiGe:B (need to monitor Ge, B and SiGe:B thickness) in source/drain areas to compressively stress the channel, and the use of highly stressed nitride layers (monitor stress) to introduce tensile or compres-sive stress in the channel. The process control requirements
Metrology
Spectroscopic Ellipsometry Film Metrology Braces for 45nm and BeyondArun R. Srivatsa -– KLA-Tencor Corporation
Spectroscopic Ellipsometry (SE) is a key technology for production monitoring of films in today’s fabs. Advancements
in spectral fidelity, use of shorter wavelengths, and many other improvements enable SE technology to measure
thickness and refractive index, but also material composition in many films, including nitrided oxides, boron-doped silicon
germanium (SiGe:B) and high-k materials at the 65nm and 45nm nodes.
TiN
Ru
P
d Laminated Material Engineered M
aterial
SiO
C C
-SiO
2
Ultr
a-Lo
w-K A
LD-Barrier ALD-Seed Electroless Cu Engineered Material
SiON
PSG Cu Ta/TaN
Al W Ti T
iN T
iSixN y
BPS
G
W H
fO2 AL
2 O3 SiO
2 S
iOxNy
P
oly
W
Six
HfO
2
Al 2
O 3
Al2O3+HfO2 BST Ni Ti Co
SiOx N
y SiO2
Poly
WSi x
Si 3N4
Poly
SiO2
HDP-Ox
SO
I SiG
e
Si-Epi
Isolation
Transistor
Capacitor
Interconnect
Substrate
Figure 1: Many new and highly complex materials are being introduced at a faster rate compared with previous technology nodes.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
and methods vary depending on the path used. Gate oxide dielectrics are becoming thinner and more heavily nitrided, requiring control of both thickness and nitrogen in the oxide.
High-k gate dielectrics will most likely be first introduced at the 45nm node. Candidate materials like HfSiO
xN
y require
the monitoring of multiple elements/compositions simulta-neously for effective process control. Along with the difficulty of monitoring more variables, the allowed variation for each of these variables typically gets tighter, since the error bars from these parameters can add up to consume the total metrology budget. There are additional challenges associated with high-k metrology, including monitoring the metal gate electrodes and the interfacial layer between the high-k dielectric and silicon. In the front end, bilayer and nanolaminate-based high-k material stacks for capacitors are also being introduced.
While there are many more challenges arising in the front end, the introduction of low-k materials and copper also brings sig-nificant challenges to the back end. The use of low-k C-doped oxides (CDO) with the associated barrier and etch stop layers demands tighter metrology control with more complex stacks. Porous low-k dielectrics add complexity since, while it appears at this time that pore size and pore distribution are parameters that may not be required for production monitoring, an estimate of porosity and/or dielectric constant is required for production control.
The trend toward product wafer metrology is driven largely by a desire to eliminate monitor wafers, especially at 300mm. In some instances, in-die measurements are required for process control due to a lack of correlation between variations in the die and larger features in the scribe lanes.6 Product wafer measurements are usually done on large pads in the scribe lane.
As geometries shrink, many critical processes are impacted. In shallow trench isolation (STI), for example, there is a marked lack of correlation between CMP rates on pads in the scribe lane and CMP rates in the die. For process control in STI, in-die measurements of oxide and nitride film stacks are required.
Solving Film Metrology Problems
Optical thin film metrology, largely based on SE, is used ex-tensively for process control throughout the fab. SE is a rapid, nondestructive technique used for both monitor and product wafer measurements. The SE technique comprises two key ingredients: hardware with good spectral fidelity to extract information from the films and applications expertise to create viable solutions using the spectral information and algorithms tools. Recent advances on both fronts have led to viable SE-based solutions for applications like compositional monitoring of complex films in both R&D and production environments.
The primary improvements from a hardware perspective are improved optics design, leading to better spectral fidelity, and extension of SE to DUV wavelengths (down to 150nm). Com-bined, these two factors are important because the extension to DUV wavelengths enables the extraction of more information from the thin dielectric films that have more absorption at these wavelengths, while spectral fidelity gives better resolu-tion and minimizes the metrology error bars, helping to satisfy increasingly stringent requirements.
The quality of spectral fidelity can easily be determined by evaluating the spectral errors (differences between measured spectra and theoretical spectra) from a thin oxide film. As an example using KLA-Tencor’s tools, examine the spectral quality of two generations of production SE systems (Figure 2). The errors
Metrology
0.02
0.01
0.00
-0.01
-0.02
-0.04
-0.03
300 400 500 600 700
0.03
0.02
0.01
0.00
-0.01
-0.02300 400 500 600 700
SEα
SEα
SEβ
SEβ
0.03
0.02
0.01
0.00
-0.01
-0.02300 400 500 600 700
0.02
0.00
-0.02
-0.04
ASET-F5x SpectraFx
Error-SE1
Error-SE2
Error-SE3
Error-SE4
Error-SE5
Residual spectral errors
300 400 500 600 700
Figure 2: Residual spectral errors are close to zero across all wavelengths, and the residual error signature is repeatable in newer generations of SE systems.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
are plotted on the same scale in both sets of graphs. It is seen that the residual errors on the newer SE systems are consider-ably smaller across all the wavelengths and close to zero. The magnitude of the errors on these production tools was found to be comparable to that of errors from a research-grade system using a similar test. Equally as important, it is seen that the “signa-ture” of the remaining small residual errors on the latest SE tools is virtually identical from one system to another. From a spectral standpoint, the measurement hardware is in-trinsically matched. High spectral fidelity and system-system spectral matching are key factors for meeting the extremely tight requirements on the most challenging film applications.
Any discussion of optical monitoring of thin gate dielectric films must address the issue of airborne molecular contami- nation (AMC). Detailed discussions are available for those
interested in pursuing the matter in more detail.6 Using ellipsometric techniques and a desorber to address AMC, a viable production-proven solution has been formulated for monitoring the thickness and nitrogen concentration (%N) in thin SiON gate dielectrics. The solution has repeatedly demonstrated good correlation between the measured SE parameter and %N baseline data across wide DoE. This type of optical solution is currently implemented successfully at several fabs worldwide.7
High-k Gate Optical Metrology
Candidate materials are largely Hf-based oxides or silicates and include HfO
2, HfSiO
x and HfSiO
xN
y. With these ma-
terials, there is typically an interfacial layer about 5–10Å thick between the 20-40Å high-k dielectric and silicon. The interlayer has a lower dielectric constant than the bulk high-k material. Process control schemes typically rely on thickness and composition monitoring of bulk high k dielectric, coupled with electrical monitoring of the interface between the high-k dielectric and silicon. These high-k materials’ optical proper-ties vary systematically with composition. At lower wave-lengths, especially in DUV down to 150nm, there is increased sensitivity to these materials due to increased absorption. Using this information, and by leveraging recent advances in the hardware, algorithms and applications methodologies, SE can simultaneously monitor two compositional parameters.
Figure 3 shows examples of optical measurements of composi-tion in high-k films in a development fab. Figure 3a shows results across an HfSiO
x DoE. In this case, SE was used to
map and output %SiO2 in the HfSiO
x films. A wide range of
compositions, nearly 50% SiO2 variation in the HfSiO
x, were
sampled across a DoE with multiple wafers. X-ray photoelec-tron spectroscopy (XPS) was used as the reference technique. Measurements at 21 sites were carried out across each wafer (from center to edge) in the DoE using both XPS and SE. DUV wavelengths down to 150nm were used to build up the optical models. The results show a strong correlation between the SE output for composition and the XPS baseline across the DoE and within each wafer in the DoE. For the HfSiO
xN
y
films (Figure 3b), a recently developed algorithmic model was used to simultaneously compute both %SiO
2 and %N in the
film. As with the HfSiOx films, 21 site measurements were
carried out across each wafer in the DoE to verify capability to track compositional variation within each wafer across the wide range of compositions in the DoE. Again, there is good correlation with the baseline across the wide range of composi-tions sampled in the DoE.
Monitoring Bilayer Structures
As with the high-k materials, there is a systematic variation in optical properties of SiGe with increasing Ge concentration. The presence of boron (B) at high dopant concentrations has a secondary effect on the optical properties. Using a DoE with relatively constant B concentration (with some variation) and a systematic variation in Ge concentration, an SE-based optical solution was formulated to measure both single-layer SiGe:B
Metrology%
SiO
2 (S
E)
%SiO2 in HfSiOx
%SiO2 (XPS)
a)
50%SiO2
y = 0.9881x + 1.0923R2 = 0.9954
y = 0.8012x + 11.828R2 = 0.9096
y = 1.1088x + 1.0751R2 = 0.9676
b)
%N
(SE)
%N
%N (XPS)
8%N
%Si
O2
(SE)
%SiO2
%SiO2 (XPS)
25%SiO2
SE vs XPS
Figure 3: (a) Tracking composition in HfSiOx films with SE; (b) Simul-taneous determination of two compositions in HfSiON films with SE.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
and bilayer Si-cap/SiGe:B/Si structures using the same recipe. The SiGe:B and Si-cap layers’ thicknesses were simultaneously measured along with Ge concentration in the SiGe:B layer. Here, X-ray diffraction (XRD) and secondary ion mass spec-trometry (SIMS) were used as baseline techniques. As with the other applications described earlier, excellent correlation was achieved between the optical measurement of Ge concentration and the baseline techniques.
The ability to track multiple parameters simultaneously in a production environment can be seen from the results in Figure 4. Results from a four-wafer DoE with roughly similar SiGe:B and Si-cap thicknesses, but varying Ge concentration, are plotted. Measurements were carried out from the center to the edge of the wafer using a standard nine-site Prometrix pattern. The nominal thickness of the SiGe:B layer was in excess of 1000Å, with a thin Si cap layer. Within the nine-site pattern, the signature of the reactor was reproduced for the SiGe:B and Si-cap thicknesses at varying Ge concentrations. The data from three tools in a production environment also show that the results for the different parameters are well matched. Such tool-tool matching is possible because of the spectral fidelity described earlier.
Ultra-thin ONO Film Stack Metrology
Thin oxide/nitride/oxide (ONO) film stacks are used in both DRAM and Flash memory stacks. At the 90nm node, the target for the nitride thickness of floating-gate Flash is around 50Å (and may be as low as 30Å for 65nm). This is a challeng-ing measurement due to extremely high correlation demands between the top and bottom oxide layers. The extent of the correlation is driven by the thickness of the nitride layer separat-ing the two oxides, since correlation increases significantly as the nitride gets thinner. Because the nitride film has increased absorption characteristics at shorter wavelengths, use of shorter wavelengths increases the contrast between the top and bottom oxides. To enable these measurements, SE technology must be extended down to DUV wavelengths (190nm) for ONOs with the nitride at 50Å, and down to VUV (150nm) for ONOs with nitrides down to 30Å.
The capability of both 190SE and 150SE systems to accurately track the introduced process changes was monitored. It is seen that both the systems accurately track the nitride thickness. The 190SE system shows a flat response for the top and bottom oxide thickness down to a nitride thickness of 50Å, but begins to show deviations and correlations between the oxides when the nitride thickness is lower. The 150SE system, on the other hand, shows a flat response for the top and bottom oxide thicknesses for the entire DoE, per the design. So for thin ONO stacks with the nitride thickness below 50Å, 150SE capability is recommended to monitor the process.
Multilayer, Multiparameter Measurements
Table 1 (next page) shows an example of the type of measure-ments achieved using advanced systems with high spectral fidelity and robust algorithms. In this measurement of a
six-layer, low-k BEOL film stack, a seven-wafer DoE was carried out to evaluate the measurement’s robustness in cor-rectly predicting the introduced changes with a single recipe. Sixteen parameters were measured simultaneously: thickness, n, and k for all the layers except the top oxide layer, where only the thickness was measured. The refractive index was not measured for the oxide layer on top since this is usually well controlled. It is seen that—with a single recipe—the various changes simultaneously introduced in this seven-wafer DoE can be correctly predicted. The circles in different colors outline missing layers, double-deposited layers, half-deposited layers, and layers with a random variation in thickness.
The migration of metrology from monitor wafers to product wafers is being accelerated with the introduction of 300mm wafers. On monitor wafers, it is easier to keep the metrology simpler and monitor individual films or processes. Product wafers call for the added requirement to monitor the same films and processes in multilayered stacks. Metrology requirements for individual films and processes are unchanged, though the
Metrology
Si-c
ap t
hick
ness
(Å)
%Ge in the SiGe:B layer in Si-cap/SiGe:B/Si
Multiple parameter tracking
%G
e
Si-cap thickness in Si-cap/SiGe:B/Si
Tool A
Tool B
Tool C
Tool A
Tool B
Tool C
Tool A
Tool B
Tool C
SiGe:B thickness in Si-cap/SiGe:B/Si
SiG
e:B
thic
knes
s (Å
)
Nom + 40Å
Nom
Nom - 40Å
Nom + 150Å
Nom
Nom - 150Å
10%range
wfr1
wfr2
wfr3
wfr4
wfr2wfr3 wfr4
wfr1 wfr2 wfr3 wfr4
wfr1
Figure 4: Simultaneous measurement of thickness of Si-cap and thickness and composition of SiGe:B layer across Ge concentration DoE with SE. Good tool-tool matching in a production environment is especially important.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
measurement is more complicated since more parameters must be simultaneously measured in a film stack. Spectral fidelity and tool-tool spectral matching become more critical for multilayered films. The above example for the measurement of multiple parameters in a six-layer stack illustrates the evolution of this capability. It must be noted, though, that in typical production environments one does not measure so many parameters simultaneously.
SE into the Future
SE continues to be the technology of choice for production monitoring of films in today’s fabs. The continual advance-ments in spectral fidelity, extension of SE to lower wave-lengths, and improvements in hardware, algorithms, and applications capabilities are enabling the use of SE technology to report additional parameters like compositions in very thin to thick films, potentially satisfying the increasingly complex metrology requirements at the 65 and 45nm nodes. Opti-cal film metrology solutions based on SE are currently being adopted to monitor composition in several complex processes involving nitrided oxides and SiGe:B, and in the development of high-k materials. Recent technology advances on multiple fronts are also facilitating the accelerated migration to product wafer metrology and multiparameter, multilayer measure-ments throughout the fab. With these continued advances, SE-based films metrology could continue to be the workhorse technology for production metrology at 45nm and beyond.
Acknowledgements
The author wishes to thank several colleagues for detailed technical discussions on several metrology topics and for making available many of the figures used. They include Arun Chatterjee, Torsten Kaack, Zhengquan Tan, Sungchul Yoo and Shankar Krishnan from KLA-Tencor; and Simona Spadoni, Rosella Piage and Davide Lodi from ST Microelectronics.
Note: This article was originally published in Semiconductor International magazine, December 2006.
References
1. International Technology Roadmap for Semiconductors, http://www.itrs.net.
2. Y.-C Yeo, Q. Lu, T.-J King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro and J. Sakai, Proc of the International Electron Devices Meeting (IEDM), p. 753, 2000.
3. H. van Meer and Kristin De Meyer, 2002 Symp. on VLSI Technology, Digest of Technical Papers, p. 170 2002.
4. H.S.P. Wong, IBM Journal of Research and Development, V46, N2/3, 2002.
5. David Lammers, EE Times, 4/4/2005. http://www.eetimes.com/showArticle.jhtml?articleID=160401538.
6. Arun R. Srivatsa, Yield Management Solutions, Winter 2005, p. 22.
7. Sungchul Yoo, Zhiming Jiang, Eric Wang and Zhengquan Tan, YMS Seminar, Semicon West, San Francisco, July 2006.
Metrology
MeanRI @ 633 nm
MeanThickness
MeanRI @ 633 nm
MeanThickness
MeanRI @ 633 nm
MeanRI @ 633 nm
MeanRI @ 633 nm
MeanThickness
MeanThickness
SiC
(2)
Low
-KSi
C(1
)Lo
w-K
SiN
MeanThicknessOx
Thickness Mean
Wafer 3
1.4042
526.7
2.0443
613.6
1.7370
1.3805
1.8472
2513.1
419.6
9.9
2491.6
Wafer 4
1.3907
526.2
2.0361
647.2
1.7075
1.3662
1.8368
2575.5
789.4
1007.5
2551.3
Wafer 5
1.3925
515.6
2.0572
617.0
1.7193
1.3785
1.8418
1238.1
412.9
1019.9
2501.1
Wafer 6
1.4069
521.3
2.0526
593.9
1.7210
1.3713
1.8441
4939.2
418.4
1045.4
2468.0
Wafer 7
1.4153
559.3
2.0594
649.4
1.7095
1.3647
1.8394
2561.6
363.3
1001.3
56.4
Wafer 1
1.3943
524.0
2.0350
653.4
1.7161
1.3807
1.8548
2568.9
423.4
650.6
1266.1
Wafer 2
1.3923
529.2
2.0317
577.3
1.7224
1.3640
1.8384
2640.4
414.8
1048.5
4921.4
Seven-wafer DoE of six-layer low-k stack
Table 1: Robustness of measurement of this six-layer low-k stack across a seven-wafer DoE was tested by randomly introducing missing layers, double-deposited layers, half-deposited layers and other variations in the film stack.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Metrology and inspection steps usually account for about 5% of a wafer fab’s total cycle time, but the value they provide in terms of improved yield is typically an order of magnitude greater than the cycle time cost that they impart to the process. However, a cycle time management program, to be success-ful, must be a fab-wide activity with equal attention paid to reducing the cycle time at every toolset in the fab. In recent years there has been a trend in wafer fabs away from maximiz-ing tool utilization, which reduces cost per wafer, and toward minimizing cycle time, which increases revenue and profit. The two objectives are at odds with each other, as decreasing utilization decreases cycle time but also decreases producti-vity. The optimal operating point is one that strikes a balance between the two.
Reduced cycle time (CT) has many benefits; the primary one is faster time to market. The price of nearly all semiconduc-tor products, DRAM, Flash, Logic, etc., declines rapidly over time - typically from 50% to 80% per year from the time the product is first released. Shorter CT ensures less decline in price from the time the product enters manufacturing to the time it reaches the market, thereby commanding a higher ASP. The other benefits revolve around having shorter cycles of learning (COL) and reduced work in progress (WIP). In R&D shorter COL equates to shorter development time and, when transferred to production, faster yield ramp. The relationship between WIP and CT is expressed through what is called Little’s Law:1
WIP = (CT) x (Start Rate)
From the equation above it can be seen that, for a given start rate, the WIP will decrease linearly with CT. The advantage of this are that there are fewer lots in the fab at any given time, which reduces overhead, exposes fewer lots to any required process changes, and reduces the number of lots at risk during any yield excursions that may occur. Carrying less WIP also means there are fewer unfinished goods on hand when the
market turns down. One of the best value statements for cycle time was summarized by Clayton Christensen2 who said,
“Extending development an extra day, to get a stepper or process qualified, is like paying $3.44 for every wafer that the factory will make. In addition, if it takes one more day to reach mature die yield, it is like paying $1.35 for every wafer that will be made, or if the cycle time is one day longer, it is like paying $3.04 per wafer.”
From this quote we can get a feel for the value of CT, which is approximately $1 million per year for every day of CT reduction (30,000 WSPM x 12 months x 3.04 per wafer = $1.1 million per year).
Mathematically, CT is equal to the queue time (the time a lot spends waiting to be processed) plus the processing time (the time it spends in the tool). The processing time is a straight forward calculation but the queue time (QT) is the product of three separate functions.3
QT = {ƒ(Variability)} {ƒ(Utilization)} {ƒ(Availability)}
There is no single correct version of the equation above; it comes in several incarnations with varying degrees of complexity depending on the level of detail one wishes to incorporate. However, essentially all the mathematical expressions of QT have the following four features in common:
1) A system with no variability has no queue time: when ƒ(Variability)=0, QT=02) ƒ(Utilization) is proportional to 1/(1-Utilization): CT increases exponentially with increased utilization.3) ƒ(Utilization) is also proportional to 1/(# of tools): CT decreases with more tools.4) ƒ(Availability) is proportional to 1/(Avail-ability): CT decreases exponentially with increased availability (uptime).
fab econoMics
Reducing Cycle Time Has Many BenefitsDoug Sutherland – KLA-Tencor Corporation
As consumer electronics increasingly drive fab economics, cycle time of wafers within the fab largely determines the
time to market of semiconductor products. Decreased cycle time and increased operational efficiency can provide higher
availability and speed time to market in the wafer fab environment.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Low utilization and high availability do not in themselves en-sure that the CT will be low; only by eliminating all sources of variability can one guarantee that the QT will vanish. Mathe-matically, variability is measured as the standard deviation of a system divided by its average. In a wafer fab variability comes from three main sources:
1) Variability in the lot arrival rate2) Variability in the lot processing time3) Variability in the downtime of the tool
Figure 1 shows the operating curve (a plot of CT vs. utilization) for identical toolsets with one to five tools assuming unit varia- bility and 100% availability. The salient point here is that changing from one tool to two does much more than simply double the capacity. For the same CT as one tool at 60% uti-lization, you can run two tools at nearly 80% utilization. Not only do you have twice as many tools but each one of them is processing about 30% more wafers — a 260% improvement. The impact of having n+1 tools is less dramatic with larger toolsets but the same principle applies and this is one of the underlying tenets of the economy of scale enjoyed by larger wafer fabs. Large fabs generally have lower CT and lower cost per wafer because they can run their tools at higher utilization without climbing into the steepest part of the operating curve.
In addition to the number of tools, the other first-order effects on CT are the related variables, availability and utilization. If we artificially set availability and utilization to 95% and 85%, respectively, we can see some interesting and unexpected trends in cycle time. For instance, for a given availability, CT actually increases with increasing MTBI. That is, it is better to divide the same downtime into many short events (low MTBI and low MTTR) rather than fewer long events (high MTBI and high MTTR), as shown in Figure 2. This isn’t a problem in terms of tool design, as we usually make the assumption that higher MTBI (fewer system-down events) equates to higher availability. However, from a service perspective we
often adopt the pragmatic philosophy that “if we’re here to fix Problem A we might as well do adjustments B, C and D at the same time.” This well-intentioned approach increases the tools MTBI and MTTR but does not substantially improve the availability (i.e., the total repair time remains unchanged) and consequently increases the CT. Often our best intentions tend to be counter-intuitive (and counter-productive) in terms of reducing our customer’s CT.
Another interesting case is that of matching, as having dedi-cated (or “golden”) tools is one of the worst things for CT. Figure 3 shows the impact to CT of having five matched brightfield inspection tools inspecting five layers in the process versus 4 matched tools inspecting four layers and one dedicated (golden) tool inspecting one layer (for the sake of simplification this assumes 100% sampling). Instead of having five layers all experiencing cycle times represented by the operating curve for five tools (see Figure 1) you have four layers with cycle times represented by the curve for four tools and one layer with a CT represented by the curve for a toolset with only a single tool. The net effect of unmatched tools in this case is to double the total CT for that toolset (Figure 3). Fabs can mitigate the effect of this by treating the tools as if they were matched whenever the golden tool is unavailable (i.e., instead of holding the lot to wait for the golden tool they run it on one of the other tools), but this comes at the cost of increased beta risk.
fab econoMics
0
1
2
3
4
5
6
0% 20% 40% 60% 80% 100%
Utilization
Cyc
le T
ime
( x
Pro
cess
Tim
e)
1 Tool2 Tools3 Tools4 Tools5 Tools
Figure 1: Cycle Time vs. Utilization for a toolset with 1 to 5 tools. Units of CT are in multiples of the tool’s processing time. Large fabs with more tools in each toolset have an advantage because they can run at higher utilizations without as much impact on CT.
0.0
1.0
2.0
3.0
4.0
50% 60% 70% 80% 90% 100%
Utilization
Cyc
le T
ime
(Day
s)
1000 Hrs MTBI
100 Hrs MTBI
Figure 2: Cycle Time vs. Utilization for two toolsets with the same avail-ability (95%) but different MTBI (and MTTR). From a CT perspective, for the same availability, it is better to have many short down events (MTBI = 100 Hrs) than comparatively fewer long ones (MTBI = 1000 Hrs). The difference in this example is about 1 day at 85% utilization.
Large fabs generally have lower CT and lower cost per wafer
because they can run their tools at higher utilization without
climbing into the steepest part of the operating curve.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Service contracts provide a threefold advantage for cycle time management. First and foremost, they increase the availability of the tool. This in turn has the added advantage of automati-cally reducing the utilization (utilization is equal to produc-tion time divided by available time). Finally, service contracts significantly reduce the variability in the downtime, which itself is a significant contribution to CT. Figure 4 shows the operating curves for six brightfield inspection tools under two different conditions: one where their reliability characteristics are typical of billable tools and the other where the six tools are covered under a service contract. The faster response time (less time down, higher availability) and the reduced variability in the downtime result in a CT reduction of about 1.9 days. Another key factor is that because utilization is equal to the production time divided by the available time, a toolset run-ning at 85% utilization while billable can be run at about 82% utilization under service contract.
As the IC industry becomes increasingly driven by consumer electronics, cycle time (or equivalently, time to market) will become ever more important to wafer fabs as they strive to produce exactly the right amount of product at exactly the right time. Being the first IC manufacturer to provide engineering samples to a prospective customer can result in design wins that could literally make or break its business. Similarly, being caught with hundreds of millions of dollars worth of WIP still in the pipeline when the market enters a downturn or when the consumer simply moves on to “the next new thing” can make the difference between a year that closes with a profit and a year that closes with a loss. There are, and will continue to be, niches within the IC industry where cycle time is less important, but the general trend for the foreseeable future is in the direction of decreased cycle time and increased operational efficiency. As a result of this, more emphasis will be given to products and services that provide higher availability and that reduce variability in the wafer fab environment.
References
1. W.J. Hopp and M.L. Spearman, McGraw-Hill, “Factory Physics”, 2001, p. 223.
2. Clayton Christensen, “Solid State Technology”, August 2001.
3. W.J. Hopp and M.L. Spearman, McGraw-Hill, “Factory Physics”, 2001, p. 325.
fab econoMics
0.0
1.0
2.0
3.0
4.0
50% 60% 70% 80% 90% 100%
Utilization
Cyc
le T
ime
(Day
s)
Billable
Contract
Figure 4: The cycle time impact of converting six brightfield tools from billable to service contract. The increased availability achieved by having the tools on contract flattens out the operating curve and also contributes to lower utilization (utilization equals production time divided by available time). For tools that are at 85% utilization when billable, a service contract can reduce the cycle time by 1.9 days.
0.0
1.0
2.0
3.0
4.0
50% 60% 70% 80% 90% 100%
Utilization
Cyc
le T
ime
(Day
s)
1 Golden & 4 Matched
5 Matched Tools
Figure 3: Dedicating layers to specific “golden tools” creates a “single tool” environment (see Figure 1) and causes a dramatic increase in cycle time that is exacerbated at higher utilizations. In this case the cycle time almost doubles as a result of having unmatched tools.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
A new reticle inspection platform, the TeraScanHR, improves upon the prior TeraScanTR platform with higher optical imaging resolution to better resolve small features; higher precision database modeling to better represent small OPC in die-to-database inspection; and higher speed image processing for higher productivity, especially when using integrated modes (e.g., transmitted + reflected). Besides its 45nm capability, the TeraScanHR platform can also be configured for 65nm, 90nm, and 130nm nodes.
This paper describes technical aspects of the TeraScanHR platform and presents selected results from the field testing of beta systems located at Toppan Printing in Japan and the Advanced Mask Technology Center in Germany. The testing used applicable programmed defect test reticles to measure defect detection sensitivity, along with a large set of product and product-like reticles from the 90nm to the 32nm logic nodes, and comparable memory nodes, to assess both sensi-
tivity and inspectability when using the available pixel sizes (72/90/125/150nm). The beta systems are currently being used for advanced production.
Reticle Inspection Development
To serve the 45nm node advanced production requirements and 32nm node development requirements, the TeraScanHR platform delivers higher performance and new capabilities. This platform can be configured as a variety of different models that are intended to cost-effectively inspect reticles from the 130nm node to the 32nm node. In this way, a reticle manu-facturer or wafer fab can purchase just the capability needed at the time, and then upgrade as more capability is needed in the future. A typical TeraScanHR system is shown in Figure 1 (note that the three electronic racks may be remotely located).
The new system’s imaging technology uses significantly higher resolution imaging of the reticle than the wafer lithography system, allowing direct inspection of both the primary struc-tures and the sub-resolution structures; its single wavelength can provide good performance inspecting reticles from a variety of lithographic wavelengths. The TeraScanHR handles typical binary (COG), 6% EPSM (including simple tri-tone), and dark field alternating PSM reticles. The system supports both transmitted and reflected light inspection modes, which can be easily integrated into a single inspection.
Using the new 72nm pixel, the system enables development of 32nm logic reticles and approximately 45nm half-pitch memory reticles. Additional capability extensions are in de-velopment for more aggressive RET, such as Mask Enhancer, complex tri-tone, and chromeless. Larger pixels are available with faster scan times for the 65nm logic node up to the 130nm node.
Mask
Field Results From 45nm Die-to-Database Reticle InspectionWilliam Broadbent, Ichiro Yokoyama, Paul Yu, Heiko Schmalfuss, Jean-Paul Sier – KLA-Tencor CorporationRyohei Nomura, Kazunori Seki – Toppan Printing Co., LtdJan Heumann – Advanced Mask Technology Center GmbH & Co
Testing of the TeraScanHR system at Toppan and the AMTC demonstrated high sensitivity, low false detections, and high
scan speed. The system’s higher NA optics, new autofocus, smaller pixel size, and improved rendering and modeling
algorithms resulted in significant improvements in inspection capability of small linewidths, small defects, and aggressive
OPC. Reflected light inspection integrated with transmitted light can be used with no additional scan time for some modes,
providing the best defect detection capability and resulting in the highest quality reticles.
Figure 1: The new TeraScanHR system enables 45nm generation mask inspection.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Image Acquisition
The image acquisition subsystem is shown in Figure 2. A high-resolution microscope and linear sensor architecture are used with both transmitted and reflected illumination paths.
The illumination source is a 257nm wavelength continuous wave (CW) laser (>5,500 hours lifetime). An active beam steering subsystem compensates for beam drift. The transmit-ted illuminator has several different configurations that can be selected by the user. Two illuminator configurations are currently implemented: standard contrast for COG and EPSM reticles, and phase contrast for quartz etch reticles such as al-ternating, Mask Enhancer, chromeless, etc. The phase contrast mode provides improved imaging contrast to quartz phase de-fects (bumps and divots), allowing for higher defect sensitivity.
The custom-designed objective images the reticle surface through a zoom lens onto the imaging sensor. The zoom lens allows different pixel sizes to be selected by the user at runtime; this provides faster scan times when a less sensitive inspection is desired – four pixel sizes are available depending upon the model (72, 90, 125, and 150nm). Image pickup is done with a time-domain-integration (TDI) sensor, which of-fers high-speed continuous image pick-up at much lower light levels than a conventional CCD linear sensor.
For reflected light inspection, the system uses a single imaging sensor with a switching device to select between transmit-ted and reflected illumination. This allows an integrated inspection using both transmitted and reflected illumination (integrated T+R mode). Since each illumination mode has the best performance for different classes of defects and different geometry types, the integrated T+R mode provides the highest quality inspection.
To achieve the needed performance level, the new system pro-vides a higher NA capability to resolve smaller lines, OPC, and defects (approximately 1.2 times higher NA than the previous 90nm pixel TeraScanTR platform). The higher NA supports the new 72nm pixel. A new autofocus subsystem provides the necessary precision for the higher NA optics, which have lower depth of focus; an advanced pre-mapping technique improves the ability to maintain proper focus, especially when inspecting reticles with significant topology such as the quartz etch types.
Image Processing
The TeraScanHR image processing subsystem features a Tera Image Supercomputer, which utilizes a fully programmable and scalable multi-processor architecture using high-speed processors.
The basic detection method is to overlay a test image with a matching reference image and identify differences above a pre-selected size; since the images should basically match, any differences are the result of a defect. For die-to-die inspection, the test and reference images compared are from adjacent die; for die-to-database inspection, the reference image is recon-structed from the design or write database. For a STARlight inspection, the transmitted light image is compared to the reflected light image – any differences are the result of a con-tamination-type defect.
The new image computer uses higher speed processors and contains 2x the number of processors compared with the previous image computer. The additional processing power improves scan time for the more processing-intensive modes; this can also allow multiple modes to be processed together with minimal inspection slowdown. For example, a transmit-ted light inspection and a reflected light inspection can be processed together without slowing the inspection station; this allows a much more cost-effective T+R inspection than the prior TeraScanTR system.
Additional processing blocks for die-to-database inspection reconstruct a database image in real time from the reticle design or write database. Sophisticated modeling algorithms ensure that the database image exactly matches the optical image since any error reduces defect detection sensitivity. A new die-to-da-tabase defect detection algorithm, UHR, provides much more precise modeling of small OPC structures in both transmitted and reflected light as compared to the previous algorithm. The test image is subtracted from the reference image to produce a difference image. Since the test and reference images should exactly match, the difference image should have a uniform gray background except where there is a defect.
Test Results
Four months of field testing and tuning at Toppan Printing in Japan and the Advanced Mask Technology Center (AMTC) in Germany provided extensive verification of system performance. Each beta site verified the sensitivity and false detection perfor-mance using K-T’s standard programmed defect test reticles, as
Mask
TDI Sensor
Condenser
Photomask
Objective
ReflectedIllumination
TransmittedIllumination
DUVLaser Source
Reflected Image
Transmitted Image
Figure 2: High resolution transmitted and reflected images show that the sub-resolution clear serifs are fully imaged and clearly visible. An oversize clear serif defect is present and visible in both the transmitted and reflected images, whereas a particle on the dark material is also present but is only visible in the reflected light image (dark spot).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
well as unique test reticles from each site. The customers’ test reticles contained geometry patterns typical of the 32nm, 45nm, and 65nm logic nodes, as well as the 5xnm half-pitch memory node. These reticles were tested at both maximum sensitivity settings and a variety of production settings.
Production-suitable detector settings were also determined by using a variety of product and product-like reticles from the 45nm, 65nm, and 90nm logic nodes and the 4xhp, 5xhp, and 7xhp memory nodes. These reticles were for ArF lithography and included primarily critical layers of 6% EPSM, with some dark field alternating PSM and EUV reticles. The testing demonstrated excellent full-area inspection of advanced product reticles with aggressive OPC, showing high sensitivity and low false detections.
Improved Imaging with New Image Acquisition
The improved optical imaging uniformity of the new system can be seen on small structures, such as SRAF. Figure 3 shows a comparison of SRAF difference image noise between the previous system (left side) and the new TeraScanHR (right side). These difference images are from the same 65nm node reticle using the 90nm pixel and the previous UCF die-to-database algorithm.
The lower noise and improved imaging uniformity are a result of the new autofocus subsystem, lower aberration optics, and lower vibration stage. In this example, there is still some noise in the difference image, which is caused by the older UCF algorithm and its limited modeling capability of small structures. The new UHR algorithm includes higher-precision modeling, which will result in lower noise difference images and lower false detection rates.
High Resolution and Improved Database Modeling
The new system’s high NA optics enable a new 72nm pixel that can resolve small OPC structures, small lines and spaces, and small defects. Figure 4a compares a small dark extension defect imaged with the previous 90nm pixel (left images) and the new 72nm pixel (right images). The 72nm pixel has about 40% higher modulation (note the larger size and darker signal in the difference image). Additionally, the 72nm pixel includes the new UHR family of die-to-database algorithms, which provide higher precision modeling, resulting in lower noise in the difference image and therefore lower false detection rates.
Figure 4b shows the difference image from a 45nm logic gate layer with aggressive OPC being imaged by the new 72nm pixel and the database modeled by the new UHR algorithm. The dif-ference image shows very low noise on this small geometry, which will result in low false detections and high detector settings.
Die-to-Database Sensitivity for 72nm Pixel
Figure 5 (next page) shows typical sensitivity performance in die-to-database mode using the KLA-Tencor Spica-200-193 programmed defect test reticle. This test reticle is standard 6% EPSM for 193 lithography and includes a typical semi-
Mask
45nm Logic
Poly Layer
6% Tri-tone
Aggressive OPC
72nm pixel
Database Transmitted
High detector settings
UHR Algorithm
Excellent matching of optical image and database model
Difference Image
Figure 4b: Higher resolution enabled by a new 72nm pixel, plus new database modeling, shows very low noise, low false detections and high detector settings on this small geometry.
Small lines & dark SRAF
Same pixel 90nm
Same algo UCF (old)
Prior Image Acquisition New Image Acquisition
Difference Image Difference Image
Improved imaging
Real defect
Optical & database matching errorsFalse detection
Better opticsNew autofocusImproved stage
Imaging limitations
Figure 3: Comparison of imaging small SRAF between prior image acquisition and new image acquisition.
Transmitted light Spica-200–193260nm dark line
Dark extentiondefect ~ 30nm
~ 40% more modulation than 90nm pixel
1.25x Mag
72nm Pixel90nm Pixel
Figure 4a: Comparison of imaging a small dark extension defect between 90nm pixel and 72nm pixel.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
wire programmed defect test section in multiple linewidths, the smallest being 260nm dark lines (shown). This result uses the 72nm pixel die-to-database with transmitted illumination and the standard high-resolution detectors set at maximum sen-sitivity (HiRes1 and HiRes2). Each gray box indicates 100% detection from 20 contiguous inspections. The upper number in the gray box is the defect size using the KLA-Tencor maxi-mum inscribed circle (MIC) sizing method from SEM images. The lower number is the detection percentage. For the smallest defect detected 100% in each column, the defect size is also shown in a larger font below the printed size for easier reading. Note that small pinholes are difficult to manufacture, so none were present on the reticle for this upper portion (NP=no defect present). Also, pinholes are best detected with reflected light rather than transmitted light due to imaging effects.
Toppan 45nm Process Level
The test reticles used at Toppan Printing were made with their latest 45nm process. This process showed significant improve-ments in linearity, corner rounding, and resolution versus the previous processes. Figure 6 shows a 57% improvement in linearity versus the previous 65nm process.
Defect Detection Performance using Toppan Programmed Defect Test Reticles
Toppan Printing designed two programmed defect test reticles for the purpose of testing advanced reticle inspection system performance (“Carbonate” and “Cyclics”). The Carbonate reticle
is a line/space design while the Cyclics is a hole design (360nm and 420nm). The Carbonate test reticle includes several rep-resentative patterns for line/space critical layers typical of the 45nm node. These patterns contain aggressive OPC designs with jogs, serifs, and SRAF and a variety of programmed defects on or near both primary geometry and OPC structures.
Figure 7 (next page) shows the defect detection performance of the 72nm pixel in the die-to-database and die-to-die transmit-ted light modes for the 45nm section of the Carbonate test reticle (selected defects shown) when using the maximum detector settings, and also when using production settings. The production settings were determined by inspecting more than 50 different patterns and selecting the tightest setting
Mask
90nm P65nm P45nm P
Target CD
∆ C
D
10
73%
57%
-10
-20
0
Figure 6: Toppan 45nm process with a 57% process linearity improvement.
Figure 5: Die-to-database transmitted 72nm pixel defect detection sensitivity with Spica-200-193 test reticle.
0.017µm
0.00%
0.000µm
0.00%
0.000µm
0.00%
0.000µm
0.00%
0.005µm
0.00%
0.005µm
0.00%
0.005µm
0.00%
0.005µm
0.00%
0.005µm
0.00%
0.005µm
0.00%
0.000µm
0.00%
0.000µm
0.00%
0.019µm
0.00%
0.000µm
0.00%
0.000µm
0.00%
0.000µm
0.00%
0.010µm
0.00%
0.010µm
0.00%
0.010µm
0.00%
0.010µm
0.00%
0.010µm
75.00%
0.010µm
95.00%
0.000µm
0.00%
0.000µm
0.00%
0.024µm
0.00%
0.015µm
0.00%
0.000µm
0.00%
0.018µm
0.00%
0.015µm
0.00%
0.015µm
0.00%
0.015µm
0.00%
0.015µm
5.00%
0.015µm
100.00%
0.015µm
100.00%
0.028µm
40.00%
0.000µm
0.00%
0.031µm
100.00%
0.022µm
0.00%
0.000µm
0.00%
0.030µm
0.00%
0.020µm
0.00%
0.020µm
0.00%
0.020µm
100.00%
0.020µm
100.00%
0.020µm
100.00%
0.020µm
100.00%
0.024µm
100.00%
0.000µm
0.00%
0.039µm
100.00%
0.031µm
100.00%
0.017µm
0.00%
0.030µm
0.00%
0.026µm
100.00%
0.026µm
90.00%
0.026µm
100.00%
0.026µm
100.00%
0.026µm
100.00%
0.026µm
100.00%
0.033µm
100.00%
0.000µm
0.00%
0.039µm
100.00%
0.031µm
100.00%
0.028µm
0.00%
0.033µm
0.00%
0.031µm
100.00%
0.031µm
100.00%
0.031µm
100.00%
0.031µm
100.00%
0.031µm
100.00%
0.031µm
100.00%
0.034µm
100.00%
0.000µm
65.00%
0.046µm
100.00%
0.039µm
100.00%
0.032µm
5.00%
0.036µm
100.00%
0.036µm
100.00%
0.036µm
100.00%
0.036µm
100.00%
0.036µm
100.00%
0.036µm
100.00%
0.036µm
100.00%
0.055µm
100.00%
0.033µm
80.00%
0.047µm
100.00%
0.046µm
100.00%
0.039µm
45.00%
0.017µm
100.00%
0.041µm
100.00%
0.041µm
100.00%
0.041µm
100.00%
0.041µm
100.00%
0.041µm
100.00%
0.041µm
100.00%
0.059µm
100.00%
0.044µm
100.00%
0.017µm
100.00%
0.017µm
100.00%
0.017µm
100.00%
0.047µm
100.00%
0.046µm
100.00%
0.046µm
100.00%
0.046µm
100.00%
0.046µm
100.00%
0.046µm
100.00%
0.046µm
100.00%
0.046µm
100.00%
0.046µm
100.00%
Edge Placement
CD
OutsideCorner
InsideCorner
Horizontal Extension
DiagonalExtension
31nm
31nm
36nm
26nm
31nm
20nm 20nm 24nm
15nm 15nm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
that provide low false detections. Note that the production settings provided virtually the same sensitivity performance as the maximum settings. Note also that the die-to-database performance is very close to the die-to-die performance, which indicates both very good database modeling and very good reticle uniformity (die-to-die typically has the highest perfor-mance since many system and mask errors are common).
Figure 8 shows the sensitivity relationships between die-to-die and die-to-database along with transmitted and reflected light for the maximum sensitivity settings. This example uses the Toppan Cyclics test reticle, which has various pro-grammed defects using hole geometry patterns, including both dense and isolated holes of various sizes. As shown in this example, the general relationships are: (1) die-to-die is more sensitive than die-to-database, (2) transmitted light is generally more sensitive than reflected light for dark defects, and (3) reflected light is generally more sensitive than trans-mitted light for clear defects. This suggests that the best overall defect detection performance is achieved when both transmitted and reflected light are used together. The green line shows the ITRS requirement.
Figure 9 (next page) shows the defect images and defect map of an oversize SRAF defect in transmitted mode (32nm node section of the Toppan Carbonate test reticle); the enhanced edges function is enabled to more easily discern the geometry. The low residue in the difference image indicated very good database modeling of the small SRAF. The defect map has no nuisance and no false detections.
Mask
: p72 ddT Max Sense
: p72 dbT Max Sense
: p72 ddR Max Sense
: p72 dbR Max Sense
Dark Extension Clear Extension Pinhole
Big
Def
ect
size
Sm
all
Figure 8: TeraScanHR 72nm pixel sensitivity performance on Toppan 45nm hole programmed defect test reticle (Cyclics) for selected defects and 360nm dense holes. Die-to-die and die-to-database performance shown for both transmitted and reflected light.
— 50nm spec — 50nm spec — 50nm spec
: p72 ddT Max Sense
: p72 ddT Production Sense*
: p72 dbT Max Sense
: p72 dbT Production Sense*
— 25nm spec — 25nm spec — 50nm spec — 50nm spec — 25nm spec
Pindot Extension Pinhole Mis-Place Mis-Place Intrusion Intrusion CD
*More than 50 various patterns tested
Figure 7: 72nm pixel sensitivity performance on Toppan 45nm line/space programmed defect test reticle (Carbonate) for selected defects.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Advanced Product Reticles using Die-to-Database Transmitted Light Mode
A number of product and product-like reticles were used to test the large-area false detection performance of the system and to determine the “production settings” under production conditions. Advanced production-critical layer reticles from the 45nm node were used to test the 72nm pixel, while cur-rent production reticles from the 65nm node were used to test the 90nm pixel (latter data not shown); comparable memory reticles were also used. Both die-to-die and die-to-database modes were tested in both transmitted and reflected illumina-tion; the standard HiRes detectors were used, along with the optional Litho2 detector for hole layers. The system demon-strated excellent inspectability performance at all three beta sites, with low false detections using high detector settings (most sensitive).
Transmitted and Reflected Illumination Modes – Highest Quality Inspection
Testing of the reflected light capability showed that higher sensitivity can typically be achieved versus transmitted light for clear pattern defects (e.g., pinholes, clear extensions, clear bridges, etc.). Similarly, reflected light typically achieves higher sensitivity versus transmitted light to defects on small clear lines and clear SRAF. In addition, reflected light can typically achieve higher sensitivity to defects on top of opaque areas such as particles or residual chrome on EPSM material. Therefore, the highest quality inspection can be achieved when using both transmitted and reflected light die-to-die or in die-to-database modes to detect both pattern defects and contamination defects. An “integrated mode” capability allows two or more inspection modes to be integrated into one in-spection with one setup, one scan, one review, and one report. When transmitted and reflected light modes are integrated, it is known as “T+R” and can be used in both die-to-die and die-to-database modes.
The system’s new image computer reduces scan time for sev-eral inspection modes. Scan times are significantly improved when using transmitted and reflected light inspection modes together in the same inspection (“integrated”). As shown in Figure 10, for the previous TeraScanTR platform, a die-to-die or die-to-database T+R inspection requires approximately twice the scan time as transmitted or reflected alone due to the
heavy image processing computation requirements. The new TeraScanHR allows full-speed operation for most T+R modes. These “Fast T+R” modes include: (1) 72/90/125/150nm pixels in die-to-die mode with COG, EPSM, and tri-tone reticle types, and (2) 90/125/150nm pixels in die-to-database mode for COG and EPSM reticle types (not tri-tone). Fast T+R is not currently available for the 72nm pixel die-to-database mode. Standard T+R is available for COG, EPSM, tri-tone, and altPSM reticle types.
The previous 45nm active layer (Figure 11) was also inspected with the 72nm pixel die-to-database mode in reflected light rather than the previous transmitted light. Figure 11 shows a clear extension defect that was detected in reflected light that was not detected in the transmitted light inspection. This ad-ditional defect would have been detected with integrated T+R mode, providing a higher quality result.
Mask
Database Image Difference Image Optical Image Defect Map
Figure 9: Over-size SRAF in the optical image 72nm pixel die-to-database transmitted mode. Toppan’s Carbonate test reticle in the 32nm node section with 150nm primary lines and 50nm SRAF.
Inspection Time (arbitrary units)
Current TeraScanTR
New TeraScanHR
Trans-only or Refl-only
Trans-only or Refl-only
Standard T+R
Fast T+R*
Figure 10: TeraScanHR scan time improvement for T+R: the new system allows full speed operation for most T+R modes.
Difference Reflected
Clear extension defect(detected in R not T)
Figure 11: 45nm active layer - clear extension defect detected in die-to-database reflected light mode and not detected in transmitted light mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
The previous 7xnm half-pitch DRAM layer (Figure 12) was also inspected with the 72nm pixel die-to-database mode in reflected light rather than the previous transmitted light. Figure 12 shows a defect that bridges two holes – this defect was detected in reflected light but was not detected in the transmitted light inspection. By inspecting with integrated T+R mode this additional defect would have been detected, thus providing a higher quality result.
A 4xnm half-pitch DRAM hole layer was inspected in die-to-die integrated T+R mode using both the HiRes detec-tor and Litho2 detector (Litho2 in T only). The reticle was manufactured by the AMTC and is standard ArF 6% EPSM material. The inspection used production detector settings and resulted in low false detections. Figure 13 shows over-size clear SRAF defects detected (upper images) and under-size holes (lower images).
Conclusions
The TeraScanHR system was tested in die-to-database and die-to-die transmitted and reflected illumination modes using numerous programmed defect test reticles and product reticles representative of the 45nm node (and comparable memory nodes), as well as early reticles from the 32nm node. Data from testing at Toppan and the AMTC showed that the platform met the targets for high sensitivity, low false detections, and scan speed. Testing of the larger pixels was also performed using cur-rent generation reticles (65nm and 90nm – data not shown).
The system’s higher NA optics, new autofocus, smaller pixel size, and improved rendering and modeling algorithms showed significant improvements in inspection capability of
small linewidths, small defects, and aggressive OPC. A new image computer gives the system productivity improvements by reducing scan time for some situations and modes. Reflected light inspection is now a more viable inspection mode since it can be integrated with transmitted light with no additional scan time for some modes. Using integrated transmitted and reflected light inspection provides the best defect detection capability and results in the highest quality reticles for the industry.
Acknowledgements
The authors thank the many individuals and organizations that contributed to the development, internal testing, and most recently, field beta testing of the new TeraScanHR platform, including:
NIST for technology development funding of the original -TeraScan platform
KLA-Tencor RAPID TeraScanHR Development -Engineering Team
Worldwide reticle manufacturers and fabs for providing -reticles used in development and internal testing
Beta sites including Toppan Printing and the Advanced -Mask Technology Center*
KLA-Tencor RAPID Applications Team for data collection -and analysis
* AMTC is a joint venture of AMD, Qimonda/Infineon and Toppan Photomasks
General References
1. W. Broadbent, et al, “Results from a new reticle defect inspection platform,” 23rd Annual BACUS Symposium on Photomask Technology, Kurt R. Kimmel, ed., Proc SPIE Vol 5256, pp. 474–488, 2003.
2. W. Broadbent, et al, “Results from a new die-to-database reticle defect inspec-tion platform,” Photomask and Next Generation Lithography XI, Hiroyoshi Tanabe, ed., Proc SPIE Vol 5446, pp. 265–278, 2004.
3. J. Heumann, et al, “Detailed comparison of inspection tools: capabilities and limitations of the KLA 576,” 25th Annual BACUS Symposium on Photomask Technology, J. Tracy Weed, ed., Proc SPIE Vol 5992, p. 599246, 2005.
4. A. Dayal, et al, “Optimized inspection of advanced reticles on the TeraScan reticle inspection tool,” 25th Annual BACUS Symposium on Photomask Technology, J. Tracy Weed, ed., Proc SPIE Vol 5992, p. 599245, 2005.
5. K. Bhattarcharyya, et al, “Process window impact of progressive mask defects, its inspection and disposition techniques (go/no-go criteria) via a lithographic detector,” 25th Annual BACUS Symposium on Photomask Technology, J. Tracy Weed, ed., Proc SPIE Vol 5992, p. 599206, 2005.
6. S. Maelzer, et al, “High-resolution mask inspection in advanced fab,” Photo-mask Technology 2006, Patrick M. Martin, Robert J. Naber, ed, Proc SPIE Vol 6349, p. 63490S, 2006.
7. S. Teuber, et al, “Limitations of optical reticle inspection for 45nm node and beyond,” Photomask Technology 2006, Patrick M. Martin, Robert J. Naber, ed, Proc SPIE Vol 6349, p. 63490T, 2006.
8. W. Broadbent, et al., “Results from a new die-to-database reticle inspection platform,” Metrology, Inspection, and Process Control for Microlithography XXI, Chas N. Archie, Ed., Proc. of SPIE, Vol. 6518, p. 651821, 2007.
Mask
Difference Reflected
Bridging holes (in R)(detected in R not T)
Figure 12: 7xnm half-pitch DRAM layer - defect bridging two holes detected in die-to-database reflected light mode and not detected in transmitted light mode.
Under-size holes ~ 5% flux error
Figure 13: 4xnm DRAM hole layer inspected in die-to-die mode using integrated T+R with 72nm pixel.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Applications of a Laser-Assisted Defect Detection System for Chemical Mechanical Planarization (CMP) Slurry Development in Rigid Disk Polishing Toshi Kasai, Charles Dowell – Cabot Microelectronics CorpAnoop Somanchi – KLA-Tencor Corporation
Several detection systems are available for scratch characteriza-tion on rigid disk substrates. One example is the dark field microscope (DFM) based scratch count tool. While the DFM is convenient and easy to use, it has been known that scratch counts and analysis using the DFM are very subjective and have a strong operator dependency. Its manual handling opera-tion imparts relatively poor repeatability and reproducibility (R&R) and cumbersome defect classification (e.g., by size). It is also hard to acquire total particle counts, due to the relatively large number of defects.
Recent developments in laser-assisted optical surface analyzer (OSA) systems provide more repeatable and reliable surface morphology information.4-6 For instance, a series of the Candela instrument is equipped with ellipsometer, reflec- tometer, scatterometer and optical profiler capabilities.6-8 Each operational mode and combination of modes can be used for defect detection with the availability of specific defect data such as the types, numbers and locations. Moreover, versatile defect scan and analysis recipes allow constructive detection tunability and consistency. This helps eliminate the subjectiv-ity of manual detection. The Candela tools are widely used in the hard disk drive industry for defect identification.
This report presents the recent development of a defect detec-tion recipe and scratch count results for rigid disks measured
For hard disk manufacturing, characterizing CMP scratches is key to improving the reliability of the device.
KLA-Tencor’s CandelaTM optical surface analyzer (OSA) systems equipped with ellipsometer, reflectometer,
scatterometer and optical profiler capabilities can be used for defect detection, allowing detection tunability and
consistency and eliminating the subjectivity of manual detection. The Candela OSA technology demonstrated significantly
lower variability than conventional darkfield microscopes (DFMs); it also more easily identified small scratches (<10μm).
Introduction
In the hard disk drive (HDD) industry, the demand for increased data capacity in the last decade has necessitated several technological implementations.1 From the head disk interface (HDI) standpoint, the reduction of the distance between a flying read/write head and a disk media has been a main driver to achieve higher data density on the HDD. In order to minimize the gap between a head and a disk, the surface roughness of the disk needs to be low enough, and more important, the number of surface defects, such as scratch-es and particles, must be small enough to improve mechanical reliability of the HDD operation.
The chemical mechanical planarization (CMP) process is a key step for smoothing rigid disk surfaces.2 Typically, CMP is accomplished through the combination of chemical reac- tion and mechanical abrasion of the disk surface in contact with a polymeric pad and a slurry containing sophisticated chemistries and abrasives under an applied load.3 It has been recognized that the slurry has a significant impact on rigid disk scratch defect performance. Scratches can be created from handling, chemistry unbalance, or the presence of large abrasive particles in the CMP slurry. It is therefore essential to utilize a consistent scratch characterization technique for slurry development.
Data storage
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
with a Candela instrument. The scratch data compiled with the Candela are compared to those acquired with a conven-tional DFM and another type of OSA tool. It is shown that tuning of the recipe parameters is a key to obtaining consistent scratch counts. This option is not available with the DFM technique. Additional advantages of using the Candela tool for scratch defect analysis are also discussed.
Experimental
Candela defect detection system
The Candela CS10 is a 405nm laser assisted multi functional tool. It is equipped with two lasers, called the circumferential and radial lasers, as shown in Figure 1. The two laser beams form a 90 degree angle and converge at the analysis point of the sample. The instrument offers the ability to scan the disk with either beam or both lasers simultaneously. Signal detec-tion is performed with two detection channels for reflected and scattering beams. For scratch and particle defect identi-fication, the scatter channel, consisting of a photo multiplier tube (PMT) detector, is used. In this mode, the laser, interact-ing with the sample surface, produces scattering signals that appear as bright areas on the scattering signal images. Three modes of polarization for the incident lasers are available: P, S and Q (combination of P and S). During the measurement, the disk rotates and the laser source and detection system move in a transverse direction, so that the entire area of the disk sample can be scanned.
Dark field microscope (DFM) scratch detection system
The DFM technique uses several light sources to illuminate the disk surface from different angles. A charge-coupled device (CCD) camera is situated above the disk and dark field images of the disk surface are displayed on a monitor. The magnifica-tion of the CCD camera system was 10X for this study. The incoming direction of the light makes a shallow angle with respect to the disk surface so that the reflected light is not
Data storage
Candela CS10 system apparatus
Disk sample
Scatter channel
Reflectionchannel
Circumferentiallaser
Figure 1: X beam technology used for Candela C10. The radial and cir-cumferential laser beams, orthogonally situated, probe the disk surface, which generates scattering signal collected by the scatter channel.
directly collected by the CCD. If defects are present on a disk, the incident light is scattered and scattering signals are detect-ed by the CCD camera. The defects appear as bright images on a dark background in the monitor. The operator rotates the disk to inspect the surface and manually counts the number of defects. An advantage of using the DFM technique is its relatively short processing time and easy setup as compared to the Candela tool.
Sample preparation and experimental setup for Candela and DFM
Disk samples were ground and nickel-phosphorous coated9 prior to the CMP process. The inner and outer diameters and thickness of the disks were 25mm, 95mm and 1.27mm, respectively. The disks were polished with several kinds of CMP slurries, cleaned, and then forwarded to defect inspec-tion. Cleanliness of disks is critical for scratch inspection, since residual chemicals and stains possibly caused by handling can lead to miscounting.
The Candela measurement procedure was performed automati-cally by placing the disk on the platen of the instrument. The data outputs included the scratch and particle distributions for each bin, together with a map showing the defect location on the disk. The defect data collected can be classified by size into five bins. Nominal settings for the scratch defect bins were as follows: bin 1: 20-100µm; bin 2: 100-500µm; bin 3: 500-1000µm; bin 4: 1000-5000µm and bin 5: >5000µm.
In the DFM technique, the number of scratches was counted with a manual counter. The scratch length analysis was performed by measuring the length of each scratch on the monitor using a scale for classification. For the specific inspec- tion work, scratches were categorized in four groups: short (< 2mm) and shallow, short and deep, long (> 2mm) and shallow, and long and deep. The depth of the scratches was estimated by visual inspection depending on the brightness of the defect on the monitor.
The area analyzed on the disk using the DFM ranged from middle diameter (MD) to outer diameter (OD), whereas it ranged from inner diameter (ID) to outer diameter (OD) for the Candela. Therefore, the scan area was about 1.5 times larger for the Candela than for the DFM.
OSA-2 scratch detection system
Another OSA tool used at a customer’s site will be later intro-duced and compared with the Candela tool. This tool also uses a laser as a probe and employs scattering signals for the scratch detection but does not use the Candela technology. Since the tool was originally developed by the customer and is not commercially available, it is conveniently called OSA-2 in this paper. Very limited information was available due to confidentiality; therefore, establishing the correlation was more challenging. As seen in the following section, the tuning capability of the Candela tool plays an important role in order to acquire better correlation with this tool.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
In the case that the texturing is made along the circumferen-tial direction, radial scratches remaining are unfavorable. In this study, both lasers were enabled for comprehensive analysis. Figure 3 shows an atomic force microscopy (AFM) height image of a scratch defect found on a rigid disk surface; (a) and its cross sectional view; (b). The width and depth of scratches are typically ~1µm and several nanometers, respectively. It has been demonstrated that a 0.1µm wide and 1nm deep scratch can be clearly observed by the Candela system.
As also shown in Figure 2, particle defects can be recognized in both images. The scattering signals were relatively inde-pendent of the beam direction, though images of the particles become elongated in the laser direction. This occurs because the laser beam has an incident angle, approximately 60 degrees from normal on the plane of incidence. The elongated features resemble scratches, which makes the distinction between scratches and particles difficult in some cases. One can over-come this difficulty by optimizing the scratch classification parameters, such as the aspect ratio, in the analysis recipe.
The encoder multiplier settings and photo multiplier tube (PMT) voltages were found to significantly affect signal-to-noise (S/N) ratio. The encoder multiplier setting defines the number of circumferential data points at each radial location. For example, an encoder multiplier setting of 64x allows one to take 64 x 1,024 (=65,536) data points at one radial location.7 Figure 4 presents Candela scattering signal image of one scratch and its cross-sec-tional view at a fixed radius near the center of the image under three different settings of the encoder multiplier and PMT voltage: (a) 16X and 475V, (b) 16x and 525V and (c) 64x and 475V.
The peak intensities of the scratch and S/N ratio are summarized in Table 1. The peak intensity, obtained from the cross-sectional analysis, is the amplitude (%) of the peak measured from the average background noise level. Note that the unit is repre-sented as a percentage of PMT output voltage given by the tool. The S/N ratio is defined as the ratio of the peak intensity to the maximum amplitude in the background noise. Case (a) exhibited an S/N ratio of 1.2, indicating that the signal was not well distinguished from the background noise. An increase in the PMT voltage from 475 V to 525 V (Case (b)) signifi-cantly enhanced the S/N ratio from 1.2 to 2.1 (1.8 times). Also, an increase in the encoder multiplier showed a 2.4 times better S/N ratio (Case (c)). Increases in both parameters led to saturation of the scattering signal; therefore, the encoder mul-tiplier settings and PMT voltages were taken as 64x and 475V, respectively, in this study.
After the scan, the scattering signal images obtained were pro-cessed through the analysis recipe in order to identify defect sites. Optimization of the analysis recipe parameters is also highly critical. A key parameter here is the threshold parameters that define the minimum scattering signal intensity to be recognized as a defect site. To best set the recipe parameters, the following operation was performed. First, scattering signal images were processed with the analysis recipe and the number of scratch counts was recorded. Second, the same scattering
Results and Discussion
Candela recipe creation issues
The scan and analysis recipes need to be optimized prior to measurements. In this section, the effects of some key parame-ters of the Candela recipes for scratch detection are scrutinized.
Figure 2 shows Candela scattering images for the use of (a) the radial and (b) the circumferential laser. The horizontal direc-tion in the figure is parallel to the circumferential direction of the disk sample. As shown, the direction of the incoming laser highly affects the appearance of defects. Circumferential scratches, the angular orientation of which are more aligned with the circumferential direction of a disk, are visible using the radial laser (Figure 2(a)), but become invisible with the cir-cumferential laser (Figure 2(b)). This anisotropy occurs because more scattering signals are generated when the angle between the direction of the laser beam and the longitudinal direction of the scratch becomes closer to 90 degrees. The advantage of using two lasers is that it minimizes the effect of scratch ori-entation. If radial scratches are the main concern, it is possible to intentionally use the circumferential laser only so that the system becomes more sensitive to radial scratches. This is the case for disks that are forwarded to the texturing process after CMP. The texturing process allows the formation of uniform, controlled scratch marks along which magnetic crystal growth can be performed in the magnetic layer deposition process.9
Data storage
Particle
Particle
Scratch visible
Scratch visible
Beamdirection
Beamdirection
200µm
200µm
(a)
(b)
Figure 2: Candela scattering signal images of a polished rigid disk surface using (a) radial and (b) circumferential laser. The incoming beam directions are indicated by thick arrows.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Data storage
signal images were checked by an operator’s visual inspection and recognized scratches were manually counted. Finally, the two scratch counts were compared. We assumed that the scratch counts made by the operator were accurate and pre-cise so that those could be used as a standard to evaluate the Candela scratch counts. Two types of potential errors exist: Type I error occurs when the Candela does not recognize a scratch even though the scratch defect is present; Type II error occurs when the Candela categorizes a scratch that is not a real scratch defect. These categorizations are illustrated in Table 2. The probability of error is dependent upon the threshold parameters set in the analysis recipe. Higher thresh-olds lead to reduced type II error but an increase in type I error, and vice versa. The value of optimized threshold param-eters for both circumferential and radial laser scattering signals was found to be 0.12%. The associated scratch counts for four disk samples are shown in Table 3. The type I and II errors occurred at 30% and 2% on average, respectively. A rate of 0% is ideal for both errors; however, it is challeng-ing since the two errors are in the correlation of a trade-off. We selected the condition that produced type II error close to zero and minimized type I error. As found later, the threshold setting is a key in the study of tuning capability.
The scratch identification sys-tem developed and described above can be also applied to other types of samples such as integrated circuit (IC) silicon wafers, though some adjustments in parameters are required.
(b)
A B
5.05.0
-5.00 5.0 0 5.0
(nm
)
(µm)(a)
(µm)
Figure 3: (a) AFM image of a scratch on a rigid disk after CMP and (b) section analysis along the line AB of the scratch indicated by arrows.
33610µm
33235
187.90 191.75 deg
187.90 191.75 deg
189.39 190.35 deg
32860
32485
33610µm
33235
32860
32485
34250µm
33875
33500
33125
(a) Angle (°), Radius (µ)
Uni
tsU
nits
Uni
ts
Angle (°), Radius (µ)
Angle (°), Radius (µ)
(b)
(c)
Figure 4: Comparison between measured CD and average image gray level for the different etch test conditions.
Case (a) Case (b) Case (c)
Encoder multiplier 16X 16X 64X
PMT voltage (V) 475 575 475
Peak intensity (%) 0.04 0.16 0.12
S/N ratio 1.2 2.1 2.9
State of Nature
Scratch Not scratch
Decision by Candela Scratch Good Type II error
Not scratch Type I error Good
Table 1: Peak intensity and S/N ratio of a scratch under various encoder multiplier and PMT voltage setting for Candela.
Table 2: Definition of Type I and II errors for Candela recipe confirmation test.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Correlation between Candela and DFM
Figure 5 shows disk surface images at the same location viewed using (a) the Candela and (b) the DFM. The Candela image was obtained using the P-polarized radial laser, directed from the top in the figure. The differences found in the two images can be explained as discussed in the previous section consid-ering the experimental setup of the Candela tool. A radial scratch slightly seen at the center bottom of the DFM image is not recognized in the Candela image. On the other hand, several circumferential scratches, which have a horizontally transverse direction, are more visible in the Candela image. Particles are elongated parallel to the beam direction in the Candela image. Stains at the left bottom corner are highlight-ed in both images.
Representative differences between the tools are summarized in Table 4. The spatial detection limit is much smaller for the Candela than for the DFM. In the case of the Candela, the detection limit is regulated by the laser spot size (4µm), while for DFM, the limit is dependent on the resolution of the CCD camera and the ability of the operator’s eye. The study varia-tion of the Gauge R&R is defined as the contribution of R&R to the total variation including repeatability, reproducibility and part-to-part variations. In general, a value larger than 9% indicates that the system needs improvement. The Candela performed at a 7% study variation for ten samples. This leads to acceptable R&R performance. On the other hand, the DFM showed a 25% study variation, which was less satisfactory since the DFM required more manual operation.
A comparative study on scratch counts between the DFM and Candela was conducted. Figure 6 shows the correlation be-tween the DFM long scratch count (> 2mm) and the Candela long scratch count (> 1mm). The variations in scratch count originated from the use of different kinds of slurries with various scratch performance. The value of the linear regres-sion correlation coefficient, R2, was 71%. This indicates that the correlation between the DFM and Candela scratch counts was marginal. Generally, an R2 of at least 75% is required for satisfactory correlation.10 In addition, the correlation was not matched since the regression line was not identical with the line y = x at a 95% confidence level. This is probably due to the differences in the detection systems of the two instru-ments, including the poor Gauge R&R of the DFM system. The correlation was examined for scratch counts under various size categories, as summarized in Table 5. The largest R2 was 71%, found in the case described above.
The slope of the regression line in Figure 6 is 0.56, which is less than unity. This suggests that, under the analysis criteria, the Candela failed to spot scratches that the DFM could detect. Considering the difference in the scan area (the scan area of the Candela was about 1.5 times larger than that of the DFM) and the size of scratches categorized (> 1mm for the Candela and > 2mm for the DFM), the overall number of scratches the Candela failed to spot may have been even larger. The most likely reason for this discrepancy is that the Candela instru-ment is not sensitive to shallow scratches due to the relatively low scattering signal from these defects and the threshold set-ting issue of the tool as discussed previously. The data shown
Data storage
Disk samplenumber
Number of scratch count Type I error (%)
Type IIerror (%)Correct False Missed Total
1 39 0 17 56 30 0
2 11 2 1 12 8 15
3 7 0 8 15 53 0
4 30 0 12 42 29 0
Overall 87 2 38 125 30 2
Table 3: Candela scratch count data used for Type I and II error evaluation.
(a) 1 mm (b) 1 mm
Figure 5: Rigid disk surface images using (a) Candela and (b) dark field microscope (DFM) techniques.
Candela C10 DFM
Light source Violet laser (405 nm) White light
Number of light sources 2 Multiple
Detector Photo multiplier tube (PMT)
CCD
Spatial resolution limit >4 µm ~100 µm
% Study variation of GaugeR&R for scratch counts
7% 25%
Table 4: Comparison of characteristics between Candela C10 and dark field microscope (DFM) techniques.
Candela vs DFM (long scratches)
DFM counts (>2mm)
Regression95% Confidence Interval
Can
del
a co
un
ts (
>1m
m) Y = 0.56 X + 3.4
R² 70.7%
40
40
30
30
20
20
10
100
Figure 6: Correlation between Candela long scratch count (> 1 mm) and DFM long scratch count (> 2 mm).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
in Table 5 support this hypothesis. The slope of the regres-sion line was 1.5, up from 0.56, when deep scratches are only counted for the DFM detection from the previous comparison.
As discussed above, the experimental evidence showed that the Candela scattering signal under the current parameter setting might be insensitive to shallow scratches. This is not necessar-ily a drawback for the tool. Its ability to provide meaningful information in terms of scratch geometries such as length, depth and width is more important than a simple count of defects. An advantage of the Candela is its flexible tuning capability for defect recognition as a function of the targeted scratch geometry, as illustrated in the following section.
Candela tuning capability and its use in CMP slurry screening
A set of disk samples was polished using a series of slurries expected to exhibit different scratch performance. These disks were inspected with the OSA-2 laser-assisted optical surface analyzer and classified into two groups: “Scratch passed (Good)” or “Scratch rejected.” The same disks were then analyzed by the Candela and the DFM. The data shown in Figure 7(a) and (b) are the total scratch counts for the Candela and the DFM, respectively. In each graph, the classification by the OSA-2 tool is incorporated. A threshold setting for the Candela is a key in this section and the value of 0.12% was taken for the measurement in Figure 7(a). In the slurry iden-tification, the combination of a letter and a number is used, where the letter refers to a category given by the OSA-2 with either “G” as “Good” or “R” as “Rejected” and the number refers to the slurry used. Slurry 1 was a standard rigid disk slurry. Slurries 2, 3 and 4 contained a scratch-reduction additive with the concentration of 100, 1,000 and 4,000 (unit: relative con-centration), respectively. The Candela total scratch count clearly exhibits the effect of the scratch-control additive. This trend is less pronounced with the DFM technique. The
OSA-2 tool, however, failed to observe the effect of the addi-tive. This occurred possibly due to the different classification methods taken by the OSA-2. Our next task was to find how to obtain consistent results with the OSA-2 using the Candela.
An attempt was made to have a better correlation by com-paring scratch counts with selected scratch length, as was performed to obtain a correlation between the Candela and DFM (see Table 5); however, the result was not satisfactory. It was later suggested that the OSA-2 classified the defects with scratch width and depth together with scratch length. From this information, we came to the conclusion that the scattering intensity should have been additionally focused on. The scat-tering signal originating from the interaction between scratch
Data storage
Candela scratch size category
DFM scratch size category
a(slope)
b(y intercept)
R square (%)
1 1 mm> 2 mm> 0.56 3.4 71
2 1 mm> 2 mm> and deep 1.5 3.9 70
3 Total Total 2.8 84 56
4 0.1 mm> Total 0.99 35 57
5 0.2 mm> Total 0.53 18 64
Table 5: Regression analysis of Candela and DFM scratch counts for various size categories.
Sample: G1 Scattering intensity range (%)
Scratch bin Lower limit (µm) Upper limit (µm) 0.12 – 0.2 0.2 – 0.3 0.3 – 0.4 >0.4
1 20 100 179 31 23 15
2 100 500 76 8 9 12
3 500 1000 7 4 0 2
4 1000 5000 0 9 3 1
5 5000 N/A 6 0 0 1
Total 268 52 35 31
Table 6: An example of categorization for Candela scratch counts using scattering intensity ranges and length bins, used for the data plot in Fig. 8(a).
500
400
300
200
100
0G1 G2 G3 G4 R1 R2 R3 R4
Good
Scratch rejected
(a) Candela: Total scratches
Scra
tch
co
un
t
Disk sample number Disk sample number
500
400
300
200
100
0G1 G2 G3 G4 R1 R2 R3 R4
Good
Scratch rejected
(b) DFM: Total scratches
Scra
tch
co
un
t
Figure 7: Total scratch counts measured using (a) Candela and (b) DFM for “Good” and “Scratch rejected” disks categorized by another laser assisted defect detection system (OSA-2). Disk sample number specifies the OSA-2 category and slurry used. Slurry 1 is a standard CMP slurry for rigid disks and slurry 2 to 4 contain scratch reduction additive with different concentrations.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
correlation. For the DFM data, an attempt was made to obtain a better correlation with the OSA-2 by selecting deep and long scratches, since the result suggested that scratches with larger scattering intensities could be better highlighted in the OSA-2 detection. As shown in Figure 8(b), such a correlation as found for the Candela was not obvious for the DFM scratch counts.
The data analysis showed that a better correlation was obtained between the Candela and the OSA-2 with a relatively higher Candela threshold setting. As shown in Table 6, the majority of scratches exhibited the scattering intensity below 0.2% for the G1 sample. The use of the scratch-control additive was effective in reducing the number of scratches in this category, but less significant in eliminating those with a larger scatter-ing intensity that could be primarily focused on in the OSA-2 detection. This recognition is critical for development of a new CMP slurry product. To satisfactorily meet the require-ment from customers in terms of scratch reduction, the scratch definition criteria are very important, i.e., to know which scratch geometries (depth, length, width and direction) should be focused on. The root cause of the various types of scratches may be different. The short/shallow scratches may be due to agglomeration of abrasive particles or by-product contamination
defects and a laser beam possibly contains the information of width and depth of scratches in its intensity. The standard Candela classification technique does not allow this capability. Possible scratch defect sites that show higher scattering signal than a threshold value are all considered to be defects. In order to classify the scratch defects with scattering intensity, scatter-ing signal data were re-analyzed with different threshold val-ues, and then scratch counts obtained were manually classified depending on the scattering intensity ranges.
An example of such a categorization for the G1 sample in Figure 7(a) is shown in Table 6. The scratches are classified depending on their length and scattering intensity. The number of significant scratches was identified from this table. Scratch defects that showed higher intensity than 0.4% were categorized as the most significant defect, no matter how long they were and then would be all counted as scratches. Those that showed 0.3 to 0.4% in intensity range were the second most significant and classified as scratches if they were longer than 500µm in length. Likewise, scratches with 0.2 to 0.3% intensity range were recognized to be the third most significant and classified as scratches if they were longer than 5000µm in length. The sum of the scratch count mentioned above was obtained to be a newly categorized scratch count.
Figure 8(a) exhibits the scratch counts under the new defini-tion for the same disk samples in Figure 7(a). It becomes clearer to discern the two categories given by the OSA-2, named “Good” and “Rejected.” When the number of scratches is below approximately 40 on the Candela measurement, the OSA-2 rates the disks as “Good” while above this value, the disks are evaluated as “Scratch rejected.” This result suggests that scattering intensity can be another key parameter to be considered for obtaining better correlation with other defect metrology tools. Though the correlation may not be satisfac-tory enough for some data (e.g., scratch counts of G1 and R3 are close in Figure 8(a)), the difference of scratch count profiles found between Figures 7(a) and 8(a) is significant. Probably, optimization of the analysis parameters will help improve the
Data storage
150
100
50
0G1 G2 G3 G4 R1 R2 R3 R4
Good
Scratch rejected
(a) Candela: Intensity & length categorization
Scra
tch
co
un
t
Disk sample number Disk sample number
20
15
10
5
0G1 G2 G3 G4 R1 R2 R3 R4
Good
Scratch rejected
(b) DFM: Intensity & length categorization
Scra
tch
co
un
t
Figure 8: (a) Candela scratch count categorized with scattering intensity and length and (b) DFM scratch counts (deep and long), for the same disk samples in Fig. 7.
The Candela system provided meaningful information
for scratch geometries such as length, depth and width, as well as
a flexible tuning capability for defect recognition
as a function of the targeted scratch geometry.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
generated from disk materials. The long/deep scratches may be caused by large particles that were not filtered out and entered the slurry as a contaminant. Depending on the mechanistic reasons, our approach for CMP slurry development should be different. With the use of the recipe-oriented Candela tool that can flexibly and efficiently provide necessary scratch informa-tion, slurry development work will be significantly enhanced. Throughout this study, we have learned that extracting and selecting required information from metrology tools is a key step in slurry product development.
This tuning capability is not currently available for the Candela system as a standard procedure. The addition of this capability to the system may require complicated design changes for the Candela scratch analysis process, but will provide more flexibility for the tool.
Conclusions
Evaluations of scratch counts using a laser-assisted optical sur-face analyzer (Candela CS10: KLA-Tencor Corp.) and dark field microscope (DFM) techniques led to the following conclusions.
1. A gauge repeatability and reproducibility (R&R) study showed the Candela tool had 7% study variation. This leads to acceptable R&R performance (less than 9%) . On the other hand, the DFM showed 25% variation and this discrepancy is most likely due to the manual operation of the DFM.
2. The correlation between the Candela and DFM scratch counts was given an R2 of 71% for specific scratch size categorization. This marginal correlation occurred due to the relatively poor R&R of the DFM measurement capability and differences in detection system between the tools.
3. It was demonstrated that the Candela can more easily identify small scratches (less than 10µm) and be less sensitive to faint scratches than the DFM under the parameter setting used, due to differences in detection, analysis, and data processing systems.
4. The Candela scratch counts with a standard threshold clearly demonstrated the effect of a CMP slurry additive on
scratch reduction. This effect was not apparent with the DFM technique, due to the limitation of resolution stated above.
5. The sensitivity adjustment (tuning) capability of the Candela gave the possibility of correlating scratch counts to those obtained with another laser-assisted scratch detection tool. This was not achieved with the use of the DFM tech-nique. Depending on the criteria of the scratch defects, the Candela is tunable with modification of the recipes to extract necessary scratch information.
Acknowledgments
The authors would like to thank Li Wang for the data collec-tion and Francois Batllo, Haresh Siriwardane, Edward Remsen, Vamsi Velidandla and Laurie Bechtler for the fruitful discus-sions and suggestions in completing this project.
References1. Sarid D, McCarthy B and Jabbour G E, 2004 Nanotechnology for data storage applications, in bhushan B (ed.), Springer Handbook of Nanotech- nology Springer-Verlag, Heidelberg, Germany.
2. Lei H and Luo J 2004, CMP of hard disk substrate using a colloidal SiO2 slurry: preliminary experimental investigation, Wear 257 pp. 461–70.
3. Michael R. Oliver (ed.) 2004, Chemical mechanical planarization of semiconductor materials, Springer-Verlag, Heidelberg, Germany.
4. Knollenberg R G, A polarization diversity two-color surface analysis system, 1987 Journal of Environmental Sciences 30, pp. 35–8.
5. Takami K, 1997, Defect inspection of wafers by laser scattering, Mat. Sci. Eng. B 44 pp. 181–7.
6. Meeks S W 2003, Optical surface analyzer inspects transparent wafers, Laser Focus World 39 pp. 105–6, 8.
7. Bechtler L, Velidandla V and Lane G, 2003, Optical surface analysis of transparent substrates for manufacturing applications, Proceedings of Electrochemical Society 2003-3, pp. 540–7.
8. Candela Instruments, 2003, Optical Surface Analyzer C10 User’s Manual, Software version 1.0, Rev 1.0.
9. Johnson K E, Mate C M, Merz J A, White R L and Wu A W, 1996 Thin film media - current and future technology, IBM J. Res. Develop. 40 (Sept).
10. Miller J N and Miller J C, 2000, Statistics and chemometrics for analytical chemistry, 4th ed. Pearson Education Limited, Edinburgh Gate.
Data storage
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
2810 and 2815Brightfield Patterned Wafer Inspection Systems
Memory manufacturers require high throughput detection of small defects on dense, repetitive patterns and in high vertical structures. Logic manufacturers must find and isolate all critical defects on complex geometries and in dense repetitive patterns which employ new materials and rapidly changing processes. In addition to these distinct inspection requirements, both memory and logic chipmakers need improved sensitivity and speed in order to quickly ramp new processes to high yield. The 2810 and 2815 are the industry’s first memory- and logic-specific full-spectrum brightfield inspectors, helping solve yield issues with features specialized by device type. Part of KLA-Tencor’s comprehensive wafer inspection portfolio, the 281x inspectors provide effective line monitoring and engineering analysis capabilities for –<55nm memory and –<45nm logic manufacturing.
The 281x tools are based on the widely adopted 2800 Series full-spectrum DUV/UV/visible brightfield inspectors, utilizing memory- and logic-customized optics modes and algorithms to capture a broad range of yield-critical defects on all process layers. The 281x inspectors include a selectable spectrum illumination source and a pixel-independent high numerical aperture (NA) which maximize material contrast, suppress nuisance and work with advancements in automatic defect binning to produce a meaningful defect Pareto. With nearly double the 2800’s throughput, the 281x inspectors enable engineers to quickly achieve systematic yield improvements and reduced baseline defectivity, for critical etch, CMP and photo line monitoring. The 281x tools offer flexibility for process development, reliability for production, and extendibility for future nodes and emerging device technologies.
Questions about how the 2810 or 2815 can address a specific use case or yield challenge? Please contact Mark Shirey at [email protected].
281x Benefits
Customized optical modes and selectable full-spectrum DUV/UV/visible illumination produce the highest sensitivity to defects of interest on all process layers
Highest weighted average throughput in production (WATIP) allows increased sampling, lower cost-of-ownership or higher sensitivity inspections
Commonality and connectivity with other KLA-Tencor inspec-tors and review tools optimize inspector capacity and reduce production integration time
Established, production-proven, highly extendible tool architecture provides reliable line monitoring capability for multiple technology nodes
Process Window Qualification (PWQ) application enables lithographers to assess designs prior to production
Product News
EquivalentThroughput
0
25
50
75
100
Layer 1 Layer 2 Layer 3
No
rmal
ized
Def
ect
Co
un
t
2810: 75–80% throughputimprovement over 2800
28002810
With increased throughput and new pattern suppres-sion modes customized for memory devices, the 2810 demonstrates improved sensitivity at throughput over the 2800 for three front end memory layers.
BridgePattern Line Thinning
Particle SEM Non-Visual/Bump
Defects of Interest
Def
ect
Co
un
t 90nm Pixel (BBDUV BF)
50nm Pixel (BBDUV BF)
2815 defect Pareto demonstrating a 2x increase in critical bridge defect capture provided by the new 50nm pixel. The industry’s smallest pixel enables improved capture of defects of interest for earlier detection of process excursions.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
Semiconductor device manufacturers must address the yield issues related to shrinking dimen-sions, new materials and innovative device structures in order to ramp to high yields quickly and profitably. Patterned wafer inspectors help improve yield by enabling engineers to solve defect problems at all stages of the product lifecycle – from process development to production. Part of KLA-Tencor’s comprehensive wafer inspection portfolio, the Puma 9150 darkfield inspector provides effective excursion monitoring capability for 45nm and beyond.
The latest in the Puma family of laser imaging, darkfield inspectors, the Puma 9150 utilizes the revolutionary Streak™ technology and introduces extended capability to capture the broadest range of defect types at high throughputs. New optical modes allow for increased sensitivity to bridging and other pattern defects for non-critical etch applications, deliver improved capture of residue and other defects for CMP, and detect photo defects at high throughputs. In addition to providing benchmark films performance, the Puma 9150 complements higher sensitivity broadband brightfield inspections by offering an improved sampling option for photo-cell monitoring, after-develop inspection, and other tool monitoring applications.
Questions about how the Puma 9150 can address a specific use case or yield challenge? Please contact Amir Azordegan at [email protected].
Puma™ 9150Darkfield Patterned Wafer Inspection System
The new optical modes of the Puma 9150 provide increased capture of low profile defect types, such as incomplete copper polish (shown), deformed contacts, bridging and residues.
Puma 9150 Benefits
New optical modes and Streak darkfield imaging technology provide improved capture of defect types across an extended applications space
Highest production throughputs at required sensitivity enable increased yield sampling or lower cost-of-ownership
Commonality and connectivity with other KLA -Tencor inspec-tors and review tools optimize inspector capacity and reduce production integration time
Ease-of-use improvements and innovative algorithms result in quick and easy recipe setup
Established tool architecture and production-proven matching produce consistent and reliable inspection results
Bridge Cu Residue Missing Contact
Sig
nal
-to
-No
ise
Rat
io Traditional Optical Modes
New Optical Modes
Signal-to-noise ratios of three defects demonstrating the complementary detection capabilities of the traditional and new optical modes of the Puma 9150. The multiple optical modes enable the broadest darkfield defect type capture across an extended applications space.
Product News1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
eDR-5200Electron Beam Review and Classification System
As design rules shrink below 45nm, defect and yield engineers are increasingly concerned about smaller defects and the quality of the defect Pareto coming from their review tools. The eDR-5200 wafer defect review and classification system successfully addresses these concerns by imaging sub-50nm defects and producing a more accurate defect Pareto with dramatically fewer SEM Non-Visual (SNV) defects. A critical piece of KLA-Tencor’s comprehensive defect solutions portfolio, the eDR-5200 leverages advances in resolution and defect re-detection sensitivity, along with unique connectivity with KLA-Tencor inspectors, to enable better review performance, faster yield learning and higher tool productivity for the 45nm node and beyond.
The eDR-5200 introduces an electromagnetic immersion column design, delivering the resolu-tion required to image <50nm defects. In addition, a high precision stage, innovative defect deskewing algorithms, and advanced re-detection methods provide the capabilities necessary to find low contrast or tiny defects, effectively reducing the number of reported SNVs. Further improvements in the defect Pareto are obtained with novel approaches to defect classification, including power assisted classification (ePAC™) and fully automated defect classification (eADC™). In order to address the inspection-review cycle as a single use case, the eDR-5200 offers seamless connectivity to KLA-Tencor optical inspectors. This produces a greater number of higher quality defect Paretos per hour, allowing engineers to rapidly resolve yield issues for even the smallest critical defects on 45nm node devices.
Questions about how the eDR-5200 can address a specific use case or yield challenge? Please contact Christophe Fouquet at [email protected].
eDR-5200 Benefits
Higher stage accuracy and image resolution allow detection and imaging of <50nm defects
Production-worthy manual, power-assisted, and fully automated defect classification achieve the fastest time to the best defect Pareto
Proprietary connectivity to KLA-Tencor inspectors produces faster, more accurate recipe setup on the SEM, plus a lower percentage of SEM non-visuals and other nuisance defects
Innovative EDX design enables analysis and classification of defects <100nm, based on their composition
Connectivity between KLA-Tencor inspection and review tools offers a significant reduction in Process Window Qualification (PWQ) time
Product News
27
4036
71 73
8578
112
12 1322
1322
0
25
50
75
100
1-FEOL
2-FEOL
3-BEOL
4-FEOL
5-BEOL
6-BEOL
7-BEOL
Layer
SNV
Rat
e %
POR Method
eDR Method
The eDR-5200 includes improved coordinate accuracy and connectivity with KLA-Tencor inspectors, resulting in a dra-matic reduction in the number of reported SEM non-visuals.
0.5µm FOV
50nm Defect
With an immersion column design and higher stage accuracy, the eDR-5200 detects and images <50nm defects.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
The SURFmonitor system extends the industry-leading Surfscan SP2 unpatterned surface inspection system beyond traditional defect inspection into the realm of metrology. SURFmonitor can measure variations in surface morphology on bare wafers or blanket films, which correlate to a broad array of process parameters such as surface roughness, grain size, and process temperature. With sub-Ångstrom repeatability, the SURFmonitor system creates detailed parametric maps while defect information is being collected, enabling fabs to monitor both process drift and defectivity simultaneously with no impact on inspection throughput. SURFmonitor also extends the defect detection capability of the SP2 into the “sub-threshold” region, identifying process anomalies and defect signatures that are not typically captured in the defect channels.
The SURFmonitor module uses the low spatial-frequency, low amplitude scattering signals from the defect scan to generate high resolution, full wafer maps with sub-Ångstrom height resolution. SURFmonitor then analyzes these maps for within-wafer or wafer-to-wafer parametric spatial variations, and can apply the results for statistical process control. SURFmonitor data have shown excellent correlation to several parameters such as surface roughness for copper, tungsten and poly-silicon films, transparent film thickness, surface damage and surface temperature variations. SURFmonitor also provides the ability to detect defects with low signal-to-noise ratio, such as watermarks and stains that are difficult to detect in traditional defect channels. Built on the Surfscan SP2 platform, SURFmonitor results demonstrate unparalleled repeatability and matching.
Questions about how the SURFmonitor can address a specific use case or yield challenge? Please contact Andy Steinbach at [email protected].
SURFmonitorProcess Signature and Metrology Module
SURFmonitor Benefits
Defect and film morphology information in the same inspection, with no additional throughput impact
Powerful algorithms for extract-ing defect signatures and trans-lating surface scattering results into usable metrology data
Sub-Ångstrom vertical (feature height) resolution and industry-leading lateral resolution
Available as an add-on module to the Surfscan SP2 products
Several proven applications across all process modules in the fab
AFM RMS roughness (nm)
SUR
Fmo
nit
or
sig
nal
(p
pm
) 300
250
200
150
100
50
00.0 1.0 2.0 3.0 4.0 5.0 6.0
SURFmonitor results for a Cu ECD film show excellent correlation to surface roughness as measured by AFM. The quadratic relationship between SURFmonitor signal and roughness matches theoretical predictions.
This SURFimage exhibits wet clean drying stains, which are extracted and reported as defects by SURFmonitor algorithms.
Product News1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
HRP-350Advanced 45nm semiconductor profiling technology at production throughputs
With profile control requirements for critical etch and CMP processes becoming much tighter every device generation, customers require a single-system solution that will support yield critical nano-scale applications, as well as control macro-scale topography on the wafer.
The HRP-350 is the industry’s most advanced high-resolution surface topography profiling system, offering chipmakers the ability to monitor significantly smaller lateral and vertical dimensions. Featuring diamond styli down to 20nm radius and a lower-noise platform for enhanced measurement sensitivity, the HRP-350 system offers nanometer-scale stylus technology which matches AFM resolution — without modeling requirements. The system’s high-resolu-tion mode enables accurate control of nano-scale features for applications that directly impact device performance, such as Shallow Trench Isolation, CMP in the interconnect, metal film roughness and tungsten plug recess. For larger scale features, the system’s long-scan mode operates at high throughput to measure Cu CMP dishing and erosion, copper plating, die planarity, and C4 bump height in packaging. Higher scan speeds elevate the HRP-350’s production worthiness across a wide range of critical transistor and interconnect applications.
The system’s broad portfolio of styli, including the proprietary 20nm UltraSharp™ stylus, are based on diamond materials to offer the longest operating lifetimes, typically up to 100 times longer than AFM tips. New stylus developments further advance the technology not only by shrinking the stylus dimensions, but also enhancing the robustness to enable scanning up to five times faster than the previous HRP-340 system. Other system productivity enhancements contribute up to 40% higher system throughput while profiling critical structures in advanced 65nm and 45nm devices. In addition to the 300mm HRP-350 system, a 200mm or less HRP-250 is also available for IC semiconductor and disk drive manufacturing applications.
Questions about how the HRP-350 can address your surface profiling challenges? Please contact Petrie Yam at [email protected].
HRP-350 Benefits
Extends the measurement capability to support advanced requirements for 65nm and beyond
Smaller styli and improved noise performance enable topography measurements of advanced nano-scale features (e.g., recess)
Provides 33% tighter gauge performance for the most stringent process control
Novel processing abilities enable small styli to scan at 5X higher scan speeds to support both macro- and micro-topography without stylus exchange
Up to 40% higher throughput and a more reliable isolation system make for the most prodution worthy surface metrology solutionStylus Lifetime Step Height Measurement
Cu
rso
r H
eig
ht
(A)
-1080.0
-1070.0
-1060.0
-1050.0
-1040.0
-1030.0
>100k
Diamond based styli offering the longest operating lifetimes, typically up to 100 times longer than AFM tips.
Featuring proprietary 20nm UltraSharpTM diamond styli and a lower-noise platform for enhanced lateral resolution.
Product News1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46