27/12/2008VLSI DesignUNIT I : Introduction to IC Technology CMOS Inverter in n-well process

Out LineCMOS Inverter in n-well processCMOS Inverter in Twin-Tub Process

CMOS Technologiesn-well: The pMOS transistors are placed in the n-well and the nMOS transistors are created on the substrateP-well: The nMOS transistors are placed in the p-well and the pMOS transistors are created on the substrate

1.WaferA bare Si wafer is chosenThe type will be n or p depending upon the technology

2.Oxidation of WaferThe wafer is oxidised at a high temperatureThis must be patterned to define the n-well

3.PhotoResist depositionThe photoresist is deposited throughout the waferThe PR has to be patterned to allow formation of the well

4.n-well MaskThe PhotoResist is exposed through the n-well maskThe softened PhotoResist is is removed to expose the oxide

5.Oxide EtchThe oxide is etched with HF acid where unprotected by PhotoResistThe wafer is now exposed to the n-well area

6.PhotoResist removalThe remaining PR is removed via piranha etchThe well is ready to be formed

7.n-well FormationThe diffusion process can make the the n-wellIon implantation can also form the same

8.Oxide RemovalThe remaining oxide is stripped with HF acidThis leaves the exposed wafer with the n-well formed

9.Gate FormationThe gates are made up of polysilicon over thinoxCVD is used to grow the poly (heavily doped) layer

10.Poly PatterningThe wafer is now patterned with PhotoResist and the poly maskFinally this leaves the device gates

11.Diffusion PatternAgain, a protective oxide is grown and PhotoResist depositedPhotoResist is patterned according to the diffusion mask

12.Wafer Exposure for DiffusionThe protective oxide is etched awayThe wafer is exposed for S/D formation

13.n-Diffusion RegionsThe n+ diffusion regions are formedPolysilicon blocks the channel area

14.Self-Aligned Process

This is a self-aligned processS/D are automatically formed adjacent to the gate

15.p-DiffusionThe p-diffusion mask is used nextThis completes creation of all active regions

16.Field OxideThe field oxide is grown to insulate wafer and metalIt is patterned with the contact mask

17.Metal FormationAl is sputtered over the entire area filling contact cuts tooMetal is patterned with the metal mask

Inverter Cross-sectionTypically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

Well and Substrate TapsSubstrate must be tied to GND, n-well to VDD Use heavily doped well and substrate contacts / taps

Six masks n-well

Polysilicon

n+ diffusion

p+ diffusion

Contact

Metal

CMOS Inverter in Twin-Tub Process

Twin Tub ProcessesTwin-tub CMOS technology provides the basis for separate optimization of the p-type and n-type transistors.

One can optimize independently for threshold voltage, body effect, and the gain associated with n- and p-devices.

Twin Tub Process: N-well / P-wellFirst place wells to provide properly-doped substrate for n-type, p-type transistors:

Twin Tub Process: Polysilicon

Pattern polysilicon before diffusion regions:

Twin Tub Process: N+/ P+ DiffusionAdd diffusions, performing self-masking:

Start adding metal layers:Twin Tub Process: Contact / Via / Metal

Twin-well CMOS process cross section

Twin Tub CMOS Process Cross Section

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