lecture1 3 cmos nwell and twintub process
TRANSCRIPT
![Page 1: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/1.jpg)
27/12/2008
VLSI DesignVLSI Design
UNIT I : Introduction to IC Technology
CMOS Inverter in n-well process
![Page 2: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/2.jpg)
Out Line
• CMOS Inverter in n-well process
• CMOS Inverter in Twin-Tub Process
![Page 3: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/3.jpg)
CMOS Technologies
n-well: The pMOS transistors are placed in the n-well and the nMOS transistors are created on the substrate
P-well: The nMOS transistors are placed in the p-well and the pMOS transistors are created on the substrate
![Page 4: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/4.jpg)
1.Wafer
A bare Si wafer is chosenThe type will be n or p depending upon the technology
![Page 5: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/5.jpg)
2.Oxidation of Wafer
The wafer is oxidised at a high temperatureThis must be patterned to define the n-well
![Page 6: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/6.jpg)
3.PhotoResist deposition
•The photoresist is deposited throughout the wafer•The PR has to be patterned to allow formation of the well
![Page 7: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/7.jpg)
4.n-well Mask
•The PhotoResist is exposed through the n-well mask•The softened PhotoResist is is removed to expose the oxide
![Page 8: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/8.jpg)
5.Oxide Etch
•The oxide is etched with HF acid where unprotected by PhotoResist•The wafer is now exposed to the n-well area
![Page 9: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/9.jpg)
6.PhotoResist removal
•The remaining PR is removed via piranha etch•The well is ready to be formed
![Page 10: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/10.jpg)
7.n-well Formation
The diffusion process can make the the n-wellIon implantation can also form the same
![Page 11: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/11.jpg)
8.Oxide Removal
The remaining oxide is stripped with HF acidThis leaves the exposed wafer with the n-well formed
![Page 12: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/12.jpg)
9.Gate Formation
The gates are made up of polysilicon over thinoxCVD is used to grow the poly (heavily doped) layer
![Page 13: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/13.jpg)
10.Poly Patterning
The wafer is now patterned with PhotoResist and the poly maskFinally this leaves the device gates
![Page 14: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/14.jpg)
11.Diffusion Pattern
Again, a protective oxide is grown and PhotoResist depositedPhotoResist is patterned according to the diffusion mask
![Page 15: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/15.jpg)
12.Wafer Exposure for Diffusion
The protective oxide is etched awayThe wafer is exposed for S/D formation
![Page 16: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/16.jpg)
13.n-Diffusion Regions
The n+ diffusion regions are formedPolysilicon blocks the channel area
![Page 17: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/17.jpg)
14.Self-Aligned Process
This is a self-aligned processS/D are automatically formed adjacent to the gate
![Page 18: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/18.jpg)
15.p-Diffusion
The p-diffusion mask is used nextThis completes creation of all active regions
![Page 19: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/19.jpg)
16.Field OxideThe field oxide is grown to insulate wafer and metalIt is patterned with the contact mask
![Page 20: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/20.jpg)
17.Metal Formation
•Al is sputtered over the entire area filling contact cuts too•Metal is patterned with the metal mask
![Page 21: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/21.jpg)
Inverter Cross-section
•Typically use p-type substrate for nMOS transistors• Requires n-well for body of pMOS transistors
![Page 22: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/22.jpg)
Well and Substrate TapsSubstrate must be tied to GND, n-well to VDD Use heavily doped well and substrate contacts / taps
![Page 23: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/23.jpg)
Six masks– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
![Page 24: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/24.jpg)
CMOS Inverter in Twin-Tub Process
![Page 25: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/25.jpg)
Twin Tub Processes
• Twin-tub CMOS technology provides the basis for separate optimization of the p-type and n-type transistors.
• One can optimize independently for threshold voltage, body effect, and the gain associated with n- and p-devices.
![Page 26: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/26.jpg)
Twin Tub Process: N-well / P-well
First place wells to provide properly-doped substrate for n-type, p-type transistors:
![Page 27: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/27.jpg)
Twin Tub Process: Polysilicon
Pattern polysilicon before diffusion regions:
![Page 28: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/28.jpg)
Twin Tub Process: N+/ P+ Diffusion
Add diffusions, performing self-masking:
![Page 29: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/29.jpg)
Start adding metal layers:
Twin Tub Process: Contact / Via / Metal
![Page 30: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/30.jpg)
![Page 31: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/31.jpg)
Twin-well CMOS process cross section
![Page 32: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/32.jpg)
Twin Tub CMOS Process Cross Section
![Page 33: Lecture1 3 CMOS nWELL and TwinTub Process](https://reader034.vdocuments.net/reader034/viewer/2022050801/5526f6ed4a795955118b45fc/html5/thumbnails/33.jpg)
---Struggle gives Strength and Dignity....