WhyisCMOSscalingcomingtoan END?NorZaidi Haron SaidHamdiouiComputer EngineeringLaboratory, DelftUniversityof TechnologyMekelweg4, 2628CDDelft, TheNetherlands{N.Z.B.Haron, S.Hamdioui} @tudelft.nlAbstract-The continuedphysicalfeaturesizescaling of com-plementaryMetal OxideSemiconductor(CMOS) transistors isexperiencingasperitiesduetoseveralfactors, andit isexpectedtoreach itsboundaryat size of 22 nm technologyby 2018.Thispaper discusses and analyzes the main challenges and limitationsof CMOS scaling, not only fromphysical and technologicalpoint of view, but also frommaterial (e.g., high-k vs. low-k) and economical point of view as well. The paper alsoaddressesalternativenon-CMOSdevices(i.e., nanodevices)thatare potentially able to solve the CMOS problems and limitations.Key words: CMOS, constant-fieldscaling, lithography, dy-namic/static power, highllow-kmaterials, nanodevices.I. INTRODUCTIONThe concept of 'MoreMoore"referstothecontinuedscal-ing of horizontaland vertical physical featuresizes of silicon-based complementary metal oxide semiconductor (CMOS)transistors [1]. This tremendous effort has been the mainimpetus in producing today' s sophisticated technologies ofelectronicsdevices. Thescaling theory that proposed by Den-nard et al. in 1972 is the starting point of this success story [2].However,semiconductor industrystarts topractice thistheoryin CMOS transistors a decade later. Since then, more and moretransistors were able to be integratedinto single integratedcircuit (IC) chip. In 1965, GordonE. Moore predictedthatthe number of transistorswhich can beplaced in cutting-edgeICchipsisdoublingapproximatelyeverytwoyears withoutcorrespondinglyincreasingthecost of thechips[3].Although thescaling of CMOStransistors has past throughsome 'brickwall" predictions as reportedin [4], pessimistsbelieve that it will finallyreach the boundaryat size of 22 nmas forecastedintheInternational TechnologyandRoadmapforSemiconductorsITRS2007[1], approximatelyattheendofnext decade. Theyfrequentlycitethat CMOStransistorsare approachingatomistic andquantummechanical physicsboundaries [5]. Furthermore, the concernis not only abouttheinabilityof thedevicesitself tocontinueoperatesteadilybut alsothe constraints fromthe economic andtechnologypoint of view.This paper addresses the important challenges that couldhinder CMOS frombeingutilized in future. It divides thechallengesintofivecategories, specifically: Physical challenges: These are due to the incrementof tunneling and leakage currents as the devices arebecoming smaller, thus impacts the performance andfunctionalityof CMOSdevices. Material challenges: These basically come fromtheinabilityof the dielectric and wiring materials topro-vide reliable insulation and conduction, respectively withcontinuedscaling. Power-thermal challenges: These are because of the everincreasingnumber of transistorsintegratedper unit-area,which demands larger power consumption and higherthermaldissipation. Technological challenges:These are the results from theincompetency of lithography-based techniques to providethe resolution below the wavelength of the light tomanufacturetoCMOSdevices. Economical challenges: These are mainly due to therisingincost ofproduction, fab, andtestingthat mayreach a point where it will be not affordable fromeconomicpoint of view.In this paper, each of the above challenges will be analyzed.Alternative non-CMOS nanodevicesthat arepossibletosolvetheCMOSlimitationwillbealsopresented.The remainder of this paper is organized as follows. SectionII give a brief overviewabout the principle structure andelectrical parameter of metal oxidesemiconductor field-effecttransistors (MOSFETs)inorder tofacilitatethe readability oftherestof thepaper. SectionIII, IV, V, VI, andVIIdiscussindetail thephysical, material, power-thermal, technological,and economical challenges of CMOS technology, respectively.SectionVIII suggests potential non-CMOSnanodevices thatare able to solve CMOS limitations. Finally, Section IXconcludesthepaper.II. MOSFET DEVICE OVERVIEWBeforewego further, wefirstoverviewthe principlestruc-tureandimportantparametersof thecoreunitof CMOSi.e.MOSFETs. It will giveus firmunderstandingof thescalingproblems. Thename 'metal-oxide-semiconductor' representsthe materials used to formthe early fabricated MOSFETs.Figure 1 shows the typical structure of a MOSFETwiththe three material layers: the metal gateelectrode, thegatedielectric, and thesiliconsubstrate. Nowadays,themetal gateelectrode and siliconoxide-based gate dielectric have beenreplacedbypolycrystallinesiliconandhigh-kmaterial suchasHf-basedZr-based, respectively[6].The source and drain are formed by adding impurity dopantintosubstrate. Thesemiconductormaterial inthesourceandAuthorized licensed use limited to: Technische Universiteit Delft. Downloaded on May 03,2010 at 10:13:41 UTC from IEEE Xplore.Restrictions apply. Fig. 1. Important MOSFETparameters.(b)VisC3DI INa/s '- 'LisBarrier height.................Ef , ...Vds(d)INaLII I

(a)EcVds(c)Oxidecapacitance,CoxBDrain-Source Current,Ids Width, /W // f---f------l...-,-----,-----l...--"--+---(Gate-SourceGround(,drainregionis dopedwithadifferent typeofmaterial thaninthe regionunder the gate. For example, if the substrateisdopedwithpositivetype(p-type) material suchasBoron,thesourceanddrainwill bedopedbynegative-type(n-type)materialsuch as Arsenic. Inthiscase, an n-channelMOSFET(n-MOSFET)willberealized.Thearea betweensourceanddrain beneath thegate, chan-nel' haslength of L andwidth of W; it iswheretheinversionlayerisformedwhensufficient voltageisbiasedtothegateanddrainwhichthentumontheMOSFETs. The oxide layerwith certainthickness, tox, separatethegateandthechannel.According to [9], Land tox of 35 nm and1.2 nm, respectively,havebeendemonstratedin65nmtechnologynode.There are few important parameters that determine thecharacteristicsof MOSFETs(seeFigure1): Oxidecapacitance, Cox, isthecapacitanceper unitareabetweenthegatemetal andthebulksurface. Gate-source voltage, VGS, is the voltage that appliedbetweengateandsourcetocontrol theoperationof thetransistor. Drain-source voltage, VD s, is the voltage which is appliedbetweendrainandsource. Thresholdvoltage, Vr, istheminimumvoltagethatwillinduceinversionlayerwhichtumonthetransistor. Drain-sourcecurrent, IDS, is thecurrent that flowbe-tween drain and source through the inversion channelconductedbeneath thegatewhentransistor isturnedon.III. PHYSICALLIMITATIONThebasicideaof constant-fieldscalingof CMOStransis-tors' physical feature andtheircorrespondingbanddiagramareshowninFigure2. For theoriginal deviceasdepictedinFigure2(a), thechannelhavelengthof L, oxidethicknessoftox, biasvoltageofV andsubstrate dopingofNa. WhilethescaleddeviceinFigure2(b), all parameters areaffectedbythe scaling factor, s0.7 [11].The channel length is reducedtobeLxs, oxidethicknessbecomes toxxs, biasvoltage isdecreasedtobeVxs, andsubstratedopingis increasedtobeNa/s.Fig. 2. CMOSconstant-fieldscalingidea.A. DecreasingdevicesdimensionThe scaling of physical dimension includes the reduction ingate dielectric thickness and channel length; they are addressednext.1) Gate dielectric thickness: The gate electrode togetherwith gatedielectriccontroltheswitching operation of CMOStransistors. The voltage of the gate electrode controls theflowof electric current across the transistor. The gate dielectricshould be made as thin as possible to increase the performanceof the transistor. In additional, it is critical to keep short-channel effects undercontrol whenatransistoris turnedonandreducesubthresholdleakagewhenatransistorisoff. Inorder tomaintaintheelectricfieldas CMOStransistors arescaled, the gate dielectric thickness should also be shrunkproportionally. An oxide thickness of 3nmis needed forCMOStransistorswith channel lengths of 100 nm or less[7].This thickness comprises onlyafewlayers ofatoms andisapproachingfundamental limitswhichisaround1 to1.5nm[8]. The thinoxidelayer is subject toquantum-mechanicaltunneling, givingrisetoa gateleakagecurrentthatincreasesexponentially as the oxide thickness is scaled down. Thistunnelingcurrentcaninitiatea damageleadingtothefallibleof thedielectric[9].2) Short channel: Short channel enables faster switchingoperationsinceless timeis neededfor current toflowfromsourcetodrain. Howbeit, several negativeeffectscouldarisefrom it.A high off-state drain leakage current, loff' flow eventhough the transistor is turned off. The band diagrams in Figure2(c)and(d)represent the energy barrier that majority carriersinthesource terminalneedsto overcome to enter thechannelfor the original device and scaledversion, respectively. AswecanseeinFigure2(d), thebarrier heightisloweredthusreducesthethresholdvoltageusedtoformadepletionlayer.Both ends of this short-channel may merge when a sufficientlylarge reverse-bias voltage is applied to the drain terminal.Consequently, many majority carriers start to flow from sourcetodraineven if thegatevoltage isbelowthethresholdvalue,which result inpunch-through, drain-induced barrier lowering(DIBL) [11] andthresholdvoltageroll-off[12]. Thesethreeproblemscausedropinthresholdvoltagelevel, subsequentlyleakagecurrents[12].Authorized licensed use limited to: Technische Universiteit Delft. Downloaded on May 03,2010 at 10:13:41 UTC from IEEE Xplore.Restrictions apply. B. Lowering power and threshold voltagesScalingthepowersupplyvoltageenablesthereductionindynamicpower dissipation. Whilereducingthepower supplyof a chip might seem straightforward, nevertheless,it leads toissuessuchasnoisesandpossiblysignallevelscompatibilityproblemsinmultichipsystemsusingvarioussupplyvoltages[10]. Reduction in power supply, which also reduces thresholdvoltagealsoincreases staticpowerduringtransistor offdueto leakage current. In [12], an analysis of the impact ofsupplyvoltagescalingonthenoisemarginof CMOSNANDwas performed; it concludes that the supplyvoltagecannotbe scaled lower than 0.5 Vin order to keep logic stateconsistency in the worst-case switching scenario.As thresholdvoltage is reduced as well, the transistor cannot be completelyturnedoff. Thetransistor operatesinaweak-inversionmode,withasubthresholdleakagebetweensourceanddrain. Thereductionof thresholdvoltageofabout 85mVwill increasethesubthresholdleakagecurrentby10times [11]. Hence, itresultsindegradationof powerandspeedefficiency.C. Increasingchannel dopingInordertocontrol short channel effects, it isdesirabletoincreasethechannel doping. However, this effort introducesother effectssuch asslower carrier mobilityand band to bandtunneling[13]. Inaheavilydopedchannel, carrier mobilitydecreases severelydue tohightransverse electric field andimpurity scattering. The on-state drain current, Ion, is reduceddue tolarger capacitance inhighdepletion-charge channel.Inaddition, a highchannel dopingwill alsoresultinbandtoband tunneling leakage. Furthermore, the formation of shallowchannel due to thermal budget of dopant activation causeshigher resistance thus reduces drain current [11]. Greaterdopant concentrationalsocausesgate-induceddrainleakagecurrent (GIDL) [14]. Therefore, increasing the channeldoping will negatively impact the CMOS performance andfunctionality.Insummary, scalingefforts weresuccessful inincrementingCMOS performance, reducing power consumption, whilekeeping high qualityand reliable devices. Today, nonetheless,theseeffortsarebecominghardtorealize, asthetechnologynodeapproachingtolimit(e.g. 10 nm).IV. MATERIALLIMITATIONNewmaterialsareintroducedinorder tokeepupwiththescalingof CMOStransistors. Figure3showsthechangesinthree decades starting in1980 [15], [16]. This effort is done inorder to ensure the manufacturability and reliability of devices.Material such as Silicon (Si), Silicon dioxide (Si02),Aluminum(AI), Copper (Cu) andSalicides areboundedbytheir physic capabilities such as relative dielectric constant(E), carrier mobility (J.1), carrier saturation velocity (vs),breakdown fieldstrength (Ec) and conductivity[17]. As thesematerial reach their physical limit, devices cannot keepupHigh-k material,--)__--'Low-k material,-I__---') CopperTungstenSilicideAluminumPolycfYstalline siliconSiIicon nitrideSilicon dioxideSilicono000'1Year of IntroductionFig. 3. Introductionof newmaterials.withtheir performance. The Si02reliability degrades as itbecomes thinner andresult inbreakdown [4]. AlthoughCuis less sensitivetoelectromigrationthanAI, the material ismore susceptibletoopendefect whenusedas interconnectwires. Low-k materials utilized for back end process (e.g.insulator between adjacent interconnect wires to minimizecross talk)suffer fromthe high mechanicalandthermalstressduringpackaging phase. Asreportedin[9], high-permittivity,kmaterials has beenused in45 nmtechnology toreplacesiliconSi02as gate dielectric. The high-kmaterials couldminimizethecurrent leakageproblemwhenthedielectricismade to become thinner to support physical scaling. However,thetendencyof thesematerialstochangetheirpropertiesinhightemperatureisamongthechallengesneedtobesolvedapart of adding new manufacturing process [19]. Severalchallengesarealsoreportedin[1] suchasappropriatetuningofmetal workfunction, ensuringadequatechannel mobility,gatestackintegrity, andalsothereliabilityof thematerial.In summary, available materials do not satisfy the requirementtorealizesmaller CMOSdevices. Moreover, theincapabilitytoprovide reliable characteristics as well as unprecedentedunknownreliabilitymechanismsof newmaterialsimpactthedevelopment of CMOSscaling.V. POWER-THERMALLIMITATIONSince the supply voltage, Vnn, has not been scaling asfast aschannel length, L, thepowerdensityhasinfact beengrowing[15]. Therearetwotypesof power densitydissipateby per unit area of integrated circuit (IC) chips namelydynamic power density and static power density [18]. Dynamicpower densityis dissipated whentransistor is switchedon.While static power density dissipation originates fromtheleakagesource-draincurrentwhentransistor isswitchedoff.Figure 4 depicts both dynamic power density and staticpower density based on measured industrial data as mentionedin [15], at junctiontemperatureofTj=25e. TheformerAuthorized licensed use limited to: Technische Universiteit Delft. Downloaded on May 03,2010 at 10:13:41 UTC from IEEE Xplore.Restrictions apply. Optical view of masks (patterns)1997 1998 2000 2002 2004 2006 2008 2010scaling. Ironically, the lithography processes cannot cope withthe shrinking feature of CMOS transistors'layout. Lithographytechniques such as proximity X-ray steppers and ion beam arelimitedbydifficultiesincontrollingmask-wafer gapanduni-formexposureof photoresistsonwafer respectively. Anotherproblemistheinabilityofpolishingprocesstomaintaintheuniformthickness ofwafer andreliablemaskas mentionedin [14]. According to [20], patterning smaller feature thanwavelength of light requires trade-off between complex, costlymasks and possible design constraint. Figure 5 shows theevolution of mask fromthe180 nmtechnologyto thecurrenttechnology[22]., Dynamic- .. . _ .. _.... .. .. A power density',A .........#., ~ ..~ . A." . ~ . - ..-... ~ ., ., ."ttl.... . . ~ ..' . ~.. ~ ~ .,Static "power density .. ",.,,,. ..1000100~ 10e~~0.1'00s::~0.01....Q)~0.001 0Q...0.00010.000010.01 0.1Gate length (urn)For 180 nmtechnology, simple masks without opticalproximitycorrection(OPC) are sufficient topatternCMOSdevices. Whenit comes to 130nmtechnology, Rule/ModelbasedOPCis alreadyneeded. As thetechnologyshiftsintobelow100nm, the masks becomemorecomplexandmoreadvancedtechniques arerequired. Moreover, it still adoubthowthefuturemaskswill be.As reportedin [22], patterningoffeatures to20nmandbelowhas been demonstrated by a variety of techniques.Newer techniques likes 248nmradiationhas beenusedtomake 9 nm devices.However,the complexity of the processesinvolvedmaycausesuchapproachestobeuneconomical. Inaddition, non-radiation patterning techniques (e.g. nanoimprintlithography)alsoappear veryattractivebutpresentlylacktheinvestment neededtomakethemattractiveforsemiconductorICmanufacturing[22].Fig. 4. Power densitytrendinCMOS[15].found to be slightly more than10 W/cm2at gate length of 0.9/-Lm, while,thelatter foundto haslower value(approximately200000times smaller for the same gate length). However,the power densities for bothofthemare becominggreateras gate length becomes smaller. It is more severe to thestatic power density where at the gate lengthof20nm, itwill beequivalenttothedynamicpowerdensity. Intherealoperation, itturnstoworstbecausetheTjisobviouslymorethan25e.Power dissipation is proportional to the thermal heat.It means that, more heat is run away as greater poweris dissipated. As reported in [21], a high performancemicroprocessor, whichuses 10KWof power, candrawheatat 1KW/cm2. For example, the power density of Intelmicroprocessorisgrowingwiththenewgenerations. Before1990s, the power density was below10W/cm2, but whenPentium family processor was introduced in 1990s, thepower densityincreasesexponentially. It isprojectedthattheprocessorcanbeas hot as rocket nozzlewhenapproachingthe end of this decade if the current scaling trend is stillcontinued without taking any prudence measures to tacklethispower-thermal problem. Asaresult, Intelcanceledits4GHzPentium4in2001duetoheatdissipationproblem.Consequently, theyannounceddualcoreprocessors.In summary, although scaling materializes one billionofCMOS transistors in a single chip, the augmentationinintegrationcontributes tothe power and thermal problems.This negatively impacts the performance and reliability ofCMOStransistor.NoOPCr=-rl'.......!Rule/Model ModelBaedBaled OPC OPe, SRAFAAPSM+ trimAI Fig. 5. Evolutionof maskpattern[22].Nutg...?VI. TECHNOLOGYLIMITATIONCMOS transistors are basically patterned on wafer by meansof lithography and masks. It means that the lithographytechnology is one of the maindrives behindthe transistorInsummary, thecurrentoptical-basedfabricationtechnologycannot support the resolution that are needed to patternfeature smaller CMOSsizes. Unless, this rudiment physic'slawcan be violated, this technology must be replaced toensuresmaller patterncanbefabricated.Authorized licensed use limited to: Technische Universiteit Delft. Downloaded on May 03,2010 at 10:13:41 UTC from IEEE Xplore.Restrictions apply. VII. ECONOMICLIMITATION VIII. POTENTIAL TECHNOLOGIESBEYOND CMOSFig. 6. Wafer foundrycost.1998 2001 2004 2007 2010YearAnother biggest drivebehindthedownscalingis theeco-nomic consideration. The rising cost in semiconductor sector isbasically contributed by the cost of production, and testing thatescalating exponentially with time as the CMOS size is scalingdown. As predicted by the National Institute of Standardsand Technology (NIST), a newwafer foundary could costapproximately 25 billiondollar today, andwill increasebyone-foldin2010asdepictedinFigure6[23].Because of numerous limitations of CMOS such as dis-cussedinSectionIII toSectionVII, it is expectedthat thetransistor will end (or partially end) it service at the endof next decade [1]. Alternative devices are needed to bethecomplementoreventhereplacement toCMOSinfuturecircuits.The nanodevices can be categorized into three classes[30]: Electrical-dependent nanodevicesThey are basedeither on ballistictransport, tunnelingoronelectrostaticphenomenon. Inthecaseofballistictransport the electrons travel without resistivity in amedium(material) [32]. In the case of tunneling, theelectronscanpass throughapotential energybarrieratsome level of energyas resultsof a quantum-mechanicalprocess [32]. In the case of electrostatic, the interaction ofelectrons happens with the presence of electric field[31].Examples of nanodevicesbelongtothisclassarecarbonnanotubes field-effect transistors (CNTFETs), semicon-ductor nanowirefield-effecttransistors(NWFETs), reso-nant tunnelingdiodes (RTDs), singleelectronjunctions(SEJs), and electrical quantumdot cellular automata(EQCA) [31], [32].2010 = $50B -100/0 of !annual marketCost of new Fab60~ 50=a40~ 30~ 20u~ 10~ O t . . = = = . r r ~1989 1992 1995The cost explosion is also primarily contributed by theequipment cost, clean room facilities, and lithography processcomplexity [8],[24]. Traditional top down silicon basedfabricationrequires over 35 masks, and700steps for a90nmprocess [25]. The same trendis alsostatedin [26] forDRAMprocess fabrication. To gain sufficient profits, [27]statesthat on theaverage, DRAMsneed3000 to5000 wafersper maskset, 1500for amicroprocessors, and 500or lessforASICsandSOCs(Le. for 130nm technology). Moreover,design revisions cause a hike in mask cost, and reductionin the number of wafer that can be produced in singlemaskset. The maskcontributionis becomingthedominantfactor inlithographycosts, particularlyas minimumfeaturesizes fall belowthe exposure wavelength. These problemslead to the combination of wafer production to the bestequippedfoundaries [28]. The alliances betweencompaniesand participation fromuniversitiesandgovernment that injectfundingarealsothestrategyusedtoreducethecost [4].Smallersizecircuit isvulnerabletohardandsoft defects.Thesedefective-pronecircuitsneeds tobetestedthoroughlyin order to guarantee the required quality. However, moresophisticatedtest method will incur additional testing stepsandtimethusincreasingtestcost [29].Insummary, thesuccessinfutureCMOSscalingrequires ahuge investment by semiconductor manufacturers. In spiteofthat, it is not clear ifthehighinvestment canguaranteehigherprofit marginduetoincreasingincost ofproductionoperationandtesting. Magnetic-dependentnanodevicesMagnetostaticand spintransportarethephenomena fortheoperationofthedevices belongingtothis class. Inthecaseofmagnetostatic, the magnetic dipoleinterac-tions aremanipulatedtocarrytheinformation [32]. Inthe caseofspintransport, the spinpolarizedelectronstransportationcanbe maintainedbythe magnetic field[32]. Theexampleofnanodevices belongtothis classare magnetic quantum dot cellular automata (MQCA) andspinfield-effect transistors(spinFETs)[31], [32]. Mechanical-dependentnanodevicesRestructuring of conductive polymers is the phenomenonfor this category. The structure of the polymer movesorchangeswhenactivatedbyinput sources [32]. Thesenanodevices have been utilized in molecular memory andFPGA[30].Thesenanodevices possess someadvantages comparedtoCMOSdevices. CNTFETshaveanextraordinarymechanicalstrength,low power consumption, better thermalstability,andhigherresistancetoelectromigration[31]. TheadvantagesofNWFETsoverCMOSaresimilartocarbonnanotubebaseddevices [31], plus the ability to operate at high speed, producessaturatedcurrent atlowbiasvoltage, andthepotentialtobe-have as either active or passive devices in single nanowire [32].Thebenefits ofusingRTDs insteadofCMOSinelectroniccircuits are related to faster operation, reduced componentcount pertransistor, higher circuit density, andlower powerconsumption [31]. The avail of SEJs compared to CMOStransistors are better scalability, faster operation, and lesspower consumption [31], [32]. EQCAand MQCAexhibitAuthorized licensed use limited to: Technische Universiteit Delft. Downloaded on May 03,2010 at 10:13:41 UTC from IEEE Xplore.Restrictions apply. greatnessinlowpower dissipation, non-volatility, andrecon-figurability[32].SpinFETs have the advantages of high powergain, small off-current, low power consumption,tunable, highoperating speed, nonvolatile, and better noise margin comparedto CMOS [31], [32]. The extremely small-size molecularelectronic devices, whichare lowpower, scalable, andcanbeself assembled[32].IX. CONCLUSIONInthispaperwehavediscussedthemainchallengesfacedby CMOS technology. The challenges are addressed fromdifferent perspectives; physical, material, power-thermal, tech-nological,and economical.We have also presented alternativedevicesthat arepotentiallyabletoovercomethelimitationinCMOStechnology.At present,the research of these emergingnon-CMOS nanodevices is still in its infancy phase. Therefore,researchers are urged to continue exploring and inventingthese new, high-performance, andcost-effective non-CMOSnanodevicesbeforetheextinctionof CMOS.REFERENCES[1] IntI. TechnologyRoadmapfor Semiconductor 2007EditionExecutiveSummary. http://www.itrs.netiLinks/2007ITRS/ExecSum2007.pdf.[2] R. H. Dennardet al., "DesignofMicron MOS Switching Devices",presented at the IEEE IntI. Electron Devices Meeting, 6 December,1972.[3] G. E. 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