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1

CMOS Scaling and Variability

2012. 1. 30

NEC

Tohru Mogami

WIMNACT WS 2012, January 30, Titech

WIMNACT WS & IEEE EDS Mini-colloquim on Nano-CMOS Technology

January 30, 2012, TITECH, Japan


Acknowledgements

• I would like to thank members of Robust

program in MIRAI project for supporting data,

and especially Dr. A. Nishida for discussing a

lot of issues.

• This work is supported by NEDO.

2

WIMNACT WS 2012, January 30, Titech 3

Outline

1. CMOS scaling and Variation

2. Evaluation methods of Variation

3. How to improve variation?

4. Summary


New structures

New materials

Lg=1.0mm Lg=0.5mm Lg=0.25mm Lg=0.18mm

Lg=0.13mm

70-90nm

40-60nm

20-30nm <10nm

SDE, Halo Dual gate

Performance of PMOS

Oxide Nitridation

Low gate leakage

Plasma Nitridation

High Quality of

Gate Oxide

Local stress

High Mobility

Compensate of

Device variation

Relaxation of

Electric field

LDD

structure

Reduction of

resistance

Salicide

Planer/3D CMOS

w/ HK/MG

Need new device

& new process

Scaling

Variability

Issue

10-15nm

CMOS scaling and Breakthrough technologies

T. Eimori, SFJ2006

Modified by A.N.

HK/MG

4


CX1

CX2

CX3

CX4

CY0

CY1

CY2

CY3

0.50.5020.5040.5060.5080.51

0.5120.5140.5160.5180.52

0.5220.5240.5260.5280.53

0.5320.5340.5360.5380.54

0.5420.5440.5460.5480.55

Vth

CX

CY

Vth distribution in wafer

Systematic variation on wafer

系列1

系列23

系列45

系列67系列89系列111

0.5

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

1 9 1725334149 57

0.57-0.58

0.56-0.57

0.55-0.56

0.54-0.55

0.53-0.54

0.52-0.53

0.51-0.52

0.5-0.51

X 1

10

系列1

系列23

系列45

系列67系列89系列111

0.4

0.45

0.5

0.55

0.6

0.65

0.7

1 9 17253341 49 57

0.65-0.7

0.6-0.65

0.55-0.6

0.5-0.55

0.45-0.5

0.4-0.45

Systematic & Random variation on chip

5

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

0 0.2 0.4 0.6 0.8 1 1.2

Vg [V]

Ids [

A]

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

0 0.2 0.4 0.6 0.8 1 1.2

Vg [V]

Ids [

A]

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

0 0.2 0.4 0.6 0.8 1 1.2

Vg [V]

Ids [

A]

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

0 0.2 0.4 0.6 0.8 1 1.2

Vg [V]

Ids [

A]

1M DMA-TEG on chip

Vd=1.2

V

Vth variation on chip and on Wafer

Subthreshold characteristics

of 200 devices on each chip

Vth mapping


-6

-4

-2

0

2

4

6

0 0.2 0.4 0.6 0.8 1

σ

Vth (V)

NMOS

PMOS

|Vth| [V]

Norm

al D

istr

ibution

No

rmal D

istr

ibutio

n

|Vth| [V]0.2 0.4 0.6 0.8

Vthc

-5

-3

-1

1

3

5

Normal Distribution

0.2 0.4 0.6 0.8

Vthc

-5

-3

-1

1

3

5

Normal Distribution

6

4

2

0

-2

-4

-60.2 0.3 0.4 0.5 0.6 0.7 0.8

Co

un

t [a

.u.]

|Vth| [V]0.2 0.4 0.6 0.8

NMOS

PMOS

Vth random variation of N/P-FETs

For 1M devices, Vth variation shows normal distribution.

For 256M, Vth variation of NFET shows normal, but that

of PFET shows normal and tail distribution.

(a) Vth variation for 1M devices (b) Vth variation for 256M devices

6


Physical parameter L : Gate length

W : Gate width

Tox : Gate oxide thickness

Nsub : impurity in Si substrate

etc.

L, W scaling → Enhance of variation by √(LW).

LW3

WN

C

qVt

depsub

inv

Threshold

voltage

Standard

deviation

inv

DEPsubSFB

C

WqNVVt

Physical parameter vs. Vth variation

Theoretical threshold voltage and its standard deviation

What is the relationship between physical parameters of

MOSFET and Vth variation?


Variation mechanisms

Dopant fluctuation

Potencial distribution

① Random Dopant Fluctuation (RDF)

Depend on channel dopant fluctuation

Depend on local grain-depletion

④ Local grain depletion of gate (LGD)

700nm

700nm

③ Oxide Thickness Fluctuation (OTF)

Depend on gate insulator variation

S D

channel

Depend on local variation of gate length

② Line Edge Roughness (LER)

8

Random variation can come from several origins.

RDF and LER are the main origins of the random variation.


Vth Random Variation & Pelgrom Plot

9

M. J. M. Pelgrom et al., IEEE JSSC, vol.

24, p. 1433, 1989.

DEPSUBINVVT WNtA

LW

AVTVTH

Dr. Pelgrom proposed

and demonstrated the

simple evaluation

method of the random

variation in 1989.

This is based on the

simple statistics and

useful.


Vth variation prospect

75 1001/(LW)0.5 [um-1]

00

0.2

0.6

Vth

[V]

0.4

5025

Tox=2nm

32nm

65nm

Avt=2.0

Avt=3.8

15nm

7nm

Avt=1.0

75 1001/(LW)0.5 [um-1]

00

0.2

0.6

Vth

[V]

0.4

5025

Tox=2nm

32nm

65nm

Avt=2.0

Avt=3.8

15nm

7nm

Avt=1.0

Pelgrom plot can foretell the

simple prospect of Vth variation.

Simple device scaling-down can

happen large Vth variation.

If Avt keeps 3.8, 7nm FET will

have about 400mV in Vth

variation.

Device parameter optimization,

such as Tinv and gate work

function, can improve the

variation.

If we need <100mV in Vth

variation at 7nm FET, Avt should

be 1.0.

Need the new technology of

variation improvement for the

future generation.


Outline




4. Summary


Pelgrom Plot

12

Pelgrom plot has been a simple and useful method to

evaluate the random variation.

Is there any issue of Pelgrom plot? Is variation of 25nm

MOSFET really

smaller than that of

50nm MOSFET?


0 1 20

4

8

12

VT

H S

tan

da

rd D

evia

tio

n (

mV

)

1/(LW)1/2

(mm–1

)

Pelgrom Plot

Low NSUB

Small TOX

High NSUB

Large TOX

Device with

the same

LW

Slope: AVT

K. Takeuchi et al. Silicon Nano. Workshop, p.7, 2007.

K. Takeuchi et al. IEDM, p. 467, 2007.

Issue of Pelgrom Plot

Pelgrom plot is very useful

when the data come from

the devices with the same

Tox and Vth. It can make

variation date into a

straight line.

However, for the devices

with the different Tox and

Vth, pelgrom plot cannot

make those into a straight

line.

13


LW

WN

C

q DEPSUB

INV

VTH3

LW

VVTB FFBTHINV

VTVTH

)2(

INV

DEPSUBFFBTH

C

WqNVV 2

LW

VVTq FFBTHINV

OX

)2(

3

K. Takeuchi et al. Silicon Nano.

Workshop, p.7, 2007.

K. Takeuchi et al. IEDM, p. 467, 2007.

1.02 THFFBTH

INV

DEPSUB

VVVC

WqN

Determined by

Impurities –0.1V for poly-Si gate.

It varies in metal gate +0.1V

OX

VT

qB

3Where,

New normalization method has been proposed by Dr. K. Takeuchi.

This can handle the variation data for devices with and w/o different Nsub and Tox.

New normalization method

14


Takeuchi Plot

Pelgrom plot can handle variation data for devices

with the same Vth and Tox.

Takeuchi plot can handle both data and make them

into a line if the process is the same.

15

0

10

20

30

40

50

60

V

th[m

V]

0 2 4 6 8 10

1/√LW [um-1]

○○○ HVth

□□□ MVth

△△△ LVth

Tox=4nm

Tox=

3nm

Tox=2nm

0

10

20

30

40

50

60

0

10

20

30

40

50

60

V

th[m

V]

0 2 4 6 8 10

1/√LW [um-1]

0 2 4 6 8 100 2 4 6 8 10

1/√LW [um-1]

○○○ HVth

□□□ MVth

△△△ LVth

Tox=4nm

Tox=

3nm

Tox=2nm

0

0.01

0.02

0.03

0.04

0.05

0.06

0 5 10 15 20 25

しきい値標準偏差

sqrt(Tinv*(Vth+0.1)/(L*W))

竹内プロット NMOS

0

10

20

30

40

50

60

V

th[m

V]

0 5 10 15 20 25

√TINV(Vth+0.1)/LW [nm0.5・V0.5・um-1]

○○○ HVth

□□□ MVth

△△△ LVth

Tox=4nm

Tox=3nm

Tox=2nm

0

0.01

0.02

0.03

0.04

0.05

0.06

0 5 10 15 20 25

しきい値標準偏差

sqrt(Tinv*(Vth+0.1)/(L*W))

竹内プロット NMOS

0

10

20

30

40

50

60

0

10

20

30

40

50

60

V

th[m

V]

0 5 10 15 20 250 5 10 15 20 25

√TINV(Vth+0.1)/LW [nm0.5・V0.5・um-1]

○○○ HVth

□□□ MVth

△△△ LVth

Tox=4nm

Tox=3nm

Tox=2nm

Pelgrom plot Takeuchi plot


0.35um-65nm devices have been analyzed by Takeuchi Plot, which

can normalize L, W, Vth, and Tox.

Vth variation of NFET was larger than that of PFET for every

generation.

PMOS random variation is determined by RDF.

Origins of NMOS random variation are RDF and others.

AV

T o

r B

VT

0

2

4

6

8

Line-A

P-channel transistors

AV

T o

r B

VT

0

2

4

6

8

N-channel transistors

x 1.5

Dopant fluctuation (flat doping)

BVT

AVT

0.35mm 65nm

90nm

Dopant fluctuation (flat doping)

Process Technology

0.35mm 65nm 90nm

Process Technology

Line-B

Line-C

Line-D

Line-E

Robust

Line-A

Line-B

Line-C

Line-D

Line-E

Robust

BVT

AVT

Vth Random Variation

16


Outline




4. Summary


Variation difference

18

Takeuchi plot has revealed that Vth variation of NFET

was larger than that of PFET for every generation.

Only NFET with channel Boron showed reverse short

channel characteristics. This indicated that channel

Boron can be segregated near the junction edge.


Enhanced Variation mechanism

Boron transient enhanced diffusion (TED) can be the origin of reverse

short channel effect and the larger Vth variation of NFET.

After As I/I for S/D region, interstitial Si (I-Si) has randomly produced

near S/D region.

During S/D annealing, B makes BI complex with I-Si and diffuses in

the channel near S/D edges rapidly to happen TED.

After annealing, B has pileup in the channel region at the edge of the

S/D region.

To control B TED, we need a new technique.

(a) After As I/I (b) During annealing (c) After annealing


Co-implantation for diffusion control

Co-I/I can suppress dopant

diffusion and achieve

shallower Xj.

Better short channel effect

and better device

characteristics.

F I/I for PFET: 5E14-2E15

Fluorine co-I/I for shallow P+ junction

Co-I/I for shallow N+ junction

20


Carbon co-implantation for diffusion control

Carbon co-I/I can control dopant diffusion for NFET.

Better short channel effect and on-current by C co-I/I

C.F. Tan et al., VLSI-TSA 2008 21


Effect of co-I/I method

There are several reports for diffusion control by using

Nitrogen, Silicon, Fluorine, and Carbon.

We have tried co-I/I method to mitigate Vth variation.

However, co-I/I using Nitrogen, Silicon and Fluorine

showed no effect to mitigate Vth variation.

22

30

5

10

15

0 1 2 4 5

RefF co-I/I

σV

T[m

V]

√Tinv*(VT+V0)/LW [nm0.5V0.5µm-1]

N co-I/ISi co-I/I

30

5

10

15

0 1 2 4 5

RefF co-I/I

σV

T[m

V]

√Tinv*(VT+V0)/LW [nm0.5V0.5µm-1]

N co-I/ISi co-I/I


Carbon co-I/I for Variation mitigation

C co-I/I has improved reverse short channel effect w/o

performance degradation for NFET.

Furthermore, C co-I/I has mitigated Vth variation of NFET.

This is because Boron TED (Transient Enhanced Diffusion)

in channel can be suppressed.

T.Tsunomura et al., VLSI Symp 2009, p.110.

0 5 10 15 20

50

40

30

20

10

0

50

40

30

20

10

0

√TINV(Vth+V0)/LW [nm0.5・V0.5・μ m-1]

V

th[m

V]

w/o C co-imp

BVT=2.7

With C co-imp

BVT=2.3

0 5 10 15 20

50

40

30

20

10

0

50

40

30

20

10

0

50

40

30

20

10

0


V

th[m

V]

w/o C co-imp

BVT=2.7

With C co-imp

BVT=2.3

0 5 10 15 20

50

40

30

20

10

0

50

40

30

20

10

0


V

th[m

V]

w/o C co-imp

BVT=2.7

With C co-imp

BVT=2.3

0 5 10 15 20

50

40

30

20

10

0

50

40

30

20

10

0

50

40

30

20

10

0


V

th[m

V]

w/o C co-imp

BVT=2.7

With C co-imp

BVT=2.3


局所電極

Laser

Beam

Vtotal

Vextraction

位置敏感検出器

~100nm

ZY

X

試料

局所電極

Laser

Beam

Vtotal

Vextraction


~100nm

ZY

X

試料Specimen

Local electrode

Position-sensitive detector

3D Atom Probe System

3D Atom probe method can analyze

Si-MOSFET structure, including gate

insulator.

RDF in channel can be measured by

3D Atom Probe.

3D Atom Probe Analysis of Si-MOSFET


Atom probe analysis of Boron diffusion

25

局所電極

Laser

Beam

Vtotal

Vextraction


~100nm

ZY

X

試料

局所電極

Laser

Beam

Vtotal

Vextraction


~100nm

ZY

X

試料Specimen

Local electrode

Position-sensitive detector

3D APT System

Carbon co-I/I analysis revealed that Boron and carbon co-

clusters formed around the projection range of boron

Boron TED was suppressed by those.

Y. Shimizu et al., APL, 98,

232101, 2011.


Summary

❒Variation is the most important issue for the

Advanced CMOS & LSI’s.

❒New variation evaluation method, Takeuchi plot,

is very useful.

❒Boron TED can be the origin of the larger Vth

variation of NFET.

❒To mitigate this variation of NFET, Carbon co-I/I

technique is very useful.

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