A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback

Buffer Amplifier

Wonseok Oh, Bertan Bakkaloglu, Bhaskar Aravind*, Siew Kuok Hoon*

Arizona State University*Texas Instruments Inc

Motivation for Local Supply Management

• With the reduction of the supply voltage, noise and cross-coupling on the power supply line starts playing a dominant role in an RFtransceiver noise budget.

• Synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratio (ACPR) of the PA are heavily influenced by the supply noise and ripple.

• Linear low dropout (LDO) regulators shield sensitive blocks fromhigh frequency fluctuations on the power supply and provide highaccuracy, fast response supply regulation

Application Example: RF Synthesizers

AGGRESSORS AND VICTIMS:• PFD/CP Drivers/Multimodulus dividers generate high current spikes withspectral content that can corrupt global supply.• Low slew rate clock xtal osc./xtal buffers/drivers/VCO are sensitive to supply noise.

Supply partitioning should not only isolate noise into sensitive blocksbut should also improve kickback from noisy blocks into global supplyplane.

Low Dropout (LDO) Regulators :Conventional Architecture

High 1/f noiseSlow transient responsePotential peaking in PSR

response

High PSR (~50dB @ 10KHz)Low Dropout VoltageGood Line Regulation(ΔVout/ΔIout)

Good Line Regulation(ΔVout/ ΔVin)

ConsPros

Low Dropout (LDO) Regulators :Noise Analysis

• Bandgap noise V2ref is

usually filtered and can be ignored.

• Pass transistor noise can be ignored due to large output (pass) transistor size and large output current.

Co

Regulation FET

R2

R1

ErrorAmplifier

Resr

Sn,ref

Sn,e

Sn,p

Sn,R1

Sn,R2

Sn,o

Vref

Unregulated Input Voltage

VoltageBuffer

Cc

+

-+

roe

( ) ( ) ( ) ( )2 2

1 12 1

2 21⎛ ⎞ ⎛ ⎞

≈ + + +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

n,o n,e n,R n,RR RS f S f S f S fR R

• Low frequency output referred noise can be estimated as:

Flicker(1/f) noise of the error amplifier becomes a dominant factor, especially for sub-micron processes at low frequencies.

• Δt1 (Δt3)is a function of bandwidth as well as slew rate of the buffer amplifier driving the parasitic gate capacitor (Cp) of regulation FET.

• The settling time Δt2 is dependent on the time requirement for the regulation FET to fully charge the load capacitor and the phase margin of the open loop response. Δt4 is the time required to discharge the output to its final value.

ILoad

Vout

∆t1

∆t3

∆t2

∆t4

time[sec]

VoutILoad

srp

clsr

cl IVC

BWt

BWt ∆

+=+≈∆11

1

Low Dropout (LDO) Regulators :Transient Analysis

[1]

[1] G.A. Rincon-Mora, and P. E. Allen, “A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator,” IEEE J. Solid State Circuits, vol. 33, no.1, pp.36-44, Jan.1998

Chopping Technique for Reducing 1/f noise and DC offset

• Modulate the baseband signal to high frequency• Error amplification & regulation processing at high frequency, push DC

offsets & 1/f noise to high frequency• Demodulate back the baseband signal • Filter out the harmonics using LPF

A

m1(t) m2(t)

Vin(t) Vout(t)

Sn(f)

f

Noise + Offsets

f0

0

00

Vin(f)

fff

fchop 3fchop 5fchop

2fchop 4fchop 6fchop

fchop 3fchop 5fchop

S1/f

SThermal

S(f)

Vout(f)•Signal after Chopping

•Noise & offset after Chopping

• Commonly used for low frequency instrumentation applications such as low noise, high precision analog IC, and audio applications

Proposed LDO Architecture:Chopper Stabilized LDO

0 fm-fm fc 2fc-fc

)f(So3

e eA S (f ))f(SA cneπ

2

( ) ( )( )( ) ( )( )

( )2 2 1 2 1

2 1π

∞

=−∞

⎡ ⎤⎧ ⎫⎡ ⎤+ + + + +⎪ ⎪⎣ ⎦⎢ ⎥≈ + ∑ ⎨ ⎬⎢ ⎥+⎪ ⎪⎩ ⎭⎣ ⎦

n c os cy e e

k

S f k f S f k fS t A S t

j k( ) )f(ZgfS)f(A)f(S omoeeo ≈

Current-Mode Feedback Buffer Amplifier

01 2

1

1 1y

CFA zox V

p p

sAVV s s

ω

ω ω=

⎛ ⎞− +⎜ ⎟⎝ ⎠≈

⎡ ⎤⎛ ⎞⎛ ⎞+ +⎢ ⎥⎜ ⎟⎜ ⎟

⎝ ⎠⎝ ⎠⎣ ⎦

13 18CFA m m mp a b dsmp,A g g g R R r≈

( )18

218

o c mp m a bp

o esr Lp c mp m a b

C C g g R R,

C R C C g g R Rω

+≈

+

m13 m18 mp a b oGBW g g g R R /C=

1 1p o dsmpC r ,ω ≈ 1z o esrC Rω ≈

m13m16

xds13 ds16

gg

Rg +2g

=

Proposed LDO Regulators :Top Level Schematic

Experimental Results :PSRR & Ripple Voltage

frequency[KHz]

PS

R[d

B]

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0mA 4mA 8mA 12mA 16mA 20mA

Ripple Voltage– 10uV with 1kHz chopping freq.– 53uV with 1MHz chopping

freq.

Power Supply Ripple Rejection>43dB @30kHz>25dB @200kHz

Power Supply Ripple Rejection (PSRR,PSR)

Ripple Voltage vs. Chopping Freq.

Experimental Results :Load Regulation & Output Noise

1.0E-10

1.0E-06

2.0E-06

3.0E-06

4.0E-06

5.0E-06

6.0E-06

7.0E-06

7.0E

+00

1.5E

+01

2.3E

+01

3.1E

+01

3.9E

+01

4.7E

+01

5.5E

+01

6.3E

+01

7.1E

+01

7.9E

+01

8.7E

+01

9.5E

+01

1.0E

+02

1.1E

+02

1.2E

+02

1.3E

+02

1.4E

+02

1.4E

+02

1.5E

+02

1.6E

+02

1.7E

+02

1.8E

+02

1.8E

+02

1.9E

+02

2.0E

+02

frequency[KHz]

V/sq

rt(H

z)

Chopper_Off

fchop=500KHzfchop=750KHzfchop=1MHz

2.04

2.05

2.06

2.07

2.08

2.09

2.1

Out

put V

olta

ge[V

]

-5

0

5

10

15

20

25

30

Load

Cur

rent

[mA

]Load Regulation :

5mV/25mA with 1MHz Chopping Freq.

Output Noise Density :Chopper_Off

:6.7uV/√Hz @ 1kHzChopper_On(1MHz)

:190nV/√Hz @ 1kHz :32nV/√H @100kHz

Load Regulation Noise Density

Output noise is reduced by 35 times @ 1kHz

Die Photo

The proposed LN-LDO is designed and fabricated on a 0.25μm CMOS process with five layers of metal, occupying 0.88mm2.

Performance comparison of previous published low dropout linear regulators

>43dB@30K,>25dB @ 200K--20@50K26dBPSR

99.7694.399.97599.96Current Efficiency [%]

0.12060.0250.028IQ[mA]

50100100100Imax[mA]

14@100K936@100KIntegrated output noise(µVrms)

32@100K-1,360@100kHz70@ 100kOutput noise [nV/√Hz]

1.5~20.92.81.3Vout[V]

2~2.51.23.31.5~4.5Vin[V]

0.25μm90nm0.5μm0.6µmProcess

2006200520042004Year

This work[4][3][2]

[2] K. N Leung., P. K. T. Mok, and S. K. Lau, “A Low Voltage CMOS Low-Dropout Regulator with Enhance Loop Response,” Proc.of ISCAS’04, vol. 1, pp. 385-388. May 2004

[3] C.K. Chava and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. on Circuits and Systems I, vol 51, no 6. pp. 1041 – 1050, June 2004

[4] P. Hazucha, T. Karnik, B.A. Bloechel, and C. Parsons, “Area-Efficient Linear Regulator With Ultra-Fast Load Regulation,” IEEE J. of Solid-State Circuits, vol. 40, no. 4, pp. 933-940, Apr. 2005

Conclusion

• A Novel Low Noise Low Dropout Voltage Regulator have been proposed.

• A low 1/f noise linear regulator with fast transient response secondary current-feedback amplifier is presented. This is the first application of chopper stabilization and CFAs to linear regulators,enabling a 14㎶rms integrated output noise from 1kHz to 100kHz.

• Chopper Stabilized LDO with Current Mode Feedback Buffer Amplifier– Using Chopper Stabilization Technique

• Low Noise LDO has been achieved– Using PSR Subtraction Stage

• PSR has been improved– Using CFA

• Fast Transient Response LN-LDO has been achieved.

• As future work SD noise shaping techniques on the chopping clockcan be used to dither and spread 1/f noise further at higher frequencies.