20130130 d ll state machine
Post on 02-Jun-2018
219 Views
Preview:
TRANSCRIPT
-
8/11/2019 20130130 d Ll State Machine
1/51
A. Kluge
2013 01 31, 2013
-
8/11/2019 20130130 d Ll State Machine
2/51
Feb 5 & 6, 2013
DLL & state machine
A. Kluge 2
-
8/11/2019 20130130 d Ll State Machine
3/51
Feb 5 & 6, 2013
release mux
A. Kluge 3
Cursor-Baseline = -835.733451ns
Baseline = 32,873.443285ns
Cursor = 32,037.709834ns
clk_dllStateMachine
resetresetCap
earlyPD
earlySM
muxCtrl
release_mux
time_early_cnt 00 00 00
s 32,200ns 32,400ns 32,600ns 32,800ns
Baseline=32,873.443285ns
TimeA=32,037.709834ns
-
8/11/2019 20130130 d Ll State Machine
4/51
Feb 5 & 6, 2013
reset
A. Kluge 4
Cursor-Baseline = -396.185718ns
Baseline = 7323.500951ns
Cursor = 6927.315233ns
clk_dllStateMachine
reset
resetCap
release_mux
7000ns 7100ns 7200ns 7300ns
Baseline=7323.500951ns
TimeA=6927.315233ns
-
8/11/2019 20130130 d Ll State Machine
5/51
Feb 5 & 6, 2013
DLL state machine
Prevents incorrect startup behavior of DLL phase detector
After startup DLL control voltage is reset to maximum
value maximum speed
DLL phase detector might deliver wrongly too slow =
phase late = not earlyPD
DLL will decrease its frequency
Once frequency is low enough phase detector issues a
correct earlyPD = 1
A. Kluge 5
-
8/11/2019 20130130 d Ll State Machine
6/51
Feb 5 & 6, 2013
DLL state machine
When reset released DLL is kept in reset state by the state machine for 63
clk dll cycles = 197 ns (clk dll= 320 MHz) Charge pump control is taken from DLL and forced to discharge
DLL state machine waits for earlyPD = 1
verifies state is stable for 127 clock cycles.
In case earlyPD goes 0 again during that time, state machine resets the wait counter and waits for earlyPD to go 1 again.
Once 127 clock cycles have passed with earlyPD = 1 state machine releases the charge pump control to the DLL phase detector and
remains in this state until the next reset.
Test signals (force signals) can be asserted via the configuration interface.
If any force signal is used and then released state machine goes to releasemux state where the DLL is is not controlled by the state machine.
A. Kluge 6
-
8/11/2019 20130130 d Ll State Machine
7/51Feb 5 & 6, 2013
lock detector
A. Kluge 7
Cursor-Baseline = -6000.3ns
Baseline = 37,775.9ns
Cursor = 31,775.6ns
clk_dllStateMachine
resetresetCap
earlyPD
lock
lock_threshold
lost_lock_count
0A
0 1
32,000ns 34,000ns 36,000ns 38,000ns
Baseline=37,775.9ns
TimeA=31,775.6ns
-
8/11/2019 20130130 d Ll State Machine
8/51Feb 5 & 6, 2013
DLL lock detector a single bit indicating the present lock/unlocked status of the DLL
number of times the lock detector of change from locked status to unlocked status.
The lock detector is not triplicated.
Monitors the earlyPD signal
The lock state is defined as follows: A 01 transition has been detected,
the following 1 state is shorter than the period of lock threshold cycles (defined inconfiguration register)
the following 0 state is shorter than the period of lock threshold cycles.
locked state is lost
if lock threshold is exceeded
counter increased and can be read via the status register and is reset to 0 after each read.
A. Kluge 8
-
8/11/2019 20130130 d Ll State Machine
9/51Feb 5 & 6, 2013A. Kluge 9
-
8/11/2019 20130130 d Ll State Machine
10/51Feb 5 & 6, 2013
test-force signals
A. Kluge 10
-
8/11/2019 20130130 d Ll State Machine
11/51
Syn 2013 01 31
Pnr 2013 01 31
-
8/11/2019 20130130 d Ll State Machine
12/51Feb 5 & 6, 2013
Demonstrator: Known bugs
Test input force_dll_lock not operative
Problem identified
Test output of DLL not routed properly
Problem identified and corrected
12
-
8/11/2019 20130130 d Ll State Machine
13/51Feb 5 & 6, 2013
signoff
run backannotated simulation
clk_sync = 442 MHz
slowProc/typProc/fastProc :
20130131/ - /20130131
verify sdf.log file; check date and warning free:
20130131(many neg delay set to 0)/-/20120201
SEU maxf-fastProc:
SEU maxf-fastProc:20110815
-
8/11/2019 20130130 d Ll State Machine
14/51Feb 5 & 6, 2013
signoff
verify synthesis constraints, 20130131
sdc/constraints.sdc
verify timing libraries used for syn & pnr
20130131
init.tcl in syn/script
set ec::LIBRARY
"$IBM_PDK/ibm_cmos8rf/std_cell/rel$PDK_OPT/synopsys_1.2/slow_v110_t125/IBM_CMOS8RF_STD_SLOW_V110_T125.lib \
$IBM_PDK/ibm_cmos8rf/short_io/rel$PDK_OPT/synopsys/slow_v108_t125_pv162/IBM_CMOS8RF_BASE_SHORT_IO_SLOW_V108_T
125_PV162.lib "
oa.conf in pnr/script
set rda_Input(ui_timelib,max) { ./synopsys_std_cell_1.2/slow_v110_t125/IBM_CMOS8RF_STD_SLOW_V110_T125.lib \
./synopsys_short_io/slow_v108_t125_pv162/IBM_CMOS8RF_BASE_SHORT_IO_SLOW_V108_T125_PV162.lib }
set rda_Input(ui_timelib,min) { ./synopsys_std_cell_1.2/fast_v130_tm55/IBM_CMOS8RF_STD_V12_FAST_V130_TM55.lib \
./synopsys_short_io/fast_v132_tm40_pv363/IBM_CMOS8RF_BASE_SHORT_IO_FAST_V132_TM40_PV363.lib }
run synthesis, 20130131
-
8/11/2019 20130130 d Ll State Machine
15/51Feb 5 & 6, 2013
signoff
verify triplication survived syn & pnr: 20120201
verify latest rc.log for errors or not understood warning
20130131
run place and route
verify latest encounter.log for errors or not understood warnings 20130131
verify power distribution:
power report & rail_analysis: in ../report/powerReports/
qchip2010_view_max.rpt/qchip2010_view_min.rpt/qchip2010_view_typ.rpt, 20130131
rail_analysis in encounter.log file
20130131
-
8/11/2019 20130130 d Ll State Machine
16/51Feb 5 & 6, 2013
VDD static, 1 bottom left (20130131)
VDD d i
-
8/11/2019 20130130 d Ll State Machine
17/51Feb 5 & 6, 2013
VDD dynamic,1 bottom left conn (20130131)
-
8/11/2019 20130130 d Ll State Machine
18/51
Feb 5 & 6, 2013
static power report (20130131) < 2.1/ 2.2/2.3mW
mW for min/typ/max case
c
clk sync = 420 MHz
activity = 30 %
-
8/11/2019 20130130 d Ll State Machine
19/51
Feb 5 & 6, 2013
Timing (20130131)
Constraints:
clk_sync = 420 MHz
Sign off all hold met: 20130131
Max_cap: 0 errors
Fan out: config_ctrl_in 3 fanin
In2reg hold: slack 137ps , earlypd, estimated delay in constraint file
in2reg: slack 326 ps, reset
Reg2out hold: 168 slack, muxctrl
reg2out: violated 159 ps, but all signals not time critical
reg2reg 119 ps
in2out: na.
-
8/11/2019 20130130 d Ll State Machine
20/51
Feb 5 & 6, 2013
signoff-reg2out ->20130131
############################################################### # Generated by: Cadence Encounter 09.12-s159_1 # OS: Linux x86_64(Host ID lnxmics3) # Generated on: Thu Jan 31 10:16:18 2013 # Command: timeDesign -si -signoff -pathReports -drvReports -slackReports -numPaths 50 -prefix signoff -outDir ../report/timingReports ############################################################### Path 1: VIOLATED Late External Delay Assertion Endpoint: mbsel[2] (^) checked with leading edge of 'clk_dllStateMachine' Beginpoint: inst_config_dll_state_machine_and_lock_detector/inst_config_ register_rw/s_parallelRegTriple_reg_parallelReg_c_7/Q (^) triggered by leading edge of 'clk_dllStateMachine' Path Groups: {reg2out} Analysis View: view_max Other End Arrival Time 0.000 + Source Insertion Delay -0.030 - External Delay 1.000 + Phase Shift 2.380 = Required Time 1.350 - Arrival Time 1.509 = Slack Time -0.159 Clock Rise Edge 0.000 + Source Insertion Delay 0.030 = Beginpoint Arrival Time 0.030 +--------------------------------------------------------------------------------------------------------------------------+ | Instance | Arc | Cell | Slew | Delay | Arrival | Required | | | | | | | Time | Time | |----------------------------------------------------+-----------------------+--------+-------+-------+---------+----------| | | clk_dllStateMachine | | 0.000 | | 0.030 | -0.129 | | clk_dllStateMachine__L1_I0 | A ^ -> Z v | CLKI_Q | 0.082 | 0.178 | 0.208 | 0.049 | | clk_dllStateMachine__L2_I4 | A v -> Z ^ | CLKI_O | 0.108 | 0.188 | 0.396 | 0.237 | | inst_config_dll_state_machine_and_lock_detector/in | CLK ^ -> Q ^ | DFF_E | 0.114 | 0.318 | 0.714 | 0.555 | | st_config_register_rw/s_parallelRegTriple_reg_para | | | | | | | | llelReg_c_7 | | | | | | | | inst_config_dll_state_machine_and_lock_detector/in | B ^ -> COUT | ADDF_F | 1.322 | 0.769 | 1.483 | 1.324 | | st_config_register_rw/g2 | | | | | | | | | mbsel[2] | | 1.326 | 0.026 | 1.509 | 1.350 | +--------------------------------------------------------------------------------------------------------------------------+
-
8/11/2019 20130130 d Ll State Machine
21/51
Feb 5 & 6, 2013
signoff reg2reg hold (20130131)
###############################################################
# Generated by: Cadence Encounter 09.12-s159_1
# OS: Linux x86_64(Host ID lnxmics3)
# Generated on: Thu Jan 31 10:17:42 2013 # Command: timeDesign -si -signoff -hold -pathReports -slackReports -numPaths 50 -prefix signoff -outDir ../report/timingReports
###############################################################
Path 1: MET Hold Check with Pin inst_config_dll_state_machine_and_lock_detector/
inst_config_interface_receiver/s_ctrl_in_d3_reg_FF_b/CLK
Endpoint: inst_config_dll_state_machine_and_lock_detector/inst_config_
interface_receiver/s_ctrl_in_d3_reg_FF_b/D (^) checked with leading edge of
'clk_dllStateMachine'
Beginpoint: inst_config_dll_state_machine_and_lock_detector/inst_config_
interface_receiver/s_ctrl_in_d2_reg_FF_a/Q (^) triggered by leading edge of
'clk_dllStateMachine'
Path Groups: {reg2reg}
Analysis View: view_min Other End Arrival Time 0.185
+ Hold -0.014
+ Phase Shift 0.000
= Required Time 0.171
Arrival Time 0.249
Slack Time 0.078
Clock Rise Edge 0.000
+ Source Insertion Delay -0.030
= Beginpoint Arrival Time -0.030
Timing Path:
+--------------------------------------------------------------------------------------------------------------------------+
| Instance | Arc | Cell | Slew | Delay | Arrival | Required | | | | | | | Time | Time |
|----------------------------------------------------+-----------------------+--------+-------+-------+---------+----------|
| | clk_dllStateMachine | | 0.000 | | -0.030 | -0.108 |
| clk_dllStateMachine__L1_I0 | A ^ -> Z v | CLKI_Q | 0.029 | 0.072 | 0.043 | -0.035 |
| clk_dllStateMachine__L2_I10 | A v -> Z ^ | CLKI_O | 0.038 | 0.080 | 0.123 | 0.045 |
| inst_config_dll_state_machine_and_lock_detector/in | CLK ^ -> Q ^ | DFF_E | 0.038 | 0.126 | 0.249 | 0.171 |
| st_config_interface_receiver/s_ctrl_in_d2_reg_FF_a | | | | | | |
| inst_config_dll_state_machine_and_lock_detector/in | D ^ | DFF_E | 0.038 | 0.000 | 0.249 | 0.171 |
| st_config_interface_receiver/s_ctrl_in_d3_reg_FF_b | | | | | | |
+--------------------------------------------------------------------------------------------------------------------------+
Clock Rise Edge 0.000
+ Source Insertion Delay 0.030
= Beginpoint Arrival Time 0.030
Other End Path:
-
8/11/2019 20130130 d Ll State Machine
22/51
-
8/11/2019 20130130 d Ll State Machine
23/51
Feb 5 & 6, 2013
signoff summary setup (20130131)
###############################################################
###############################################################
# Generated by: Cadence Encounter 09.12-s159_1
# OS: Linux x86_64(Host ID lnxmics3)
# Generated on: Thu Jan 31 10:16:17 2013
# Command: timeDesign -si -signoff -pathReports -drvReports -slac...
###############################################################
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.159 | 0.119 | 0.326 | -0.159 | N/A | N/A | | TNS (ns):| -0.510 | 0.000 | 0.000 | -0.510 | N/A | N/A |
| Violating Paths:| 4 | 0 | 0 | 4 | N/A | N/A |
| All Paths:| 251 | 237 | 49 | 11 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) | | max_fanout | 1 (1) | -2 | 1 (1) |
+----------------+------------------+------------+------------------+
Density: 127.028%
Total number of glitch violations: 0
------------------------------------------------------------
--------------------------------------------
-
8/11/2019 20130130 d Ll State Machine
24/51
Feb 5 & 6, 2013
signoff summary hold 20130131
############################################################### # Generated by: Cadence Encounter 09.12-s159_1
# OS: Linux x86_64(Host ID lnxmics3) # Generated on: Thu Jan 31 10:17:42 2013 # Command: timeDesign -si -signoff -hold -pathReports -slackRepor... ###############################################################
------------------------------------------------------------ timeDesign Summary ------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+ | Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate | +--------------------+---------+---------+---------+---------+---------+---------+ | WNS (ns):| 0.078 | 0.078 | 0.137 | 0.168 | N/A | N/A | | TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A | | Violating Paths:| 0 | 0 | 0 | 0 | N/A | N/A | | All Paths:| 251 | 237 | 49 | 11 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
Density: 127.028% Total number of glitch violations: 0 ------------------------------------------------------------
i ff
-
8/11/2019 20130130 d Ll State Machine
25/51
Feb 5 & 6, 2013
signoff
Assura DRC: 20130131
Calibre DRC:20130131
Assura LVS: 20130131
Calibre LVS: 20130131
lib fil ( )
-
8/11/2019 20130130 d Ll State Machine
26/51
Feb 5 & 6, 2013
.lib files (x)
several .lib files have been created
only those are reasonable which are created whenencounter is closed and restarted and createLibModels.tclusing saveModel is started.
sdf files and lib files have been compared for one signal:see next to pages
results seem coherent
A. Kluge 26
D i fl
-
8/11/2019 20130130 d Ll State Machine
27/51
Feb 5 & 6, 2013
Design flow notes
-
8/11/2019 20130130 d Ll State Machine
28/51
Feb 5 & 6, 2013
i l i f
-
8/11/2019 20130130 d Ll State Machine
29/51
Feb 5 & 6, 2013
serial interfaceread & write procedure
-
8/11/2019 20130130 d Ll State Machine
30/51
Feb 5 & 6, 2013
-
8/11/2019 20130130 d Ll State Machine
31/51
Feb 5 & 6, 2013
-
8/11/2019 20130130 d Ll State Machine
32/51
Feb 5 & 6, 2013
i l d t t
-
8/11/2019 20130130 d Ll State Machine
33/51
Feb 5 & 6, 2013
serial_reg_read status
uses Gianluca configRegisterRO
has a reset output to reset registers after being read.
-
8/11/2019 20130130 d Ll State Machine
34/51
Feb 5 & 6, 2013
w
-
8/11/2019 20130130 d Ll State Machine
35/51
Feb 5 & 6, 2013
_ _ _w _ _config
triplicated
uses Gianluces configRegisterRW but has been modified to
output also the non triplicated data for use in the qchiphere the triplicated data output is used
-
8/11/2019 20130130 d Ll State Machine
36/51
Feb 5 & 6, 2013
SEU i l ti
-
8/11/2019 20130130 d Ll State Machine
37/51
Feb 5 & 6, 2013
SEU simulation
DFF t
-
8/11/2019 20130130 d Ll State Machine
38/51
Feb 5 & 6, 2013
DFF_meta.v
in ./digital/source/DFF_meta.v
`define meta_duration 2500 defines length of metastbaility//`define random 1, to be commented/uncommented whenmetastability should give random value after metastability orold value for setup, new value for hold violation
sim lation
-
8/11/2019 20130130 d Ll State Machine
39/51
Feb 5 & 6, 2013
simulation
behavioral & functional
almost identical (with exception of verification of internalsignals)
automated
scans the phase between the clk_dll and the serial signals for
0 to clk_dll_period in 30 steps to verify correctsynchronisation between clock domains
meta stable flip flop used
SEU simulation on functional
write & readback care taken not to read back serial regwithout actual read command
-
8/11/2019 20130130 d Ll State Machine
40/51
Feb 5 & 6, 2013
scripts for synth, place and route
power up to M5 conform with Gianluca
size ~225x 242 um2
DRC & LVS run on virtuoso
1.8
max frequency 442 MHz: sdf backannotated max delay
min frequency 200 MHz: sdf backannotated min delay
code coverage (2012)
-
8/11/2019 20130130 d Ll State Machine
41/51
Feb 5 & 6, 2013
code coverage (2012)
notes on design flow
-
8/11/2019 20130130 d Ll State Machine
42/51
Feb 5 & 6, 2013
notes on design flow cp /homedir/bert/SysAdm/KITdistribution/m* .
./mklib name of digital block
will create directory structure from design_1 as in script on page 22. following info is available for the script: ------------------------------------------------------ -- mklib -- by S. Bonacini and B. Van Koningsveld ------------------------------------------------------ Add in verilog the VDD,GND and IO pads. What to do now: - Copy your verilog files in ./digital/hitArbiter/syn/verilog [default name: hitArbiter.v] - Edit ./digital/hitArbiter/syn/scripts/init.tcl setting the variables: CORE_CHIP, VERILOG_LIST, DFT - Edit ./digital/hitArbiter/pnr/scripts/variables.tcl setting the variable: CORE_CHIP [default: CORE] - A default sdc file is provided in ./digital/hitArbiter/syn/sdc/constraint.sdc [please set at least the clock
signal] - DFT [scan chain] port options are in ./digital/hitArbiter/syn/scripts/dft.tcl [default: off] run synthesis in ./digital/hitArbiter/syn/work by launching ./run_rc In case source is VHDL modify init.tcl: remove files name from set ec::VERILOG_List and add to VHDL list set _attribute hdl_language to vhdl change read_hdl $ec::VHDL_LIST modify import.tdl and change the floorplan values
run encounter until floorplan and do design/save/io and save template IO file to be modified uncomment ioadIOfile ...save.io - run PnR in ./digital/hitArbiter/pnr/work by launching encounter -replay ../scripts/all.tcl
or copy from me
/projects/IBM_CMOS8/gtk2010/V2.0/workAreas/akluge
h lib i t V
-
8/11/2019 20130130 d Ll State Machine
43/51
Feb 5 & 6, 2013
change libraries to 1.2V change timing libraries to 1.2 V
in: /projects/IBM_CMOS8/gtk2010/V4.0/workAreas/akluge/digital/hitArbiterAndController2010a/pnr/work ln -s /vlsicad/micsoft/IBM_CMOS8_V1.8_DM_vcad/ibm_cmos8rf/std_cell/relDM/synopsys_1.2/ synopsys_std_cell_1.2
change oa.conf in pnr/script # original timing files #set rda_Input(ui_tim elib,max) { ./syno psys_std_ce ll/slow_v 140_t125/IBM_CMOS 8RF_CMOS8RF_S C_SLOW_V140_T12 5.lib \ #
./synopsys_short_io/slow_v135_t125_pv162/IBM_CMOS8RF_BASE_SHORT_IO_SLOW_V135_T125_PV162.lib }
#
#set rda_Input(ui_tim elib,min) { ./syno psys_std_ce ll/fast_v1 60_tm55/IBM_CMOS8RF _CMOS8RF_SC_FAS T_V160_TM55.lib \ #
./synopsys_short_io/fast_v165_tm40_pv363/IBM_CMOS8RF_BASE_SHORT_IO_FAST_V165_TM40_PV363.lib } # end original timing files
# 1.2 V timing files set rda_Input(ui_timelib,max) { ./synopsys_std_cell_1.2/slow_v110_t125/IBM_CMOS8RF_STD_SLOW_V110_T125.lib \
./synopsys_short_io/slow_v108_t125_pv162/IBM_CMOS8RF_BASE_SHORT_IO_SLOW_V108_T125_PV162.lib }
set rda_Input(ui_ti melib,min) { ./syno psys_std_ce ll_1.2/fa st_v130_tm55/IBM_CMOS8 RF_STD_V12_FAS T_V130_TM55.lib \
./synopsys_short_io/fast_v132_tm40_pv363/IBM_CMOS8RF_BASE_SHORT_IO_FAST_V132_TM40_PV363.lib }
# end 1.2 V timing files
from 1.8 on change also mmc.view #original files #create_library_set -name libs_max -timing {./synopsys_std_cell/slow_v140_t125/IBM_CMOS8RF_CMOS8RF_SC_SLOW_V140_T125.lib
./synopsys_short_io/slow_v135_t125_pv162/IBM_CMOS8RF_BASE_SHORT_IO_SLOW_V135_T125_PV162.lib } -si {std_cell_ss_1.4v_125c.cdb} #create_library_set -name libs_typ -timing {./synopsys_std_cell/typ_v150_t25/IBM_CMOS8RF_CMOS8RF_SC_TYP_V150_T25.lib
./synopsys_short_io/typ_v150_t25_pv250/IBM_CMOS8RF_BASE_SHORT_IO_TYP_V150_T25_PV250.lib } #create_library_set -name libs_min -timing {./synopsys_std_cell/fast_v160_tm55/IBM_CMOS8RF_CMOS8RF_SC_FAST_V160_TM55.lib
./synopsys_short_io/fast_v165_tm40_pv363/IBM_CMOS8RF_BASE_SHORT_IO_FAST_V165_TM40_PV363.lib } -si {std_cell_ff_1.6v_m40c.cdb} #end original files #changed for 1.2V operation create_library_set -name libs_max -timing {./synopsys_std_cell_1.2/slow_v110_t125/IBM_CMOS8RF_STD_SLOW_V110_T125.lib
./synopsys_short_io/slow_v108_t125_pv162/IBM_CMOS8RF_BASE_SHORT_IO_SLOW_V108_T125_PV162.lib } -si {std_cell_ss_1.4v_125c.cdb}
create_library_set -name libs_typ -timing {./synopsys_std_cell_1.2/typ_v120_t25/IBM_CMOS8RF_STD_TYP_V120_T25.lib./synopsys_short_io/typ_v120_t25_pv250/IBM_CMOS8RF_BASE_SHORT_IO_TYP_V120_T25_PV250.lib}
create_library_set -name libs_min -timing {./synopsys_std_cell_1.2/fast_v130_tm55/IBM_CMOS8RF_STD_V12_FAST_V130_TM55.lib
./synopsys_short_io/fast_v132_tm40_pv363/IBM_CMOS8RF_BASE_SHORT_IO_FAST_V132_TM40_PV363.lib } -si {std_cell_ff_1.6v_m40c.cdb} # end changed for 1.2V operation in mmmc.view and oa.conf link to std_cell_ff_1.6Vxxx.cdb files should be changed to 1.2V but does not exist.
change init.tcl in syn/script # original settings #set ec::LIBRARY "$IBM_PDK/ibm_cmos8rf/std_cell/rel$PDK_OPT/synopsys/slow_v140_t125/IBM_CMOS8RF_CMOS8RF_SC_SLOW_V140_T125.lib \ #
$IBM_PDK/ibm_cmos8rf/short_io/rel$PDK_OPT/synopsys/slow_v135_t125_pv162/IBM_CMOS8RF_BASE_SHORT_IO_SLOW_V135_T125_PV162.lib "
# #end original setting #1.2 V libraries set ec::LIBRARY "$IBM_PDK/ibm_cmos8rf/std_cell/rel$PDK_OPT/synopsys_1.2/slow_v110_t125/IBM_CMOS8RF_STD_SLOW_V110_T125.lib \
$IBM_PDK/ibm_cmos8rf/short_io/rel$PDK_OPT/synopsys/slow_v108_t125_pv162/IBM_CMOS8RF_BASE_SHORT_IO_SLOW_V108_T125_PV162.lib "
#end 1.2V libraries
workflow simulations
-
8/11/2019 20130130 d Ll State Machine
44/51
Feb 5 & 6, 2013
workflow simulations
in akluge/. run
hdlCompileDllStateMachine2010Behavioral.script
or hdlCompileDllStateMachine2010Functional.script
must be started in a gp window, otherwise ncsim will notstart
work flow
-
8/11/2019 20130130 d Ll State Machine
45/51
Feb 5 & 6, 2013
work flow
run gp select gtk2010 version 1.8 / version 4 or gpak
run all procedures on the new window
top module is called/projects/IBM_CMOS8/gtk2010/V3.0/workAreas/akluge/digital/source/dll_state_machine_and_lock_detector2010.vhd
dll_state_machine_and_lock_detector2010 syn
constraints file is in syn/sdc and need verification for earlyPD and clk_dll *(20120404)
output is in syn/output/r2g.v
work low
-
8/11/2019 20130130 d Ll State Machine
46/51
Feb 5 & 6, 2013
work lowdll_state_machine_and_lock_detector2010
synthesize dll_state_machine_and_lock_detector2010
digital//dllStateMachine2010/syn/work run ./run_rc
in digital/dllStateMachine2010/pnr/work
run velocity replay ../scripts/all.tcl
simulation with backannotation
verilog output from pnr is dfm.v dllStateMachine2010/pnr/output/dfm.v
/projects/IBM_CMOS8/gtk2010/V3.0/workAreas/akluge/hdlCompileDllStateMachine2010Functional.script compiles all required files and starts simulations
in test_dll_state_machine2010_stimulus.vhd variables modify log behavior and sim behaviorconstant displayMessages :boolean := true;
constant logMessage :boolean := true;constant number_of_phase_runs : integer := 20;
in ./digital/source/DFF_meta.v`define meta_duration 2500 defines length of metastbaility
//`define random 1, to be commented/uncommented when metastability should give random value after metastability or old value for setup, new value for hold violation
./seuFunctional_meta.tcl loads SEU into design
This must be stared manually -> reset simulation if simulation time is not 0, then source seuFunctional_meta.tcl
sdf command files defines min/max, reelaboration required if changed/projects/IBM_CMOS8/gtk2010/V4.0/workAreas/akluge/digital/sdf_backannotate_dll_state_machine2010/sdf.cmd
/projects/IBM_CMOS8/gtk2010/V4.0/workAreas/akluge/digital/sdf_backannotate_dll_state_machine2010/ contains backannotations scripts: check that they are error/warning free;
elaborated with option coverage to receive coverage report
work flow virtuoso
-
8/11/2019 20130130 d Ll State Machine
47/51
Feb 5 & 6, 2013
work flow virtuoso open (dfm) layout and convert to layout
Launch > layout L
( not needed anymorefrom layout view: tools > remaster Instances
search for view name abstract and update to view name layout
save as different view from dfm)
Assura DRC
IBM_PDK > checking > Assura > DRC
rundirectory ./DRC (assura_drc_dll_state_machine) rules file:
/vlsicad/micsoft/IBM_CMOS8_V1.7_DM_vcad/IBM_PDK/cmrf8sf/V1.8xxDM/Assura/DRC/drc.rul (echo $techdir)
options: GridCheck BEOL_STACK_323 CELL
OK
Assura density antenna checks Assura run DRC
run directory ./ANT (./assura_ant_drc_dll_state_machine)
change technology field co cmos8sfTech
is greyed out and thus not possible ?[check Rule Set field to antenna]
click switch ames button and set the BEOL_STACK_323 ALL_CHECKS options
work flow virtuoso
-
8/11/2019 20130130 d Ll State Machine
48/51
Feb 5 & 6, 2013
work flow virtuoso
IBM_PDK Checking Calibre DRC menu
BEL_STACK:3_2_3, density local: off, design_type: celllast metal:MA, nummetal:8 OK
Rules Tab:
/vlsicad/micsoft/IBM_CMOS8_V1.8_DM_vcad/IBM_PDK/cmrf8sf/relDM/Calibre/DRC/cmrf8sf.drc.cal
run directory: (calibre_drc_dll_state_machine)
Input tab: new directory OK
Output tab:
RunDRC:
Look at summary file
workflow LVS
-
8/11/2019 20130130 d Ll State Machine
49/51
Feb 5 & 6, 2013
workflow LVS assura runLVS
set rundirectory field to ./LVS (assura_lvs_dll_state_machine)
change technology field to cmos8sfTech
set switches NO_SUBC_IN_GRLOGIC SBAR_feature
ruleset field to default
click OK
click watch logFile
after run click YES
From LVS debug click on the Nets/Devices to peon Nets mismatch tool or devices mismatch tool
click view LVS Error Report
Go to LVS dir and check different files (.err, .cls, .sum)
Calibre LVS
-
8/11/2019 20130130 d Ll State Machine
50/51
Feb 5 & 6, 2013
Calibre LVS
IBM_PDK Checking Calibre LVS Menu
Default Runset (never appeared)
BEOL_STACK:3_2_3, cell, lastMetal: MA, #layers =8,No_subc_in_grlogic = true, use_resistance_multipliers:
true Rules tab:
/vlsicad/micsoft/IBM_CMOS8_V1.7_DM_vcad/IBM_PDK/cmrf8sf/relDM/Calibre/DRC/cmrf8sf.drc.cal
Set DRCrundirectory (calibre_lvs_dll_state_machine)
click inputs tab
Run LVS
in rundirectory check files
notes
-
8/11/2019 20130130 d Ll State Machine
51/51
notes
top related