analog cmos design 09(2)

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1 April 16-17, 2009 Etienne SICARD etienne.sicard@insa- toulouse.fr www.etienne-sicard.fr INSA Toulouse, FRANCE Analog CMOS Design Analog CMOS Design

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cmos design presentation

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Page 1: Analog Cmos Design 09(2)

1

April 16-17, 2009

Etienne SICARD [email protected]

www.etienne-sicard.fr

INSA Toulouse, FRANCE

Analog CMOS Design Analog CMOS Design

Page 2: Analog Cmos Design 09(2)

2

AGENDA

First day : 9h - 12h: Mos Implementation - Inverter

Second Day: 14h - 17h: Basic Cell Design

Second day: 9h - 12h: Mini-project 1/2

Second Day: 14h - 16h: Mini-project 2/2 – Mini presentation

OBJECTIVES

At the end of the course, the auditor will be able to design and simulate

basic analog cells and understand the link between design parameters and

electrical performances.

PRE REQUISITES

Basic knowledge in CMOS technology, electrical circuits and MOS models.

Outlines

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• All notions may be illustrated with Microwind

Microwind is a friendly and free PC tool for designing and simulating microelectronic circuits at layout level.

http://www.microwind.org

Microwind

Version used in 2009: version 3.5 “beta”

Temporary installation permitted

Copying or diffusion prohibited

Lite version free for download at www.microwind.net

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• http://www.etienne-sicard.fr/cours/cmos • Logiciel de conception de circuits micro-électronique • Unzip in “My Documents/Temp”• Open “/system”, double click “Microwind35.exe”• Documentation : click “Livre CMOS de base” ch2 – pp21

Getting Started

Page 5: Analog Cmos Design 09(2)

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Microwind Main Screen

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Most important icons

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1. MOS Implementation

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Problem 1

• Draw a n-channel MOS

• See the MOS in 2D

• Measure Ion, Ioff

• Simulate the switch (ch2 – pp 21)

• Summarize the n-channel behavior

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Draw a n-channel MOS

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2D section of a n-channel MOS

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Source (Si)

Polysilicon gate

Gate oxide

Horizontal strain created by the silicon nitride capping layer

Drain (Si)

Drain (Si) Source

(Si)

Tensile Strain

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Ion, Ioff

Page 13: Analog Cmos Design 09(2)

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Ion, Ioff

Page 14: Analog Cmos Design 09(2)

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Transient Simulation

Page 15: Analog Cmos Design 09(2)

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Transient Simulation

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N-channel MOS summary

Page 17: Analog Cmos Design 09(2)

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Draw a p-channel MOS

Page 18: Analog Cmos Design 09(2)

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2D section of a p-channel MOS

Page 19: Analog Cmos Design 09(2)

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Compressive Strain

SiGe Si Si SiGe

Gate

Gate oxide

Horizontal pressure created by the uniaxial SiGe strain

Page 20: Analog Cmos Design 09(2)

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Ion, Ioff

Page 21: Analog Cmos Design 09(2)

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Ion, Ioff

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Transient Simulation

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P-channel MOS Summary

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Problem 2

• Design a Transmission Gate

• Draw a n-channel + p-channel MOS

• Add “Enable control”

• Simulate the analog switch

• Determine the cut-off frequency

Page 25: Analog Cmos Design 09(2)

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Interconnect n-diff and p-diff

Page 26: Analog Cmos Design 09(2)

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Transmission Gate

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Problem 3 – correct design

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Problem 3 – correct design

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Problem 4

• Design a MOS device suitable for Bluetooth output stage

• What ????

Page 30: Analog Cmos Design 09(2)

2. Inverter

Page 31: Analog Cmos Design 09(2)

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Problem 5

• Draw an Inverter (ch4 – pp 3)– Tune the design for symmetrical V/V curve– Delay performances when connected to 1,2, 3

inverters (fanout)

• Draw 3 inverters (ch4 – pp 35)– Try to have the fastest free oscillator

Page 32: Analog Cmos Design 09(2)

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V/V Static Curve

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Delay vs. Fanout

Delay

Fanout

0 1 2 3

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3. Basic analog cells

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Problem 6 – What is this ?

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Problem 7 – Draw a 10 K resistor

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Problem 8 – Generate a 0.6 V reference, 1µA max

• Use two diode-connected MOS

• Verify DC consumption by – “Voltages and

Currents”– I in log

Page 38: Analog Cmos Design 09(2)

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Problem 9 – From 1µA, generate 100µA

• Use the current mirror principle

• I(M2) = I(M1) if size identical

• For which Vout range do we have 100µA +/- 10% ?

Vout

Page 39: Analog Cmos Design 09(2)

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Problem 10 – Amplify with a gain of 10

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Problem 10 – Amplify with a gain of 10

Vout

Vin

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Problem 11 – OpAmp to compare two analog values

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4. Mini-Projects

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5V

0V

1.25V

2.5V

3.75V

Vin

A1

A0

C1

C0

C2

+

+

+

-

-

-Poly resistor

Amplifer used as comparator

Coding Logic

Analog - Digital Converters

5V

2.5V

3.125V

3.75V

4.375V

A0

0.625V

1.25V

1.875V

0V

nA0A1 nA1

Vout

A2 nA2

0

0

1

• 3-bit ?• R/2R ?• C/2C ?• Other type?

Page 44: Analog Cmos Design 09(2)

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Static Memory

• 4 x 4 ?• 8 x 8 ?• Emulate 256 x 256 ?• Split in 3 sub-projects?

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Other ideas

• Amplifier with programmable gain• Rail-to-rail amplifier• 1.9 GHz amplifier 1 Watt• 2.45 GHz amplifier with sub-sampling to 100 MHz• Phase Lock Loop

– Frequency multiplier

– FM receiver

Page 46: Analog Cmos Design 09(2)

Thank you for your attentionThank you for your attention