chapter1_integrated-circuit logic family
TRANSCRIPT
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BKTP.HCM
2010
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Chapter 1INTERGRATED-CIRCUIT
LOGIC FAMILIES
Faculty of Computer Science and Engineering
Department of Computer Engineering
©2010, CE Department
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Outline
• Digital IC Terminology• TTL Logic Family
• MOS Technology• Open-Collector/Open-Drain Ouputs
• Tristate (Three-State) Logic Outputs
• IC Interfacing
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Digital IC Terminology
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Current and Voltage Parameters
HIGH logic:1 ; LOW logic :0 V IH(min) – High Level Input Voltage
V IL(max) – Low Level Input Voltage V OH(min) – High Level Output Voltage
V OL(max) – Low Level Output Voltage
I IH – High Level Input Current
I IL – Low Level Input Current
I OH – High Level Output Current
I OL – Low Level Output Current
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Fan-out
• Loading factor
• The maximum number of logic inputs that an
oputput can drive reliably.
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Propagation Delays
t PLH: Delay time in going from 0 Æ 1 (LOWÆ HIGH)
t PHL: Delay time in going from 1 Æ 0 (HIGHÆ LOW)
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Power Requirement
• TTL devices: VCC
• MOS devices: VDD
• I CCH : all outputs are HIGH• I CCL: all outputs are LOW
I CC (avg)=( I CCH + I CCL)/2
P D(avg)= I cc(avg).V cc
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Speed-Power Product
• Digital IC families desire: – Higher speed (shorter gate propagation delay) : S
– Lower power dissipation: P – Measuring and comparing the overall performance of
an IC.
Speed-power product = S * P
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Noise Immunity
– high-state noise marginV NH
= V OH
(min) – V IH
(min)
– low-state noise margin
V NL = V IL (max) – V OL(max)
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Current-Sourcing – Current-Sinking Logic
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IC Packages
• DIP (dual-in-line package) – Lead pitch: spacing between pins (100 mils)
• Surface-mount
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TTL Logic Family
• TTL inputs: multiple-emitter
• TTL outputs: totem-pole
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TTL NAND Gate
• HIGH State
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TTL NAND Gate
• Current-Sinking and Current Sourcing
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TTL NAND Gate
• Totem-Pole Output – Advantage
• Low power dissipation
• Fast rise-time
– Disadvantage
• Large current spike during switching form LOW to HIGH
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TTL Series
• Standard TTL, 74• Schottky TTL, 74S
• Low-Power Schottky TTL, 74LS (LS-TTL)• Advanced Schottky TTL, 74AS (AS-TTL)
• Advanced Low-Power Schottky TTL, 74ALS• 74F-Fast TTL
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TTL D Sh
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TTL Data Sheets
• Supply Voltage – Temperature Range• Voltage Levels
– VIL, VOL, VOH, VIHÆ
VNL, VNH
• Maximum Voltage Ratings
• Power Dissipation
– ICCH, ICCLÆ ICC(avg)Æ PD(avg)
• Propagation Delays
– tPLH, tPHLÆ tpd(avg)
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TTL D Sh
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TTL Data Sheets
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TTL D t Sh t
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TTL Data Sheets
• Loading and Fan-out
fan-out(LOW)
fan-out(HIGH)
• Example: In datasheet of 74ALS00
– I OL(max) = 8 mA, I IL(max) = 0.1 mA– I OH(max) = 0.4 mA = 400 μA, I OL = 20 μA
Æ fan-out(LOW) = 80, fan-out(HIGH) = 20
(max)
(max)
IL
OL
I
I =
(max)
(max)
IH
OH
I
I =
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TTL D t Sh t
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TTL Data Sheets
• Loading and Fan-out
IOL = Σ IIL IOH = Σ IIH
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Oth TTL Ch t i ti
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Other TTL Characteristics
• Unconnected Inputs (Floating) – Open input acts exactly like a logical 1 (HIGH)
• Unused Inputs – Left disconnected (undesirable – antenna)
– Connect to VCC
(+5V) through a 1-kΩ resistor or toGND to produce for a constant-output logic level
– Tied to a used input
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Oth TTL Ch t i ti
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Other TTL Characteristics
• Tied-Together Inputs – Represent a load – Sum of the load current rating
– NAND, AND gates: LOW-state input load – singleinput
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Other TTL Characteristics
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Other TTL Characteristics
• Biasing TTL Inputs Low
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Other TTL Characteristics
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Other TTL Characteristics
• Current Transients – high-amplitude current spike occurs when a totem-
pole TTL output goes from LOW to HIGH
– Power-supply decoupling: capacitors connect from
VCC to GND (0.01 μF or 0.1 μF)
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MOSFET
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MOSFET
• Metal-oxide-semiconductor field-effect transistor.• Advantage
– Simple, inexpensive to fabricate – Small, little power consumption
– Suited for complex ICs
– Faster than 74, 74LS, 74ALS TTL Series
• Disadvantage
– susceptibility to static-electricity damage
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Enhancement MOSFET
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Enhancement MOSFET
• Use in digital ICs
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Basic MOSFET Switch
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Basic MOSFET Switch
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Digital MOSFET Circuit
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Digital MOSFET Circuit
• N-MOS or P-MOS – Use MOSFET as a switch
– Implement all resistors using channel resistance of aMOSFET
– Simple circuits and fabrication processes
• C-MOS (complementary MOS) – Use both P- and N-channel MOSFET
– Increase complexity of IC fabrication process, lower
packing density
Æ Faster and less power consumption
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N MOS Inverter
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N-MOS Inverter
• Gate of Q1 connected to
the drainÆ always ONÆ pull-up resistor 100 kΩ
Pull-upresistor
Switchon/off
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Complementary MOS Logic
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Complementary MOS Logic
• CMOS Inverter
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Complementary MOS Logic
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Complementary MOS Logic
• CMOS NAND Gate
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Complementary MOS Logic
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Complementary MOS Logic
• CMOS NOR Gate
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CMOS Series
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CMOS Series
• 4000/14000 Series• 74C Series
• 74HC/HCT (High-Speed CMOS )• 74AC/ACT ( Advanced CMOS )
• 74AHC/74AHCT ( Advanced High-Speed CMOS )
• BICMOS 5-Volt Logic
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Low-Voltage Technology
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Low Voltage Technology
• CMOS Family – 74LVC ( Low-Voltage CMOS )
– 74ALVC ( Advanced Low-Voltage CMOS )
– 74LV ( Low-Voltage)
– 74AVC ( Advanced Very-Low-Voltage CMOS )
• BiCMOS Family – 74LVT ( Low-Voltage BiCMOS Technology)
– 74LVT ( Advanced Low-Voltage BiCMOS Technology)
– 74ALB ( Advanced Low-Voltage BiCMOS )
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CMOS Characteristics (1)
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CMOS Characteristics (1)
• Power-Supply Voltage• Logic Voltage Levels
– Not sink/source any significant amount of current
– V OL: close to 0 V, V OH: close to VDD
• Noise Margins: greater than TTL
– V NH = V OH(min) – V IH(min)
– V NL = V IL (max) – V OL(max)
• Power Dissipation – Extremely low Æ Suitable for applications using
battery power
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CMOS Characteristics (2)
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CMOS Characteristics (2)
• P D increases with Frequency – Increase in proportion to the frequency at switching
states of the circuit (LOW to HIGH)
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CMOS Characteristics (3)
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CMOS Characteristics (3)
• Fan-Out: depend on – Permissible maximum propagation delay
– Frequency
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CMOS Characteristics (4)
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CMOS Characteristics (4)
• Switching Speed – Faster than N-MOS and P-MOS (low output resistance
– 1 kΩ vs. 100 kΩ)
• Unused Inputs
– Never left disconnected : susceptible to noise and
static charges – Tie to fixed voltage level (0V or V DD) or to another input
• Static Sentivity
• Latch-Up
– Transistors stay ON permanently
– Solution: Clamping diodes
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Output Combination (sharing a common wire)
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Output Co b at o ( g )
• Conventional CMOS outputs, TTL totem poleoutputs should never be tied together
– Output voltage: in the indeterminate range
– Damage the ICs
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Open-Collector/Open-Drain Outputs
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p p p
• Solution: remove the active pull-up transistor – CMOS output circuits: open-drain ouputs
– TTL totem pole output circuit: open-collector ouputs
– Output LOW state: no problem
– Output HIGH state: external pull-up resistor R p
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Open-collector/drain outputs Application
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p p pp
Wired-ANDconnection
Open-collector/drainBuffer/Driver
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Tristate (Three-State) Logic Ouputs
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( ) g p
• Allow three possible output states: – HIGH, LOW
– High-impedance (Hi-Z): both pull-up and pull-down
transistors are turned OFF
• Have an enable input (OE – output enable)
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Tristate (Three-State) Logic Ouputs
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( ) g p
• Advantage – Tristate ICs output can be connected together
– Low-impedance, high-speed characteristic
• Application: Tristate Buffers
Bus contention
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CMOS Transmission Gate (Bilateral Switch)
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( )
• Pass signals in both directions• Digital and analog applications
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IC Interfacing
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• Connecting the output(s) to the input(s) ofdifferent electrical charateristic systems.
• Take advange of the strong points of each IC
family – High-speed, greater output current/voltage capability,
high frequency
• Concerned problems
– Fan-out
– Voltage and current parameters
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TTL Driving CMOS
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• Current: no problem• Output votages
– V OH(min) of TTL: too low when compared with V IH(min)
of CMOS
– Solution: Pull-up resistor at TTL output
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TTL Driving CMOS
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• Driving High-Voltage CMOS – Use TTL series from certain manufacturers that can
operate with an high-voltage output pull-up
– Utilize a voltage level-translator
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CMOS Driving TTL
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• Driving TTL in the HIGH State: no problem• Driving TTL in the LOW State:
– Excepting 4000B series, 74HC/74HCT series have no
trouble driving a single TTL load of any series
– Concern fan-out problem
– Use buffer to interface low-current CMOS to high-current TTL
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CMOS Driving TTL
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• High-Voltage CMOS Driving TTL – Use TTL series that can withstand high-voltage input
– Use voltage level-translator
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Reference