d-wave systemsfuture hardware directions of quantum annealing 1cm qubits europe 2018 d-wave users...

Future Hardware Directions of Quantum Annealing

Qubits Europe 2018D-Wave Users ConferenceMunich

Mark W JohnsonD-Wave Systems Inc.

April 11, 2018

Copyright © D-Wave Systems Inc.

Overview

I Where are we today?I annealing optionsI reverse annealingI quantum materials simulation

I Where are we going?I next generation processor - improved connectivityI lower noise

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Overview



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The goal of quantum annealing (QA): model the Hamiltonian

HS(s) = −12A(s) ∑

iσx,i + B(s)

[−∑

ihiσz,i + ∑

i<jJijσz,iσz,j

]

Φ 2

Φ 1

Josephsonjunction

a

"spin-down" circulating current

"spin-up" circulating currentΦ1X

Φ2X

0 0.2 0.4 0.6 0.8 10

2

4

6

8

10

12

s

A/h(G

Hz)

B/h(G

Hz)

Energ

y (

GH

z)

I T. Kadowaki and H. Nishimori, PRE, 58(5), pp.5355-5363, (1998)

I E. Farhi, et al., Science 292, 472 (2001)I W. Kaminsky, S. Lloyd, T. Orlando,

arXiv:quant-ph/0403090, “ScalableSuperconducting Architecture for AdiabaticQuantum Computation”

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D-Wave 2000Q quantum annealing processorQuantum processing unit = QPU

128,472 Josephson junctions18,305 composite �ux DACs10,960 QFP shift register stages

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2000 qubits: Chimera architecture at C16 scale

D-Wave Two D-Wave 2X 2000QQubits (max) 512 1,152 2,048Couplers 1472 3360 6016Target Qubit Yield 95%+ 95%+ 97%+Qubit degree Chimera, degree = 6

New features: Supporting more control over annealing:

I Anneal O�setsGive user per-qubit control over transverse �eld

I Anneal PauseSpecify start and duration of global pause in anneal

I Anneal QuenchSpecify when to abruptly quench transverse �eld

I Reverse Anneal: a new quantum algorithm5 / 25


Standard annealing trajectory

HS(s) = −A(s)

2 ∑i

σx,i +B(s)

2

[−∑

ihiσz,i + ∑

i<jJijσz,iσz,j

]

0 0.2 0.4 0.6 0.8 10

2

4

6

8

10

12

s

A/h(G

Hz)

B/h(G

Hz)

Energ

y (

GH

z)

or

I ratio A(s)B(s) a �xed function of s

for given qubit design

I trajectory: choose s(t) linear

I ⇒ quadratic growth in B(s)

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Modi�cations to the QA path: What is possible?

0 0.2 0.4 0.6 0.8 10

2

4

6

8

10

12

s

Ene

rgy

(GH

z)A(s) dashed, B(s) solid

I Added control:a per qubit o�set

I advance or delay individualqubit schedule

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Application: Factoring

Percentage of solvedinstances

product standard delay longsize (bits) anneal chains

6 100% 100%8 55% 100%10 2% 98%

“Boosting integer factorization performance via quantum annealing o�sets”, E. Andriyash, et al., 2016see “D-Wave White Papers” at http://www.dwavesys.com/resources/publications

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0 20 40 60 80 100 1200

2

4

6

time (µs)

standard 20 µs annealing pattern

B(t)(G

Hz)

0 20 40 60 80 100 120 1400

2

4

6

time (µs)

20 µs anneal with 100 µs pause at s = 0.5

B(t)(G

Hz)

Manipulate global schedule:pause mid-anneal

Why? What good does this do?I Useful for study of instances with

purturbative crossings

I indentify regions during anneal wheredynamics occur

I probe of global freeze-out, localization

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0 0.2 0.4 0.6 0.8 10

2

4

6

8

10

12

s

Ener

gy (G

Hz)

A(s) dashed, B(s) solid

QUENCH! abruptly terminate the anneal

What good does this do?I can sample distribution at point earlier

in the anneal

I useful for Quantum Boltzman Sampling

I enabling capability for machinelearning

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Reverse anneal enables hybrid algorithms

0 2 4 6 8 10 12

Time ( s)

0

5

10

15

20

25

30

Energ

y s

cale

Reverse annealing protocol

Transverse A

Longitudinal BPrepare initial state

Anneal backwards to s*

Dwell at s* for some time

Ramp

A new Quantum Machine Instruction (QMI)

1. Initialize given classical state2. Increase transverse �eld to speci�ed

value s*3. wait for dwell time4. anneal forward to complete

Tunable local search

• N. Chancellor “Modernizing quantum annealing using local searches”, New J. Phys. 19, 023024 (2017)• “Reverse Quantum Annealing for Local Re�nement of Solutions”,D-Wave Whitepaper, www.dwavesys.com/resources/publications

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Quantum simulation: �ux qubit can behave like a quantum Ising spin

Φ 2

Φ 1

Josephsonjunction

a

"spin-down" circulating current

"spin-up" circulating currentΦ1X

Φ2X

U

δU

Φ1

2h

b

Bll

Bt

Hq = − 12

[εqσz + ∆qσx

]HQS = −gµB

[B||σz + Btσx

]where εq = 2

∣∣Ipq∣∣Φx

q = −hiσz − 12 ∆σx

Parameter QUBIT Quantum Ising Spinbias energy εq/2 gµBB|| or h

tunneling energy ∆q/2 gµBBtmagnetic moment

∣∣Ipq∣∣ gµB

Binary information encoded in �ux basis: |0〉 → |↓〉 and |1〉 → |↑〉12 / 25


Quantum simulation of transverse �eld cubic Ising lattice (R. Harris)

H3D(s) = −Γ(s)

2 ∑i

σxi + J (s) ∑

〈i,j〉Jijσ

zi σz

jI 3D transverse Ising models embedded in

D-Wave QA processorI Quantitative agreement with locations of phase

transitions:vs. disorder (doping p) & transverse �eld Γ

0.16 0.18 0.2 0.220

0.5

1

1.5

2

2.5

s

χAFM×

105(Φ

−1

0)

p = 0p = 0.05p = 0.1p = 0.15p = 0.2

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Quantum simulation of topological phase transition (A King)

vortex anti-vortex0 0.5 1 1.5 2

0

0.1

0.2

0.3

s = 0.30

s = 0.25

s = 0.20

KT

Ordered

PM

Γ/J

T/J

QA @ 8.4 mKUpper transition

0.2 0.25 0.30

0.1

0.2

0.3

0.4

0.5

0.6

0.7

PM critical PM

Annealing parameter s

Ord

erpa

ram

eter

〈m〉

QMCQA

A. King, et al., “Observation of topological phenomena in a programmable lattice of 1,800 qubits” arXiv:1803.02047 14 / 25


Overview



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Progression of processor scale over time

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Important processor characteristics

I number of qubitsHow large of a problem can be posed?

I connectivityHow feasible is it to solve my problem?

I noiseHow precisely can a problem be posed?How well will QA perform?

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Next generation architecture signi�cantly enhances connectivityChimera C16 - DW 2000Q Pegasus P6 - 680 Qubit Prototype

I most signi�cant architecture change since �rst processor D-Wave OneI enabled by major technology changes in fabrication stackI have demonstrated P6 prototype

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Pegasus architecture signi�cantly enhances connectivityChimera C16 - DW 2000Q Pegasus P6 - 680 Qubit Prototype

Device Count C16 P6 P12 P16Qubits 2048 680 3080 5640Couplers 6000 4784 21764 40484max degree 6 15 15 15

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A closer look at Pegasus

Chimera - C4

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Basic Graph Embedding Statistics

C16 P6 P16Complete Graph 64 (17) 60 (7) 180 (17)Complete Bipartite 64x64 (16) 52x52 (5) 172x172 (15)Cubic Lattice 8x8x8 (4) 5x5x12 (2) 15x15x12 (2)Factoring Circuit 16-bit (16) 10-bit (5) 30-bit (15)Grid with Diagonals 16x16 (6) 15x15 (6) 45x45 (6)

(max chain length in blue)

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Compare embedding of graphs with similar average degree

Chimera C16 - DW 2000Q Pegasus P6 - 680 Qubit Prototype

Logical Qubits 366 318Average chain length 5.6 2.1Average degree 24 25

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Noise and coherence are important for quantum annealing

Lower intrinsic device noise will allow:

I more precise control of h, J, Γ

I more multiqubit tunneling

I faster calibration

�gure from Denchev, et al., PRX 6 031015 (2016), “What is the Computational Value of Finite-Range Tunneling?”

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Continuing research on lower noise materials

Examining alternatives

I conductor material & processing

I dielectric material & processing

0

50

100

150

200

250

TunnelingLineWidth

(µΦ0)

early R&D

DW1prod

DW2 prod A

DW2 prod B

R&DA

R&DB

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Summary

I D-Wave 2000Q processor

I Pegasus architecture signi�cantly increases connectivity

I continued progress on noise & coherence

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d-wave systemsfuture hardware directions of quantum annealing 1cm qubits europe 2018 d-wave users...

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