design considerations for the chain magnetic storage array

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  • S. A. Abbas

    H. F. Koehler

    T. C. Kwei

    H. O. Leilich

    R. H. Robinson

    Design Considerations for the Chain MagneticStorage Array

    Abstract:A computerstoragedesign usingthe chain store device as both a DRO and an NDRO storageelement is discussed for anarray organization of one megabit capacityand 5QO-nsec cycle time. The bit/sense system and schemes for minimizing the longitudinalfields insidethe array during the "write" portion of the cycle are presented.

    Noisedueto difference in the information statesof the device is studiedexperimentally and throughevaluations of computersolutionsof simulated bit/sense lines. The word-line characteristic impedance and its dependence on the magnetic behaviorof the device duringthe "read" portionof the cycle and on the sending and receiving end terminations are examined with consideration given to long wordlines. Sources of noiseand bit-to-bitinteraction are discussed and comparisons between calculated and experimental results obtainedfrom a small model of the array are given.



    The chain store magnetic film element/ which was devel-oped from the chain magnetic memory element," is eval-uated here on the basis of its actual collective perform-ance in a typical DRO and NORa storage system. Theobjective of this study was a large (106-bit) and fast (500-nsec) word-organized memory with diode selection, usingthe relatively large signal output and the high packagingdensity which are possible with this device.

    This paper considers a possible packaging arrangement,the characteristics and problems of the bit/sense wiringscheme, and the transmission properties of the chain as aword line. Interaction and noise problems, as well as noiserejection means, are also discussed.

    Memory package

    Because copper chains are exposed to a plating bath onall surfaces, they must be self-supporting structures. Tofacilitate handling during etching and plating, 32 chainsof 72 bits each are tied together with small tie-bars andtreated as a batch (Ref. 1, Fig. lOa). In the designedmemory package, these chains are inserted into a "nest"(Ref. 1, Fig. lOb), etched from lO-roil-thick copper-Mylar-copper laminate, which acts as support, protection, andword current return for the chain, and as a container forthe selection diodes in strip form. The ends of the chains

    are welded to provided tabs in the nest and the tie-bars arethen removed.

    Sixty-four of these nests are stacked to form a module(Fig. 1), containing 2048 words of 72 bits each. Eight ofthese modules would be connected by a double bit/sensesegment of 8192bits each to form a 1.2 X 106-bit memoryarray. Chains on each plane are connected in pairs atone end with a common "return" which is verticallyconnected to the returns of adjacent planes to form a"gate slice" (Fig. 1). This gate slice has a minimum capac-itance with respect to other memory parts since only itssides face other gate slices. The capacitance to all bit-sense wires in this segment is the largest portion of thegate capacitance.

    The chains are word lines, and may be shorted to thereturns since the delay time (2 nsec) is small compared tothe designed word current rise time (20 nsec), resulting ina minimum need for selection circuitry, 1 diode per word.The selection matrix is square, 128 drivers X 128 gates.The 128 drivers supply two 16-diode strips in each of the64 planes. The total of 16 gate slices per module multipliedby 8 modules yields 128 "gate drivers."

    To simulate the array just described, a cross-sectionmodel was designed, built and tested. It consisted of twohand-wired modules, one of which contained chains with


  • Figure 1 Array configuration.


    36 bits per word (Fig. 2). Although few planes in the work-ing module were operational, they were all populated withtested devices. All the bits were wired, including thedummy module, with connections brought out to allowseveral bit/sense winding schemes to be examined forintramodule and intermodule interactions.

    Bitl sense system

    The design objectives of the bit/sense system were tominimize interaction between the lines and to satisfy trans-mission requirements in terms of impedance, attenuation,delay, and bit noise. It was also necessary to minimizefields generated by the bit/sense wires along the chain (thelongitudinal direction). A schematic of the system, shownin Fig. 3, consists oftwo common bit!sense lines, each link-ing n bits with a bipolar current driver at one end and adifferential sense amplifier at the other end. A cross-section of the wiring pattern is shown in Fig. 4. Thedimensions indicated in Fig. 4 were those used in the ex-perimental model.

    In the pattern shown in Fig. 4, called the alternatingpattern, two features are to be noticed. First, along thebit line the current direction across the array stack alter-nates from chain to chain. This has the effect of reducingthe longitudinal field generated by the total bit/sensesystem. It also reduces the self-inductance of the bit/senselines. Second, the wiring pattern involves cross-over, sothat two chains on a gate slice would consist of One chainlinking line A and the other chain linking line B. The pur-pose is to cancel the gate noise components by makingthem of the common-mode type.

    Bit/sense transmission

    A computer program was used to calculate the trans-mission line properties. The parameters were defined interms of an equivalent circuit per unit bit section (thelength of line between two adjacent planes) as shown inFig. 5. The parallel network RILl was the linear model forchain loading. A spacing (Ax) of 10 mils between planeswas used in the calculation. Other parameters were definedas: 303


  • Figure 3 Bit/sense system schematic.

    30 mils

    L.. __.

    -=VA RA+





    VA-VBZB + '-v---"

    VB Ra Senseamplifier


    A N


    ~---t--- oJ

    A I ......-------'B------------,


    3 senselinepairs

    Figure 2 Test model.


    Figure 4 Alternate bit-wire pattern.

    Figure 5 Bit/sense line equivalent circuit per bit.

    Various transmission properties have been calculated.The results are:

    RO LoR1

    L 1


    1) Zo = 110 n 12%. The variation in Zo is due tocoupling from the neighboring bits and the worst-casebit loading effect.

    2) Delay, fl, is 1.6 psec per bit.

    Favorable disturb

    R1 = 0.0085 nL1 = 0.0311 nH

    Unfavorable disturb

    R1 = 0.00845 nL 1 = 0.0435 nR

    4) R1 , L1 - the equivalent circuit values for the chains.They are obtained from a computer curve-fitting pro-gram, using as input the back voltages of chains dis-turbed by a bit current in the same (favorable disturbs)and opposite direction (unfavorable disturbs) as the bitcurrent used in the previous write cycle. The data are:

    2) Co - capacitance between adjacent bit/sense lines asshown in Fig. 6. This capacitance is found by two inter-section capacitances Cn in series. The value is 0.01 pFper plane.

    3) La - line inductance of line A or B. This is composedof three inductances:

    (a) L D inductance of line A or B (the self-inductanceof the line plus the mutual inductance resulting fromthe alternate wiring pattern with crossovers).L D = 0.107 nR/bit

    (b) m - mutual inductance between lines A and B.m = 0.0122 nR/bit.

    (c) M - mutual inductance between line A or Bandthe rest of the bit lines in the array.

    M = .0285 nH/bit (36 th bit of a 72-bit chain plane).The polarity of M is dependent upon the polarity ofthe bit current, and is also a function of the position inthe array. The worst-case value is quoted here.

    1) Ro-resistance of either line A or B (for #36 wire, Ro =0.346 X 10-3 n).


    S. A. ABBAS BT AL.

  • 6,'----------------





    tz,Figure 6 Bit/sense wiring details.

    Time in nseo








    j-1.5 ]



    Time in nanoseconds















    i1.~-700a" -800~

    ;:; --900

    Figure 8 Bit-voltage recovery.

    Figure 7 Sense signal transmission.3) Fig. 7 shows the sense signal distortion for a bit seg-ment of n = 8k bits, using #36 wire. TIle attenuationis about 13%.

    4) Fig. 8 shows the noise recovery due to the bit current.

    The experimental model was used to verify some of thecalculated values. Because of the small size of the model,four parameters were investigated, M 12 (mutual inductancebetween adjacent bit lines), CB , Zo, and ~. All checkedwell with the calculated values.

    Information noise

    In general, the impedances of line A and line B are notequal. One of the causes for their difference is that the bitslinking them have unequal loading because of their dif-ferently magnetized states or because of the informationstored. The resultant voltage is called information noise.

    A special test jig was built to study this noise contribu-tion. It was found that the worst-case pattern is one inwhich the two lines are uniformly stored but with oppo-sitely magnetized information states. The peak differencevoltage per bit was observed to be between 0.05and 0.2 mVfor I B = 200 rnA (20 nsec risetime). Tests also showed noclear correlation between the information noise voltage andthe shape of the S-curves.1 Thus, one might think of S-curve valuesas those reflectingthe total or integrated effectof the different disturb pulses, since the values are takenafter the disturb pulses are comp


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