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Design for manufacturability foranalog, radio frequency, andmillimeter wave designs

Lynn Wang, Gail Katzman, Yongfu Li, Vikas Mehrotra,Janam Bakshi, et al.

Lynn Wang, Gail Katzman, Yongfu Li, Vikas Mehrotra, Janam Bakshi, AhmedAbdulghany, Michael Simcoe, Rais Huda, Zhao Chuan Lee, Don Blackwell,Thomas Hermann, Uwe Paul Schroeder, Thomas McKay, Sriram Madhavan,"Design for manufacturability for analog, radio frequency, and millimeter wavedesigns," Proc. SPIE 10962, Design-Process-Technology Co-optimization forManufacturability XIII, 109620G (20 March 2019); doi: 10.1117/12.2514769

Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

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Design for Manufacturability for Analog, Radio Frequency, and Millimeter Wave Designs

Lynn Wanga, Gail Katzman, Yongfu Li, Vikas Mehrotra, Janam Bakshi, Ahmed Abdulghany, Michael Simcoe, Rais Huda, Zhao Chuan Lee, Don Blackwell, Thomas Herrmann, Uwe Paul

Schroeder, Thomas McKay, Sriram Madhavan

aGLOBALFOUNDRIES, 2600 Great America Way, Santa Clara, CA, USA 95054

ABSTRACT

A suite of DFM enablement is enhanced to address the unique needs of analog, RF, and mmWave designs in the custom design flow. The DFM rules and patterns are made stricter beyond baseline requirements, and new DFM rules and patterns are added to further reduce layout-dependent device variability. Auto-fixing in the custom design flow is enhanced to meet these new requirements. New DFM enablement is developed for device matching for differential circuits and sensitive devices. Lastly, novel DFM fill strategies are implemented to reduce the variability of passive devices operating at high frequencies. Using DFM-aware fill, a 2% quality-factor loss for a mmWave inductor operating at 30 GHz is shown to be sufficient for meeting manufacturing planarity requirements. Keywords: DFM, analog, RF, mmWave, fill, device matching, scoring, pattern matching, automated layout fixing

1. INTRODUCTION As analog, Radio Frequency (RF), and MilliMeter Wave (mmWave) Integrated Circuit (IC) designs target advanced technology nodes, novel Design for Manufacturability (DFM) enhancements are needed to reduce device variability and improve manufacturability and yield [1]. Compared to digital ICs, analog, RF, and mmWave layout designs have more stringent electrical tolerances but more relaxed area constraints. Consequently, more aggressive DFM strategies should be pursued for these designs. In addition, high frequency RF and mmWave ICs operating in the range of 2 GHz and beyond present new design and process co-optimization challenges [2].

Historically, DFM enablement has been developed for digital designs, which are densely packed with transistors using minimum critical dimensions that push the optical resolution limit and hence are difficult-to-manufacture. The specific needs of digital designs have been addressed through the development of DFM methodologies, such as rule-based scoring, pattern-based checking, and in-design automated fixing as part of the place-and-route reference flows[3][4][5]. Since analog, RF, and mmWave designs typically use less transistors with larger critical dimensions compared to that of digital, the established DFM tool suite has been sufficient for these designs, manufacturing successful products at mature technology nodes. As these designs migrate to advanced technology nodes, however, circuit designers are requesting DFM automation support for reducing device variability in addition to improving manufacturability.

A suite of DFM enhancements is developed to address the specific needs of analog, RF, and mmWave designs in the custom design flow. The DFM rules and patterns are made stricter beyond baseline requirements, and new DFM rules are added to further reduce layout-dependent device variability. Auto-fixing in the custom design flow is enhanced to assist the layout designer to meet these new requirements. New DFM enablement is developed for device matching for differential circuits and other sensitive devices. Lastly, novel DFM fill strategies are implemented to reduce the variability of passive devices operating at high frequencies.

This paper is organized as follows: Section 2 describes the background on the state-of-the-art DFM enablement and how they are enhanced for analog, RF, and mmWave designs. Section 3 presents applications of the enhanced DFM tools. Section 4 concludes the paper.

Design-Process-Technology Co-optimization for Manufacturability XIII, edited by Jason P. Cain, Proc. of SPIEVol. 10962, 109620G · © 2019 SPIE · CCC code: 0277-786X/19/$18 · doi: 10.1117/12.2514769

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2. BACKGROUND ON DFM ENABLEMENT AND ENHANCEMENTS FOR ANALOG, RF, AND MMWAVE DESIGNS

New and enhanced DFM tools are developed to address the unique needs of analog, RF, and mmWave designs. The state-of-the-art DFM tool suite for digital designs is used as the baseline for further enhancements for analog designs. Four areas for improvement are identified: pertinent tools for custom designs, checks and auto-fixing methodologies to reduce device variability, device matching checks for sensitive circuits, and fill for passive devices. These enhanced DFM components form a novel tool suite for physical design that reduces variability and improves manufacturability.

2.1 Background on Analog, RF, and mmWave Applications

Analog applications drive new opportunities for semiconductor manufacturing. These applications can be divided in three categories based on the band of operating frequencies, from the lowest to the highest: analog baseband (otherwise commonly known as analog), RF, and mmWave. Refer to Table 1.

Design Type Example Operating Frequency Example ApplicationsAnalog Baseband ~20 kHz Television, radio Radio Frequency (RF) ~2 GHz 3G/4G transceivers Millimeter Wave (mmWave) ~30 GHz 5G transceivers, satellite antennas

Table 1: Summary of analog design types

Table 1 summarizes the three categories of analog applications based off of operating frequencies. Baseband applications include televisions and radios, RF include Third Generation (3G) and Fourth Generation (4G) transceivers, and mmWave include Fifth Generation (5G) transceivers and satellite communication. Analog applications bring about a diverse set of design requirements, in which the operating frequency is one of the key determining factors of the unique design tolerances. These tolerances drive new DFM challenges to reduce layout-induced circuit variability and improve manufacturability and thus yield.

2.2 The DFM Enablement for Digital versus Analog, RF, and mmWave Designs

The unique needs of analog, RF, and mmWave designs are identified and compared with that of digital across four categories: tools, checks and auto-fixing, device matching, and fill. Refer to Table 2.

Requirements Digital Analog, RF, and mmWave

Tools Place-and-route Custom

Checks and Auto-Fixing Baseline Stricter compliance checking and additional rules/patterns are strongly recommended to reduce device variability

Device Matching Not applicable Unique requirements for identical devices and differential circuits

Fill Baseline Unique requirements for passive devices

Table 2: Summary of the unique requirements for digital versus analog, RF, and mmWave designs

Table 2 describes the DFM automation enhancements that are built for analog, RF, and mmWave designs, leveraging the established digital-based methodologies. For tools, DFM is integrated with the custom design tools in addition to the place-and-route flows. For checks and auto-fixing, stricter compliance checks and additional rules and patterns are strongly recommended to reduce device variability for analog designs. Because device matching is not applicable for digital designs, new tools are developed to support this unique requirement for identical devices and differential circuits. Lastly, the fill implementation for baseline, digital designs is enhanced to support the passive devices at high operating frequencies greater than 30 GHz.


2.3 The DFM Enablement and Methodologies for Improving Layout Quality and Productivity

The DFM enablement consists of various methodologies that can be generalized to the following categories: checking, fixing, analysis, and fill. These methodologies are developed to improve the productivity and quality of layout designs that can be easily inserted in the existing physical design flows. Table 3 summarizes the DFM enablement categories, the corresponding methodologies, and their purposes in the physical design flow.

Enablement Methodologies Purposes

DFM Compliance Checking

DFM rule- and pattern-based checking and scoring

• Reduce layout-induced circuit variation • Improve layout manufacturability and

functional yield • Reduce 2D lithography hotspots and other

process weak points DFM Fixing Automated rule- and pattern-based

fixing • Improve layout productivity and quality • Alleviate manual fixing

DFM Analysis Analog device matching checker • Improve schematic and layout productivity and quality

• Alleviate manual checking Fill Exclude fill region • Reduce layout-induced topography

• Reduce layout-induced circuit variation at high operating frequencies

Table 3: Summary of DFM enablement and corresponding methodologies

Table 3 presents a summary of the DFM enablement and the purposes for the corresponding methodologies. For compliance checking, rule- and pattern-based methodologies reduce device variability and improve layout manufacturability. For fixing, rule- and pattern-based methodologies improve layout productivity and quality, alleviating manual fixing, which may be prone to human errors. For analysis, the analog device matching checker improves layout productivity and quality: automating the device matching checks alleviates manual effort and prevents human errors. Lastly, fill methodologies are enhanced to reduce topography-induced manufacturing issues as well as layout-induced circuit variation at high operating frequencies.

The DFM methodologies described in Table 3 are inserted in the custom design flow shown in Figure 1.

Figure 1: DFM insertions (highlighted in orange) in the custom design environment


Figure 1 presents a flow chart depicting DFM insertions in the custom design environment. The key, DFM-enhanced components are highlighted in orange: analog DFM device matching schematic checks, DFM-aware P-cells, DFM automated fixing, DFM rule/pattern checks, analog DFM device matching layout checks, and DFM-aware fill. A typical physical design flow for custom designs is as follows: after completing circuit schematics, analog DFM device matching schematic checks are used to verify that the sensitive circuit topologies are identical. P-cells enhanced with DFM rules are used to create the layout designs. Then, DFM auto-fixing tools are deployed to increase the rate of via redundancy insertions and reduce the number of manufacturing weak points. After the layouts pass both Layout versus Schematic (LVS) and Design Rules Checks (DRC), DFM rule- and pattern-based checks as well as device matching checks provide additional layout-fixing guidance. The last step is fill, which is enhanced for mmWave passive devices.

2.4 The DFM Tool Highlights for Analog Designs

The DFM tool highlights from the flow presented in Figure 1 are presented in the follow sections. Section 2.4.1 presents the DFM-aware checks and automated fixes in the custom design environment, section 2.4.2 presents the DFM checks for analog device matching, and section 2.4.3 presents the DFM-aware fill for mmWave passive devices.

2.4.1 DFM-Aware Checks and Automated Fixes in the Custom Design Environment

Compared to digital designs, analog designs are less dense and hence have more room for layout improvements in the available white space. Thus, they should be driven to comply with stricter DFM compliance requirements. See Figure 2.

(A) (B)

(C) Figure 2: Analog layout designs (A) are less dense compared to digital (B); thus, these designs should drive to comply with stricter DFM compliance requirements (C).

Figure 2 juxtaposes a layout design of an analog RF transceiver (A) to that of a digital CPU (B) for the poly layer and compares the DFM compliance requirements between that of analog and digital (C). Figure 2(A) shows that the RF layout design is less dense than that of digital (B), with more room for layout improvements in the available white space. Hence, analog designs should strive to comply with stricter DFM compliance criteria. For Priority 1 (P1) rules and patterns, compliance requirements are the same for all design types. The differences lie in the Priority 2 (P2) rules and patterns, in which the compliance requirements are stricter for analog designs. For DFM rules, the P2 scores for analog designs must be greater than or equal to 0.99, compared to the baseline digital compliance criteria of 0.95. For DFM patterns, the P2 violations are strongly recommended to be fixed for analog designs, whereas for digital designs, they are used for monitoring purposes only.

2.4.2 DFM Checks for Analog Device Matching

In addition to compliance checks, the DFM Analog Device Matching Checker (ADMC) provides checks to identify mismatches in identical, sensitive devices at both the schematic and layout design stages for guided fixing. The ADMC

DFM Compliance Checks Criteria for Priority 1 Criteria for Priority 2

Rules (score) > 0.99 > 0.99

Digital : > 0.95

Patterns Must fix Strongly recommended fix

Digital: monitoring purposes


leverages logical connectivity information from the LVS checks and physical information from the DRC to perform advanced device matching checks [6] [7]. The methodology is based off of building a library of pre-determined circuit topologies commonly used in analog circuit designs. Then, using connectivity information, the topologies are identified in a new design. Figure 3 shows how circuit topologies are analyzed at the schematics level to automatically identify current mirrors and other differential pairs.

(A) (B)

Figure 3: The current mirror circuit topology (A) is detected in the bandgap filter (B).

Figure 3 shows a current mirror topology (A), and using the ADMC, this pair of devices is identified in the larger bandgap filter design (B). These circuits are identified for DFM device matching, in which the schematic check ensures relevant P-cell parameters, such as gate lengths, gate widths, and well sizes, are identical.

Once the topologies have been identified in the schematic checks, they are then mapped to the layout. The DFM checks go beyond DRC and identify mismatches in physical dimensions, such as widths, lengths, and well dimensions. The DFM device matching checks also identifies mismatches in symmetry for two sensitive transistors, such as mismatches in the number of contacts between source and drain. Lastly, these checks also identify mismatches in proximity in order to identify any neighboring shapes that may cause layout-induced variability for the two sensitive transistors.

2.4.3 DFM-Aware Fill for Passive Devices

One of the last but important steps in the physical design flow is fill insertion. Fill insertions at high operating frequencies present a tradeoff between manufacturability and design. On the manufacturing side, fill insertion improves planarity. On the design side, fill insertion reduces the Quality (Q)-factor, which is the ratio of the inductance to the resistive loss, as shown by Equation 1:

Q(ω) = ωL(ω)/R(ω) (Equation 1)

where Q is the quality factor, ω is the operating frequency, L is the inductance, and R is the resistance. Q is dependent on ω. At low operating frequencies, L and R are predictable. At higher operating frequencies, however, Q is more difficult to predict: due to skin effects and eddy currents, additional R loss is generated, lowering the Q [8]. To examine the tradeoffs between process planarity and Q, a Chemical Mechanical Polishing (CMP) model is used to simulate topography, and a rigorous electromagnetics (EM) field-solver is used to model and characterize RF and mmWave electrical effects.

3. EXPERIMENTAL RESULTS Compared to digital designs, analog designs should drive to comply with stricter compliance requirements and additional DFM rule checks to reduce variability. To demonstrate the possibility of complying with stricter compliance requirements, four DFM-compliant designs from different applications: digital, analog baseband, RF, and mmWave are examined. The DFM scores are shown for standard DFM rules that are developed to improve functional yield and additional DFM rules to reduce device variability as shown in Figure 4.


(A) (B)

Figure 4: Digital, analog baseband, RF, and mmWave layout designs are compared for standard DFM rules developed for improving functional yield (A) and additional DFM rules developed for reducing device variability (B). Analog, RF, and mmWave designs can be driven to comply with stricter compliance requirements with scores > 0.99.

As shown in Figure 4, analog baseband, RF, and mmWave designs pass stricter compliance checks for standard DFM rules, such as redundancy, metal-via enclosure, minimum metal area, and active-contact enclosure. They also pass additional DFM rule checks for 1x metal jogs, active jogs, and poly-active extensions.

One key technique to meet DFM compliance requirement is using the auto-fixing tools. Fixing rates for analog baseband, RF, and mmWave are compared to that of the digital baseline for four types of DFM violations: via redundancy, minimum metal area island, metal-via line-end extension, and 2D weak points (patterns) as shown in Table 4.

Violation Types Digital Analog (Baseband) RF mmWave Via redundancy Baseline 5x 2x N/A (no violations) Minimum metal area island Baseline 6x 6x N/A (no violations) Metal-via line-end extension Baseline 1x 2x N/A (no violations) 2D Weak point (pattern) 100% N/A (no violations) N/A (no violations) N/A (no violations)

Table 4: Summary of auto-fixing rates for digital, analog, RF and mmWave layout designs

In Table 4, compared to the digital baseline, analog baseband, RF, and mmWave layout designs show better fixing rates of up to 6x, due to more availability in the white space. They are also clean to P1 and P2 pattern-based checks, so no fixing opportunities were identified by the pattern-based auto-fixing tool.

Once the layout designs meet DFM compliance criteria, the Analog Device Matching Checker (ADMC) is used to provide additional layout fixing guidance. An ADMC application is demonstrated for color matching. Refer to Figure 5.

(A) (B)

Figure 5: Normalized frequency FT and FMAX are plotted against thirteen coloring combinations for an RF device (A). The ADMC identifies mismatches in the source and drain metal coloring for two devices (B).

Figure 5 shows measured frequency FT (unity current gain) and FMAX (unity power gain) for thirteen, metal 1 and metal 2 exposure 1 and exposure 2 masks combinations for an RF device. At higher operating frequencies, RF and mmWave devices show sensitivity to coloring for key, electrical parameters: while FT remains relatively consistent with coloring, FMAX can vary by 15%. The ADMC ensures that the source, drain, and gate metal 1 coloring for matched devices are identical.


The last step of the physical design flow is fill insertion. When the baseline fill methodology that has been developed for digital designs is applied to inductors at high operating frequencies, it improves the process planarity at the cost of degrading the electric Q. One solution is to create a fill exclude region around the inductor. To determine the dimensions of the exclude region, tradeoffs between planarity and Q were examined using CMP and EM simulations. The CMP simulation results are presented in Figure 6, and the EM results are shown in Table 5.

(A)

(B)

(C)

Figure 6: The CMP topography simulations are used to examine the impact on process planarity caused by the fill exclude region. The topography plots for fill insertion with no exclude region (A) and with the exclude region indicated by the two arrows (B) are shown. The topography values taken at the dashed lines (A) and (B) are compared (C).


The CMP simulations in Figure 6 identify a range of exclude region dimensions with sufficient planarity. Exclude region range from baseline to baseline + 4 units was simulated. The topography plots are examined comparing baseline fill to exclude region with fill. The worst case topography change is 50A, which is a minor change. No CMP hotspots are observed.

The EM simulator models the electric Q with the exclude regions, and the DFM tradeoff analysis between Q versus planarity simulations shown in Figure 6 defines an exclude region for operating frequencies 30 GHz and beyond. Refer to Table 5.

Exclude Region Q % Δ Q Δ Planarity Baseline+1 13.8 -30 GreenBaseline+2 16.2 -20 GreenBaseline+3 17.9 -10 GreenBaseline+4 19.3 -2 Green

No Fill 19.7 Ideal RedTable 5: Summary of exclude region dimensions and corresponding Q, % Δ Q, and Δ planarity

Table 5 presents a summary of the exclude region dimensions, Q, percent Q change, and normalized planarity change, in which green represents a negligible change and red represents a major change that would cause manufacturability issues. High Q is desirable for mmWave inductors. Inductor Q, highest at no fill, is reduced by up to 30% when fill is placed too close to the coil. Planarity simulations show minor topography increases compared to baseline with no CMP hotspots with the exclude regions. The exclude region for inductors operating at 30GHz and beyond is thus defined at baseline + 4 units, with a negligible Q loss of 2% and minor planarity changes.

4. CONCLUSIONS A suite of DFM tools has been developed to support the unique needs of analog, RF, and mmWave designs. Analog designs are driven to meet stricter DFM compliance requirements for standard DFM rules to improve functional yield and additional DFM rules to reduce device variability. The DFM analog device matching checker prevents mismatches in coloring for identical devices and reduces FMAX variability by 15%. The DFM tradeoffs between Q versus process planarity show that using a fill exclude region around an inductor achieves negligible Q loss (~2%) with no CMP hotspots.

REFERENCES

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[7] Li, Y., Perez, V., Tripathi, V., Lee Z. C., Tseng, I-L., and Ong, Y. S., "Variability-aware double-patterning layout optimization for analog circuits," Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880E (20 March 2018).

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