cmos analog and radio-frequency integrated-circuit design
TRANSCRIPT
CMOS Analog and Radio-Frequency Integrated-Circuit Design
Employing Low-Power Switched-Capacitor Techniques
by
Yu Song
Submitted in Partial Fulfillment
of the
Requirements for the Degree
Doctor of Philosophy
Supervised by
Professor Zeljko Ignjatovic
Department of Electrical and Computer Engineering
Arts, Sciences and Engineering
Edmund A. Hajim School of Engineering and Applied Sciences
University of Rochester
Rochester, New York
2011
ii
Curriculum Vitae
The author was born in Hebei Province, China in 1980. He attended Nankai
University (Tianjin, China) from 1999 to 2006, and graduated with a Bachelor of
Science degree in Electronics in 2003 and a Master of Science degree in Optics in
2006. He came to the University of Rochester in the fall of 2006 and begun graduate
studies in the Department of Electrical and Computer Engineering with a
concentration in analog/radio-frequency integrated circuit design. He pursued his
research under the direction of Professor Zeljko Ignjatovic and received the Master of
Science degree from the University of Rochester in 2008.
iii
Acknowledgements
My graduate studies at the University of Rochester have been full of
opportunities to learn from a large body of faculty members and students with
extensive and profound knowledge. I would like to thank my advisor, Prof. Zeljko
Ignjatovic, for investing considerable time, effort and resources in my graduate
studies. He provided me invaluable guidance throughout the years and it is a privilege
to be in his group. I, also, want to thank the members of my thesis committee for
providing me insightful advice and feedback. Besides, I am grateful for the assistance
received from members of Prof. Ignjatovic's group, Prof. Mark Bocko's group and
Prof. Hui Wu's group, regarding computer environment setup, circuit design
discussion, testing assistance, and so on.
Thanks to the MOSIS Educational Program for the Sigma-Delta modulator
project fabrication in the IBM 130nm CMOS process.
iv
Abstract
We propose and verify the design of low-power, high-performance CMOS
Switched-Capacitor (SC) circuits for analog and radio-frequency (RF) applications. In
low-cost CMOS semiconductor processes, SC circuits play a crucial role in
implementing accurate analog signal processing functions. However, conventional SC
circuits are usually power-demanding due to the accurate signal settling requirement.
On the other hand, the shrinking of amplifier gain and voltage swing driven by
technology scaling makes SC circuit design in deep sub-micron CMOS processes
more and more challenging. To counteract these problems, low-power SC circuit
techniques suitable for deep sub-micron CMOS processes are investigated in this
work. In the first illustrative circuit example, a 2.5 GHz Phase-Locked-Loop (PLL)
employing a new low-power SC loop filter is proposed, designed and verified in a
0.18μm CMOS technology. By employing the proposed SC loop filter, the
advantages of low reference spur and small on-chip capacitor size are achieved.
While the loop filter consumes a very low power, 1/f noise introduced by the inverter
amplifier is also suppressed. The second circuit example is an audio-band
highly-linear low-power multi-bit Delta-Sigma (ΔΣ) modulator with a SC
nonlinearity-suppressed feedback DAC verified in a 0.13μm CMOS technology. By
employing this proposed scheme, problems with conventional methods to realize
multi-bit feedback DACs are circumvented. The power consumption of the proposed
method can be maintained low. A promising approach to implement practical
multi-bit ΔΣ analog-to-digital converters (ADCs) is demonstrated.
v
Table of Contents
Curriculum Viate ii
Acknowledgements iii
Abstract iv
List of Tables ix
List of Figures x
List of Acronyms xvii
Foreword 1
Chapter 1 Introduction 2
1.1 Motivation 2
1.2 Research Goals 3
1.3 Thesis Organization 6
Chapter 2 Switched-Capacitor Circuits 8
2.1 Discrete-Time Signal Basics 8
2.1.1 Spectra of Discrete-Time Signals 8
2.1.2 Sample-and-Hold Response 10
2.2 Building Blocks in Switched-Capacitor Circuits 11
2.2.1 Sampling Switches 11
2.2.2 Capacitors 16
2.2.3 Amplifiers 19
2.3 Noise in Switched-Capacitor Circuits 25
2.3.1 KTC noise 25
vi
2.3.2 Thermal noise of a switched-capacitor integrator 26
Chapter 3 PLL Frequency Synthesizer 31
3.1 PLL basics 31
3.1.1 Type I PLL 32
3.1.2 Type II PLL 35
3.2 PLL Building Blocks 44
3.2.1 Phase/frequency detector 44
3.2.2 Charge Pump 47
3.2.3 Programmable Divider 48
3.2.4 Voltage Controlled Oscillator 49
3.3 Implementation Issues and Noise 52
3.3.1 Implementation Issues 52
3.3.2 Noise Consideration at Different Nodes 55
Chapter 4 Delta-Sigma A/D Converters 58
4.1 A/D Conversion Basics 58
4.1.1 Sampling and Quantization 58
4.1.2 Oversampling ADC 61
4.2 Basics of Delta-Sigma ADCs 62
4.3 Higher-Order Delta-Sigma ADCs 67
4.3.1 Single-Loop ΔΣ modulators with Distributed
Feedback Paths 69
4.3.2 Single-Loop ΔΣ modulators with Feed-Forward Paths 72
vii
4.3.3 Stability of single loop ΔΣ modulators 75
4.3.4 MASH modulators 81
4.3.5 Techniques to enhance ΔΣ modulator performance 83
4.4 Thermal Noise in ΔΣ ADCs 86
Chapter 5 PLL Design with a Low-Power Active Switched-Capacitor Loop Filter
91
5.1 PLL Loop Filters in literatures 91
5.1.1 Active Continuous-Time Loop Filter 91
5.1.2 Passive Switched-Capacitor Loop Filter 93
5.1.3 Hybrid Loop Filter 96
5.2 Proposed Low-Power Active Switched-Capacitor Loop Filter 98
5.2.1 Sub-Threshold Inverter Amplifier 98
5.2.2 Design of the Low-Power Active Switched-Capacitor
Loop Filter 101
5.2.3 Reference Spur and Noise of the Loop Filter 109
5.3 Other Building Blocks of the PLL Prototype 112
5.3.1 Phase/Frequency Detector 112
5.3.2 VCO 113
5.3.3 Programmable Divider 117
5.4 Prototype Measurement Results 119
5.5 Chapter Conclusion 121
Chapter 6 A Multi-bit ΔΣ ADC with a Low-Power Switched-Capacitor
viii
Nonlinearity-Suppressed DAC 123
6.1 Existing Techniques to Enhance DAC Linearity 123
6.1.1 Layout considerations for capacitor matching 124
6.1.2 Calibration 126
6.1.3 Dynamic element matching 127
6.2 ΔΣ ADCs with Nonlinearity-Suppressed DACs 129
6.2.1 Switched-capacitor ratio-independent multiply-by-N 129
6.2.2 Low-power SC nonlinearity-suppressed DAC 139
6.2.2.1 Gain-Boosted Inverter Amplifier 139
6.2.2.2 Nonlinearity-suppressed DAC 142
6.2.2.3 Noise analysis for the
nonlinearity-suppressed DAC 149
6.2.2.4 ΔΣ ADC using the low-power
nonlinearity-suppressed DAC 159
6.3 Chip Measurement Results 160
6.4 Chapter Conclusion 164
Chapter 7 Conclusion 165
References 168
ix
List of Tables
Table Title Page
Table 3-1 Design parameters for a 2.4GHz PLL 53
Table 3-2 PLL Phase noise transfer function for different noise sources 56
Table 5-1 Karnaugh map for D1 119
Table 5-2 Karnaugh map for D2 119
Table 5-3 PLL performance comparison 122
Table 6-1 ΔΣ Performance summary and comparison 164
x
List of Figures
Figure Title Page
Figure 2-1 Sampling and Sample-and-Hold 9
Figure 2-2 Frequency domain illustration of sampling 10
Figure 2-3 Sample-and-Hold response 11
Figure 2-4 MOS sample-and-hold stage 12
Figure 2-5 Charge injection and clock feed-through suppression by
dummy switch 15
Figure 2-6 Cross section of a MIM capacitor 16
Figure 2-7 A charge redistribution DAC and its equivalent circuit during
output phase 17
Figure 2-8 A typical switched-capacitor integrator 20
Figure 2-9 Equivalent circuit of Figure 2-8 in Phase 2 22
Figure 2-10 Block diagram for a basic negative-feedback system 24
Figure 2-11 Bode plots of loop gain for a two-pole system 25
Figure 2-12 Sample-and-hold equivalent circuit during sampling phase 26
Figure 2-13 Input referred integrator thermal noise power versus gm(RS1+RS2) 28
Figure 2-14 Opamp feedback circuit 29
Figure 2-15 Integrator noise model 30
Figure 3-1 Phase-locked loop block diagram 31
Figure 3-2 Magnitude and phase response of the Type I PLL loop gain 33
Figure 3-3 Second order Type II PLL block diagram 36
xi
Figure Title Page
Figure 3-4 Magnitude and phase response of the Type II PLL loop gain 37
Figure 3-5 The ratio ω-3dB/ωc versus damping factor 40
Figure 3-6 Time-domain output frequency response of a second-order Type II
PLL 40
Figure 3-7 Fourth order Type II PLL block diagram 41
Figure 3-8 Maximum phase margin versus n 42
Figure 3-9 Maximum ωc/ωref versus n 44
Figure 3-10 The inputs and output of an XOR gate 45
Figure 3-11 Implementation of a PFD 46
Figure 3-12 State machine diagram for the PFD 46
Figure 3-13 Principle of charge pump with loop filter 47
Figure 3-14 Clock aligning circuit 48
Figure 3-15 Block diagram of the divider 48
Figure 3-16 Topology of the negative-gm LC oscillator 50
Figure 3-17 Equivalent circuit for the cross-coupled transistors 50
Figure 3-18 Inductor model 51
Figure 3-19 Equivalent circuit of the oscillator 51
Figure 3-20 Mechanism of VCO control voltage ripples 54
Figure 3-21 Magnitude response of a third-order Type II PLL closed-loop
transfer function 55
Figure 3-22 Lineralized PLL phase noise model 56
xii
Figure Title Page
Figure 3-23 PLL noise transfer function response 57
Figure 4-1 Transfer characteristic of quantizers 59
Figure 4-2 Model for a conventional ADC 60
Figure 4-3 Spectral Illustration for a Nyquist rate ADC and an Oversampling
ADC 61
Figure 4-4 ΔΣ ADC Block Diagram 63
Figure 4-5 Linearized model of a ΔΣ modulator 64
Figure 4-6 First-order ΔΣ noise shaping 65
Figure 4-7 Second-order ΔΣ modulator block diagram 67
Figure 4-8 Block diagram for an Mth-order ΔΣ modulator with distributed
feedback 69
Figure 4-9 Block diagram for a 4th-order ΔΣ modulator with weighted
feedback and delay-free integrators 71
Figure 4-10 Block diagram for a Mth-order ΔΣ modulator with weighted
feedback and distributed feedforward 72
Figure 4-11: Block diagram for a Mth-order ΔΣ modulator with weighted
feed-forward 73
Figure 4-12 Output swing of integrators in feed-forward topology 74
Figure 4-13 Output swing of integrators in feedback topology 74
Figure 4-14 STF magnitude response of a 3rd-order modulator 76
Figure 4-15 NTF magnitude response of a 3rd-order modulator 76
xiii
Figure Title Page
Figure 4-16 Block diagram for an Mth-order ΔΣ modulator with weighted
feed-forward 77
Figure 4-17 Root-locus of a 3rd-order modulator with a1=1, a2=1, a3=0.5 79
Figure 4-18 Root-locus of a 3rd-order modulator with a1=1, a2=1, a3=1.5 79
Figure 4-19 A two-stage general structure for a MASH modulator 81
Figure 4-20 Noise analysis for an Mth-order ΔΣ modulator with
weighted feed-forward 87
Figure 4-21 NTFs at different nodes for a 3rd-order ΔΣ modulator 88
Figure 5-1 Dual-path loop filter 1 93
Figure 5-2 Dual-path loop filter 2 93
Figure 5-3 Passive switched-capacitor loop filter and its timing scheme 94
Figure 5-4 Hybrid loop-filter in [64] 97
Figure 5-5 Hybrid loop-filter in [65] 97
Figure 5-6 Cascode inverter amplifier 99
Figure 5-7 Relationship of DC gain and bandwidth on an inverter's power
supply volatge 100
Figure 5-8 Distribution of the amplifier’s DC gain and offset voltage
with the presence of process variations 101
Figure 5-9 Proposed switched-capacitor PLL loop filter with complimentary
charge pumps 102
Figure 5-10 Clocks generator circuit and a set of example clocks 102
xiv
Figure Title Page
Figure 5-11 Phase and gain responses of the sinc and single pole filters 105
Figure 5-12 Magnitude response of the active SC loop filters 106
Figure 5-13 Phase response of the active SC loop filters 107
Figure 5-14 Transient response of VCO control voltages 108
Figure 5-15 PFD schematic 112
Figure 5-16 VCO schematic 113
Figure 5-17 Tuning Characteristics for the nAMOS and pAMOS varactors 115
Figure 5-18 Phase noise model in Eq. (4-35) 116
Figure 5-19 Block diagram of the prescaler 117
Figure 5-20 State machine for the phase select signals 118
Figure 5-21 Circuit implementing the state machine in Figure 4-21 119
Figure 5-22 PLL die photo 120
Figure 5-23 PLL phase noise measurement plot 121
Figure 5-24 PLL output spectrum 122
Figure 6-1 Output power spectral density for a multi-bit ΔΣ Modulator using
a conventional DAC with a component mismatch standard
deviation of 0.1% 126
Figure 6-2 Element selection algorithm for DWA 128
Figure 6-3 Ratio-independent multiply-by-two circuit 130
Figure 6-4 (a) Linearity deviation for the 3-bit DAC 132
Figure 6-4 (b) Linearity deviation for the 7-level DAC 132
xv
Figure Title Page
Figure 6-5 Transfer characteristics for different quantizers 133
Figure 6-6 Sigma-Delta modulator topology 134
Figure 6-7 Quantizer Schematic 135
Figure 6-8 Modulator output power spectral density using the resistor ladder
DAC 138
Figure 6-9 Modulator output power spectral density using the resistor ladder
DAC 138
Figure 6-10 Gain-boosted inverter amplifier 140
Figure 6-11 Voltage transfer characteristic of the gain-boosted cascode inverter
implies a large-gain differential output swing of more than 600mV 141
Figure 6-12 Gain and Voff variation statistics due to process variations 142
Figure 6-13 Schematic of the proposed low-power ratio-independent DAC
(Analog Part) 143
Figure 6-14 A DAC with one virtual ground Φ1 switch 145
Figure 6-15 Linearity deviation plots 147
Figure 6-16 Block diagram for the logic and clock control circuits 147
Figure 6-17 Schematic of the DAC logic control circuits 148
Figure 6-18 Amplifier schematic and equivalent circuit for noise analysis 150
Figure 6-19 The equivalent circuit for the DAC during the reset phase 151
Figure 6-20 The equivalent circuit for noise of Rra 151
Figure 6-21 The equivalent circuit for noise of Rrb 152
xvi
Figure Title Page
Figure 6-22 The equivalent circuit for noise of the inverter amplifier 154
Figure 6-23 The equivalent circuits for DAC charge transfer phase 155
Figure 6-24 The equivalent circuits for DAC charge transfer phase 157
Figure 6-25 The topology of the designed ΔΣ modulator with the
ratio-independent DAC 159
Figure 6-26 Die photo for the ΔΣ modulator prototype 161
Figure 6-27 Layout for the ΔΣ modulator prototype 161
Figure 6-28 ΔΣ modulator output spectrum 162
Figure 6-29 SNDR and SNR versus input signal level 163
xvii
List of Acronyms
ADC Analog-to-Digital Converter
CMOS Complementary Metal Oxide Semiconductor
CP Charge Pump
DAC Digital-to-Analog Converter
DEM Dynamic Element Matching
DNL Differential Nonlinearity
DR Dynamic Range
DWA Data-Weighted Averaging
IC Integrated Circuit
INL Integral Nonlinearity
ISF Impulse Sensitivity Factor
LF Loop Filter
LSB Least Significant Bit
MASH Multi-stage noise shaping
NMOS N-channel Metal Oxide Semiconductor
OSR Over-Sampling Ratio
OTA Operational Transconductance Amplifier
PD Phase Detector
PFD Phase/Frequency Detector
PLL Phase-Locked Loop
PMOS P-channel Metal Oxide Semiconductor
xviii
PSD Power Spectral Density
RF Radio-Frequency
SC Switched-Capacitor
SFDR Spurious-Free Dynamic Range
SNDR Signal-to-Noise and Distortion Ratio
SNR Signal-to-Noise Ratio
SR Slew Rate
TSPC True-Single-Phase-Clock
VCO Voltage-Controlled Oscillator
XOR Exclusive OR gate
1
Foreword
This thesis covers the author's main research contributions during his PhD studies
at the University of Rochester from September 2006 to July 2011, under the
supervision of Prof. Zeljko Ignjatovic. The author is the primary contributor to the
thesis and performed all the design and experiments.
An article coauthored with Prof. Zeljko Ignjatovic related to the contents of
Section 5.2 and Section 5.4 of this thesis is accepted for publication in IEEE
Transactions of Circuits and Systems II, the issue of September 2011.
A manuscript coauthored with Prof. Zeljko Ignajtovic related to Section 6.2.2 and
Section 6.3 is being prepared for IEEE Transactions of Circuits and Systems II.
2
Chapter 1
Introduction
1.1 Motivation
The development of modern microelectronics has been greatly boosted by
complementary-metal-oxide-semiconductor (CMOS) technology. CMOS offers cost-
and power-efficient high-density circuit integration, and due to its versatility it finds
more and more important applications in the fields of mixed-signal (analog/digital)
and radio-frequency (RF) integrated-circuit (IC) design [1], [2]. With the aggressive
technology scaling during the past decades, CMOS feature size has decreased to tens
of nanometers. While technology scaling is beneficial for digital circuits in terms of
reduced device size, increased operation speed and less power consumption [3], it
imposes several disadvantages on analog and RF circuit designs. One problem is the
reduction of the voltage supply, which causes insufficient voltage headroom and/or
signal swing in some conventional circuit topologies. Another problem is that along
with the shrink of transistor length, amplifier DC gain also decreases. This increases
finite gain related errors in circuits. Other factors such as the rise in leakage current
and enlarged impacts of process variations also require extra care [4]. To counteract
these problems and realize complex high-level integration, it is very important to
investigate new circuit techniques suitable for analog and RF design in deep
3
submicron CMOS processes.
In CMOS technology, the switched-capacitor (SC) technique is crucial and the
most popular way to implement accurate analog signal processing functions. By using
the SC technique, circuit parameters (such as gain, zero/pole frequencies) are defined
by ratios of capacitors, which can be precisely set in CMOS processes with accuracy
on the order of 0.1%. Therefore analog functions such as filtering and data conversion
can be implemented more accurately in this way than by other methods which depend
on an accurate definition of absolute resistance and capacitance. This work focuses on
SC circuits in CMOS analog and RF applications, and several new techniques that
offer the potential for significant improvements in both energy efficiency and
performance in deep-submicron CMOS technology are presented.
1.2 Research goals
The low-power and high performance SC techniques addressed in this work are
embodied in the contexts of two instructive design examples, which are a RF
Phase-Locked Loop (PLL) frequency synthesizer prototype implemented in a 180nm
CMOS process and a Delta-Sigma (ΔΣ) Data Converter prototype for audio signal
processing implemented in a 130nm CMOS process. Techniques related to two major
analog circuit functions, which are filtering and data conversion, are investigated and
verified in these important application systems.
PLL frequency synthesizers are critical components in modern electronic systems,
such as wireless transceivers, cable tuners, and high-speed data converters. In
communication applications, PLL frequency synthesizers usually serve as local
4
oscillators for the purpose of frequency translation and channel selection. These
systems usually impose very stringent requirements on the PLLs' performance, and
make their integrated implementation in CMOS technologies a troublesome
procedure. First, due to the inferior performance of the components CMOS offers,
oscillators with performance meeting specification requirements are difficult to
implement compared with those in bipolar or BiCMOS technologies. Second, for a
conventional resistor-capacitor (RC) loop filter, a large capacitor is required and if
integrated on-chip, it takes enormous space and the effectiveness of CMOS will be
reduced dramatically. Another major problem is the reference spurs or periodic jitters
caused by the mismatch between the positive and negative charge pump currents.
This is an inherent problem at the interface between the charge pump and the
conventional loop filter, and this could introduce significant interference to other
channels in wireless communication systems.
Recently, several PLL frequency synthesizers with switched-capacitor (SC) loop
filters have been reported. While some works have shown their effectiveness on the
problems mentioned above, some imperfections still exist. In [5]-[6], with the use of
passive SC loop filters, small on-chip capacitors and low reference spur levels are
accomplished. However, these loop filters do not have a DC pole and the loop
dynamics become Type I, resulting in unfavorable problems. In order to achieve a
Type II SC PLL and keep circuit power consumption within a reasonable level,
existing solutions [7], [8] employ additional continuous-time (CT) active filters to
provide the missing DC pole. However, OTAs or Gm cells in these topology increase
5
power consumption, and more importantly, additional 1/f and thermal noise are
introduced. In order to counteract these problems, a new low-power SC loop filter is
proposed in this work. Compared with conventional RC loop filters, small on-chip
capacitors can be used and reference spurs caused by charge pump current mismatch
are eliminated. Compared with other SC loop filter implementations, low-power
amplifiers are used to maintain its power consumption low. Additionally, 1/f noise of
the active amplifiers can be suppressed by the auto-zero function in the SC circuit.
Experimental results demonstrate that with less on-chip space and lower power
consumption, a PLL implemented with this loop filter achieves comparable
performance to other solutions.
Delta-Sigma (ΔΣ) modulation is a very attractive technique to implement
high-resolution analog-to-digital or digital-to-analog converters in low-cost CMOS
processes, since errors caused by circuit imperfections in signal-bands can be
suppressed by the loop filter employed. It is well-known that the performance of a ΔΣ
ADC can be significantly improved by using a multi-bit internal quantizer. It
enhances loop stability and reduces the sampling frequency compared to
implementations with single-bit quantizers for the same SNR. However, when
designing a ΔΣ ADC with a multi-bit quantizer, a highly-linear feedback DAC
matching the overall ADC accuracy is required, because the feedback signal is
subtracted from the analog input directly and no noise-shaping is carried out. The
feedback DAC then becomes the major bottleneck when designing a multi-bit ΔΣ
ADC, since it is not a trivial task to design a highly-linear (>14bit) DAC in CMOS
6
technologies with the presence of inherent component mismatch. To design a highly
linear multi-bit DAC, many approaches have been proposed to counteract errors
introduced by element mismatches. Data-weighted-averaging (DWA) technique is
most widely used nowadays [9]. However, the DWA technique introduces
signal-dependent distortion or performance loss for certain input levels. This is
known as the in-band tone problem and its influence still depends on the matching of
unit elements [10]-[11].
In this work, we propose to design the ΔΣ feedback DAC in a SC
ratio-independent manner. In addition, ΔΣ modulator topologies suitable for the
ratio-independent DAC are introduced. By using a gain-boosted sub-threshold
inverter as an amplifier, circuit power consumption is kept low. The sensitivity of the
differential DAC output linearity on circuit mismatches is reduced by using
mutually-referred inputs. Moreover, in-band noise is improved since noise increase
introduced by component mismatch in conventional or DWA design is suppressed.
Measurement results from a ΔΣ modulator prototype fabricated in a 130nm CMOS
process demonstrate that the proposed method offers a power- and space-efficient
solution for highly linear data conversions.
1.3 Thesis Orgnization
This thesis is organized in the following manner:
Chapter 2 reviews the CMOS switched-capacitor technique. Circuit blocks and
some general design considerations along with noise issue are presented.
Chapter 3 describes the general theories behind PLL frequency synthesizers. PLL
7
building blocks and implementation issues in conventional architectures are
discussed.
Chapter 4 explains the basic principles of analog-to-digital conversion and
delta-sigma (ΔΣ) modulation. Different ΔΣ topologies are discussed. Stability, noise
issues and techniques to enhance its performance are covered.
In Chapter 5, PLL loop filter structures reported in recent literatures are reviewed.
The low-power active switched-capacitor loop filter is proposed and a PLL frequency
synthesizer is designed based on this loop filter. Measurement results are also
presented.
In Chapter 6, a ratio-independent feedback DAC for ΔΣ ADCs is proposed at the
beginning. In order to reduce its power consumption, a low-power
nonlinearity-suppressed switched-capacitor DAC is further proposed and applied to a
ΔΣ modulator implementation. Prototype measurement results are presented.
Chapter 7 concludes this thesis and future work is discussed.
8
Chapter 2
Switched-Capacitor Circuits
This chapter describes some fundamentals of switched-capacitor (SC) techniques
in CMOS technology. Topics on discrete-time signal basics, circuit building blocks
and design challenges are covered. A simple sample-and-hold stage and a SC
integrator are used to exemplify the analysis methods.
2.1 Discrete-time signal basics
Switched-capacitor techniques are widely used in the design of modern analog
systems. In an essentially analog real world, SC circuits sample continuous-time input
signals and then they are represented and processed in the discrete-time domain. In
some applications, in order to interface with other parts of the system, the
post-processed discrete-time signals are required to be converted back to analog
signals as well. Therefore it's critical to have a basic understanding of the conversion
between continuous-time and discrete-time signals.
2.1.1 Spectra of Discrete-Time Signals
By taking samples of the continuous-time signal at uniform time intervals, a
discrete-time representation of the signal can be obtained. As shown in Figure 2-1 (a)
and (b), x(t) is the continuous-time input signal and x(n) = x(nT) is a discrete-time
9
representation of x(t), where T is the sampling period or the sampling frequency is
fS=1/T.
In order to obtain the spectrum of the sampled signal x(n), its time-domain
expression can be written as
( ) ( ) ( )x n x t s t= i (2-1)
where s(t) is a periodic impulse train or
( ) ( )n
s t t nTδ∞
=−∞
= −∑ . (2-2)
Since multiplication in time-domain corresponds to convolution in frequency-domain,
the spectrum of x(n) can be found as [12]
1 1( ) ( ) ( ) ( 2 2 )2S S
kX f X f S f X j f j k f
Tπ π
π
∞
=−∞
= ⊗ = −∑ i i . (2-3)
The spectra of x(t) and x(n) are illustrated in Figure 2-2. It can be observed that
the sampling process in time-domain leads to periodic spectrum replicas in frequency
Figure 2-1: Sampling and Sample-and-Hold
10
domain. Also, the amplitude is scaled by 1/T. In order to avoid overlapping of
replicated signals in frequency domain (i.e. aliasing) during sampling, the following
condition should be satisfied
S B Bf f f− ≥ or 2S Bf f≥ , (2-4)
where fB is the highest frequency of the input signal. The minimum sampling
frequency required to avoid aliasing is referred to as Nyquist rate.
2.1.2 Sample-and-Hold Response
The discrete-time signal obtained by the sampling operation can be converted
back to a continuous-time signal with a simple holding operation as shown in Figure
2-1 (c). By defining the step function u(t) as
1, ( 0)( )
0, ( 0)t
u tt≥⎧
≡ ⎨ <⎩, (2-5)
the sample-and-hold signal xh(t) can be expressed mathematically to be
[ ]( ) ( ) ( ) ( ( 1) )hn
x t x nT u t nT u t n T∞
=−∞
= − − − +∑ . (2-6)
Figure 2-2: Frequency domain illustration of sampling
11
It can be shown that the spectrum of xh(t) is
( ) ( ) ( )h h SX f H f X f= i , (2-7)
where XS(f) is given by Eq. (2-3) and Hh(f) is
sin( / )( )j fT
Sh
S
e f fH ff
π ππ
−
=i
. (2-8)
The magnitude response of Hh(f) is plotted in Figure 2-3. The holding operation
works as a low-pass filter with the sinc response.
2.2 Building Blocks in Switched-Capacitor Circuits
2.2.1 Sampling Switches
MOSFETs have several favorable properties when used as sampling switches.
First, it has very large off resistance which makes charge conservation possible.
Second, it has reasonable on resistance so that circuit can settle quickly during
amplification phase. Third, there is no offset voltage between the source and drain of
the transistor switch when it's turned on.
A simple sample-and-hold stage with a MOS switch is shown in Figure 2-4.
Figure 2-3: Sample-and-Hold response
12
When a MOS transistor is used as a switch, it usually operates in the triode region.
Ignoring higher-order effects, the behavior of the transistor can be modeled
mathematically as
( ) 212D ox GS TH DS DS
WI C V V V VL
μ ⎡ ⎤= − −⎢ ⎥⎣ ⎦. (2-9)
In the above equation, ID is the drain current. μ is the mobility of charge carriers. Cox
is the gate capacitance per unit area. W and L are the width and length of the
transistor and VTH is its threshold voltage. For 2( )DS GS THV V V− ), the 21 2 DSV term
can be ignored and drain current can be approximated as a linear function of VDS and
the transistor behaves as a voltage-controlled resistor. The on resistance of the switch
is
( )1
on
ox GS TH
R WC V VL
μ=
−. (2-10)
With the equivalent on-resistance known, several considerations can be addressed
when a MOSFET is used as a switch. First, during the on state, the sample-and-hold
circuit shown in Figure 2-4 becomes a low-pass filter. Assuming the clock high
Figure 2-4 MOS sample-and-hold stage
13
voltage is VCLK,H and the maximum input signal is Vin,max, it is straightforward that
the worst case (minimum) bandwidth for the sample-and-hold circuit is
( ), ,max
min,max
12 2
ox CLK H in TH
on H H
WC V V VLf
R C C
μ
π π
− −= = . (2-11)
The above bandwidth should be larger than the maximum frequency of the input
signal.
Moreover, the on resistance of the switch should be small enough to assure
enough settling accuracy. For a single-pole first-order filter, its step response can be
found to be
( )( ) 1 tout stepV t V e τ−= − , (2-12)
where on HR Cτ = is the time constant of the sample-and-hold circuit, and Vstep is the
size of the voltage step at the input. From Eq. (2-12), the time required for the circuit
to settle to within a specific value can be found. For 1% accuracy, 4.6t τ≥ should be
satisfied. Assuming the sampling phase takes half of a sampling period, the
requirement for 1% settling accuracy can be rewritten as
min
1 4.62 2Sf fπ
≥ . (2-13)
Equation (2-13) can be simplified as min 1.46 Sf f≥ . Compared with Eq. (2-11), since
fS should be at least two times the input maximum frequency to avoid aliasing, the
settling accuracy requirement is usually more stringent than the simple bandwidth
requirement above.
Another concern on the MOS switch is related to precision issues. In Figure 2-4,
14
when the MOSFET is turned on, some charge is stored in the channel capacitance and
it can be denoted by
( ),ch ox CLK H in THQ WLC V V V= − − . (2-14)
When the MOSFET is turned off, with fast transition assumed, half of the charge will
flow onto the holding capacitor CH. This is called the charge injection problem and it
causes an output voltage error which equals
( )2
ox DD in TH
H
WLC V V VV
C− −
Δ = . (2-15)
Equation (2-15) indicates that ΔV is linearly related to Vin, and this introduces
gain error to the circuit. But this is obtained under the assumption that VTH is a
constant. In the real case, VTH changes with the variations of the transistor's
source-bulk voltage VSB and the relationship between the two is a nonlinear process
which can be modeled as
( )0 2 2TH TH F SB FV V Vγ= + Φ + − Φ , (2-16)
where VTH0 is the threshold voltage when VSB=0, γ is the body effect coefficient and
ФF is the difference between the built-in Fermi potential of the substrate and intrinsic
silicon. For a NMOS switch, assume the substrate is tied to the power ground, and
thus VSB equals approximately Vin. Therefore, ΔV is related to Vin nonlinearly and
this results in distortion for the circuit.
In addition to the charge injection problem mentioned above, there is another
phenomenon called clock feed-through which can challenge the precision of
switched-capacitor circuit. Due to the gate-drain or gate-source overlap capacitance
15
Cov in a transistor, the clock signal will be coupled onto the holding capacitor and the
error can be expressed as
,ov
CLK Hov H
CV VC C
Δ =+
. (2-17)
The effect of charge injection and clock feed-through should be investigated
carefully in specific applications, and proper measures should be taken to counteract
these problems. Otherwise, circuit performance could be degraded dramatically. A
popular method of suppressing both the charge injection and clock feed-through
effects are illustrated in Figure 2-5 [13], where a half-sized dummy switch is used. It
can be shown that ideally the charge injected from T1 can be absorbed by T2 and the
error caused by clock feed-through can also be canceled. But in real world, the
assumption that the T1 channel charge is split equally in the two directions does not
hold generally. However, it can still reduce the output error to less than about
one-fifth the value it would have without it.
Differential configuration can also relieve the charge injection problem by
Figure 2-5 Charge injection and clock feed-through suppression by dummy switch
16
cancelling offset and suppressing the even order distortions. Other techniques such as
using complementary transmission gate, bottom-plate sampling technique [14], and
bootstrapping technique are also widely adopted.
2.2.2 Capacitors
The low-cost single-poly CMOS processes employed to implement circuit
designs in this work offer Metal-Insulator-Metal (MIM) options to construct relatively
accurate on chip capacitors. The cross section of a dual MIM capacitor is depicted in
Figure 2-6. In this structure, the top plate of the formed capacitor is Thin Metal 2 and
the bottom plate is Thin Metal 1 and Metal 2 (M2) which are connected together by
vias and Metal 1 (M1). It is important to indentify the two plates in applications that
are sensitive to parasitic effects. Distinct difference in parasitic capacitance between
the two plates is present, since a substantial capacitance exists between the bottom
Figure 2-6 Cross section of a MIM capacitor
17
plate M2 and substrate (signal ground) but the parasitic capacitance of the top plate is
mainly contributed by the interconnect capacitance. By using this dual MIM capacitor
shown in Figure 2-6, capacitance density and thus space-effectiveness are
significantly improved.
Several non-idealities in capacitors introduce noise and distortion to SC circuits.
The first issue is capacitor mismatch originated from linear gradients which arise
from non-uniform dielectric growth conditions and from random variations.
A charge redistribution DAC consisting of unit capacitors of the same nominal
size can be used to demonstrate the influence of linear gradients. As shown in Figure
2-7, during the reset phase, all the capacitors are discharged to zero. During the output
phase, assuming a number of j capacitors are connected to Vref according to the input
thermometer code and then the output voltage will be jVref/N if all the capacitors are
Figure 2-7 A charge redistribution DAC and its equivalent circuit during output phase
18
identical. With the presence of linear gradients effect, the capacitor array will be
valued as C1, C2+ΔC, … , CN+(N-1)ΔC and the output voltage in turn will be
( )
( )
( )
( )
1
01
0
12
12
j
refi
out refN
i
j jC i C V jC CV V
N NC i C NC C
−
=−
=
−+ Δ + Δ= =
−+ Δ + Δ
∑
∑. (2-18)
Differential nonlinearity (DNL) can be found as
( )1
12
12
refj j j ref
Nj C VDNL V V V N N NC C
+
−⎛ ⎞− Δ⎜ ⎟⎝ ⎠= − − =
−+ Δ
. (2-19)
Integral nonlinearity (INL) can be found as
( )1 2
2
refj ref j
Vj N j CjINL V V NN NC C
− Δ= − =
−+ Δ
. (2-20)
In addition to mismatch caused by process linear gradients, in reality capacitors
also exhibit random mismatch originating from dimension variations during
fabrication. The percentage mismatch for identical adjacent MIM capacitors with the
same orientation and at the same voltage can be modeled as
22 2
2 2WA LMM MM
WL W L= + + %, (2-21)
where W and L is the width and length of the capacitor and MA, MW and ML are the
mismatch parameters. Though Eq. (2-21) indicates that increasing capacitor
dimension can increase the matching, gradient effect becomes more significant in
large capacitors and mismatch can deteriorate when the dimension reach a certain size
19
[15]. For large capacitors, unit-size capacitors laid out in the common-centroid
manner can be employed to achieve good matching.
The second issue with capacitors is their voltage dependence [16]. With αi as the
ith-order voltage coefficient of a capacitor, its capacitance can be modeled as
( )20 1 21 ...dQC C V V
dVα α= = + + + . (2-22)
This voltage dependence introduces nonlinearities into the circuits. In most cases,
coefficients with orders higher than two are much smaller and negligible. In
differential applications, assume an increase of voltage from 0 to V1 happened on the
capacitor in the positive half circuit and a decrease of voltage from 0 to –V1 is
accompanied in the negative half, the amount of charge changed on the two
capacitors are expressed as
( )1 2 2 31 21 0 1 2 0 1 0 1 0 10
12 3
VQ C V V dV C V C V C Vα αα αΔ ≈ + + = + +∫ (2-23)
and
( )1 2 2 31 22 0 1 2 0 1 0 1 0 10
12 3
VQ C V V dV C V C V C Vα αα α
−Δ ≈ + + = − + −∫ , (2-24)
respectively. Therefore when the output is taken as ΔQ1-ΔQ2, odd order coefficients in
Eq. (2-22) can be suppressed and the effect of α2 is dominant.
2.2.3 Amplifiers
In switched-capacitor technique, amplifiers play a critical rule in defining circuit's
precision, speed and power consumption. With capacitive loads employed in SC
circuits, the low-output-impedance buffer in an operational amplifier (opamp) is
20
usually omitted and operational-transconductance-amplifier (OTA) is thus formed.
Though different structures can be used to implement an OTA, the same model with
parameters such as DC gain, unity gain frequency and slew rate can be used to
describe the performance of a conventional OTA. Some insights on the performance
of the SC circuit can also be obtained with these parameters.
If an OTA is properly compensated, it exhibits a simple first-order single-pole
response at frequencies of interest. With ωp1 as the dominant pole, the transfer
function of an OTA can be modeled as
0
1
( )1 p
AA ss ω
=+
, (2-25)
where A0 is the finite DC gain of the OTA and s is the complex frequency. The unity
gain frequency ωta of the OTA can be calculated by setting the magnitude of Eq. (2-25)
to 1 and we have
0 1ta pAω ω≈ . (2-26)
The effects of finite DC gain and unity gain frequency of the OTA on the
performance of a SC integrator shown in Figure 2-8 are discussed in detail below. Φ1
and Φ2 are non-overlapping clocks and Φ1a and Φ2a are simply the advanced version
of them. This arrangement can reduce the effect of switch charge injection. It can be
derived that with an infinite OTA DC gain, the transfer function of the circuit is
11
12
( )( )( ) 1
out
in
V z C zH zV z C z
−
−= =−
. (2-27)
On the other hand, if the finite gain of A0 is accounted for, the integrator becomes
21
leaky and the gain is also altered. The transfer function becomes
11
12
( )( )( ) 1
out
in
V z C gzH zV z C zα
−
−= =−
, (2-28)
where g and α are the actual gain and the leakage factor, respectively, shown below
0
0 1 21Ag
A C C=
+ +, (2-29)
0
0 1 2
11A
A C Cα +=
+ +. (2-30)
It can be observed that in a SC filter circuit, the finite OTA DC gain not only
affects the accuracy of circuit coefficients (magnitude error), it also changes the
locations of the poles or zeros (phase error) of the filter. Depending on applications,
the DC gain of an OTA in SC circuits typically ranges from 40dB to 90dB.
As mentioned in Section 2.2.1, a single-pole first-order filter has an exponential
step response. In order to assure a certain settling accuracy, the OTA should have a
unity gain bandwidth large enough. The small-signal equivalent circuit of the
integrator in Figure 2-8 during the amplification phase or Phase 2 is illustrated in
Figure 2-8 A typical switched-capacitor integrator
22
Figure 2-9. Two resistors RS1 and RS2 are used to model the resistance of the MOS
switches. gm is the transconductance of the OTA. By applying an input signal Vin to
the integrator, the current i can be found as
( )1 2 11in X
S S
V ViR R sC
−=
+ +. (2-31)
Considering the fact that
m Xi g V= , (2-32)
VX is found to be
( )1
1 1 2
/1 1/
in mX
m S S
V sC gVsC g R R
=+ + +
. (2-33)
Then the transfer functions of the capacitor voltages are
1 11
C
in
VV sτ
=+
, (2-34)
2 1
2
11
C
in
V CV C sτ
=+
, (2-35)
where
Figure 2-9 Equivalent circuit of Figure 2-8 in Phase 2
23
( )1 1 21 m S SC g R Rτ = + + . (2-36)
The closed-loop -3dB bandwidth is
( )( )31 1 2
11
mdB
m S S
gC g R R
ω− =+ +
. (2-37)
The settling error can be simply denoted as
3Int dBTe ωδ −−= , (2-38)
where TInt is the duration of the integration phase and it's directly related to sampling
frequency fS of the integrator. If TInt is taken as 1/(2fS), f-3dB should be at least 2.23
times fS to achieve 0.1% settling accuracy. The sampling frequency and the size of C1
are usually selected according to specifications of circuit performance. It is obvious
that to achieve good settling accuracy, an adequate gm or unity gain frequency
( ta m LOADg Cω = ) of the OTA is required. Also the resistance of the switches should
be as small as possible.
In order to assure fast settling, slew rate limiting should be avoided. Slew rate
(SR) is the maximum rate that the output voltage can change, or mathematically
maxmax
LOADout
LOAD
IdVSRdt C
= = . (2-39)
For the output voltage response described in Eq. (2-12), its maximum slope is
maxout STEPdV V
dt τ= . (2-40)
Thus, the output current that an OTA can provide should statisfy
STEPLOAD LOAD
VI Cτ
≥ (2-41)
24
and then no slew rate limiting would occur.
The above analysis focuses on the effects of the magnitude response of circuits
and the OTA is approximated as a first-order single pole system. However, in reality,
the phase response is more complicated and it has a strong influence on circuit
behavior. The block diagram of a negative-feedback system is shown in Figure 2-10.
Its closed-loop transfer function is
( )( )1 ( )CL
H sH sH s β
=+
. (2-42)
Its loop gain is
( ) ( )OLH s H sβ= . (2-43)
The magnitude and phase responses of the loop gain for a two-pole system are
depicted in Figure 2-11. To assure system stability, loop gain magnitude should drop
to below unity at a frequency for which its phase shift is less than 180 degree.
Defining phase margin (PM) as
( )0 180OLPM H ω= + ° , (2-44)
where ω0 is the gain crossover frequency, at which the magnitude of loop gain is unity.
Phase margin is an important parameter to evaluate system stability, and moreover,
Figure 2-10 Block diagram for a basic negative-feedback system
25
the transient response for switched-capacitor circuits. To achieve small ringing and
fast settling at the same time, a phase margin of around 60 degree is usually selected.
2.3 Noise in Switched-Capacitor Circuits
2.3.1 KTC noise
The equivalent circuit during sampling phase for the sample and hold circuit
shown in Figure 2-4 is illustrated in Figure 2-12. Since the power spectral density of
the resistor thermal noise is 4kTR (k is Boltzmann Constant and T is the absolute
temperature), the output noise power of the circuit is
Figure 2-11 Bode plots of loop gain for a two-pole system
26
2
2 2 2 20 0
1 441 4 1n
kTR kTP kTR df dfsRC R C f Cπ
∞ ∞= = =
+ +∫ ∫ . (2-45)
This is known as the KTC noise or sampling noise. This result implies that the output
noise is independent of the value of R. For a given temperature, kT/C noise can be
decreased only by increasing C. In switched capacitor circuits, the bandwidth of
thermal noise is usually much larger than the sampling frequency. Therefore, the
thermal noise is under-sampled and heavily aliased. For each sampling bandwidth fS,
the noise power is kT/C. Since the spectrum of the folded thermal noise is very nearly
white [17], [18], the single-sided sampled thermal noise power spectral density is
2( )S
kTS fCf
= . (2-46)
2.3.2 Thermal noise of a switched-capacitor integrator
For the integrator shown in Figure 2-8, during the sampling phase, the thermal
noise power on C1 is
, 11
nkTPCΦ = . (2-47)
During the integration phase, as illustrated in Figure 2-9, the integrator can be
Figure 2-12 Sample-and-hold equivalent circuit during sampling phase
27
approximated as a lowpass filter with a -3dB bandwidth shown in Eq. (3-27). For a
first-order filter with -3dB bandwidth of ω-3dB and DC gain of G0, its transfer function
can be expressed as
0
3
( )1 dB
GH ss ω−
=+
. (2-48)
Its equivalent noise bandwidth is
23 3
3200
( )12 2 2 2 4
dB dBeq dB
H jf d f
Gω ω ωπ πω
π π∞
− −−= = = =∫ . (2-49)
With gm as the trans-conductance of the input transistor, the power spectral density of
a conventional OTA is approximately [19]
163OTA
m
kTSg
≈ . (2-50)
The noise power on C1 during the integration phase is thus
( ) 3, 2 1 2
1643 4
dBn S S
m
kTP kT R Rg
ω−Φ
⎛ ⎞= + +⎜ ⎟⎝ ⎠
, (2-51)
where ω-3dB is given by Eq. (2-37).
The input-referred thermal noise power of the switched-capacitor integrator Pn is
then given by
( ), 1 , 21 1 2
2 1 611n n n
m S S
kTP P PC g R RΦ Φ
⎛ ⎞= + = +⎜ ⎟⎜ ⎟+ +⎝ ⎠
. (2-52)
Since ( )1 20 m S Sg R R< + < ∞ , we have
1 12 2.33nkT C P kT C< < . (2-53)
The relationship between Pn and gm(RS1+RS2) is plotted in Figure 2-13. Though a
28
large gm(RS1+RS2) gives a relatively small noise power, this does not indicate that the
large switch on-resistance is a good circuit design practice. When large on-resistance
switches are used, gm should be increased accordingly in order to achieve comparable
circuit speed. This would result in a significant increase of circuit power consumption.
This can also be explained mathematically below.
Equation (2-52) can be rearranged as
( )( )31 2
2 7 6dBn m S S
m
kTP g R Rgω−= + + , (2-54)
and gm can be solved as
Figure 2-13 Input referred integrator thermal noise power versus gm(RS1+RS2)
29
( )3
3 1 2
73 2
dBm
n dB S S
kTgP kT R R
ωω
−
−
=− +
. (2-55)
This result implies that for a given settling time (determined by ω-3dB) and noise
constraint Pn, the solution to minimize gm or power consumption is the one that
minimize the switch resistance RS1+RS2.
The above analysis only accounts for the noise on C1 for each integration period.
The opamp noise during the sampling phase is not included. However, in reality, the
opamp noise does contribute to the total output noise. For an opamp circuit with
capacitive feedback coefficient β=C2/(C1+C2) and load CL=C3+C1C2/(C1+C2) as
shown in Figure 2-14, its transfer function is
( ) 1 1
1 L
m
H sCs
gβ
β
≈⎛ ⎞
+ ⎜ ⎟⎝ ⎠
. (2-56)
Using Eq. (2-50) and (2-56), the output noise for the circuit in Figure 2-14 is thus
2
, ,1
16 1/ 43 4 3n op out
m L
kT kTPg C
βτ β
⎛ ⎞⎛ ⎞= =⎜ ⎟⎜ ⎟
⎝ ⎠⎝ ⎠. (2-57)
When the integrator is in the sampling phase, the opamp forms a circuit similar to the
Figure 2-14 Opamp feedback circuit
30
one in Figure 2-14 with C1=0. Therefore its output noise power is simply
, , 143n op
L
kTPCΦ = . (2-58)
This noise is under sampled at the integrator output and has a nearly white PSD. Its
power over [0, fS] is simply Eq. (2-58).
The integrator can then be modeled as shown in Figure 2-15 with a noiseless
integrator and two white noise sources, which are mathematically described by Eq.
(2-52) and (2-58), at the input and output, respectively.
Figure 2-15 Integrator noise model
31
Chapter 3
PLL Frequency Synthesizer
This chapter presents the theoretical analysis of PLL-based frequency
synthesizers. Linearized small-signal phase loop transfer function and basic building
blocks are included. Implementation issues and noise considerations are discussed.
3.1 PLL basics
The concept of phase-locked loops (PLLs) was first introduced by H. de
Bellescize in 1932 [20] and it is soon widely used in the areas of televisions and FM
radio. Nowadays, PLLs have become critical components in various electronic
systems for their versatility. In super-heterodyne transceivers, the local oscillator
signal for frequency translation and channel selection comes from a PLL-based
frequency synthesizer. For high speed micro-processing and data conversion systems,
Figure 3-1: Phase-locked loop block diagram
32
generation and recovery of clock signals also relies on PLLs. Though the basic
principle behind PLLs remains nearly the same, with the fast development of modern
semiconductor technology, their implementation with compatible architectures for
diverse applications is still an area of active research.
3.1.1 Type I PLL
A PLL synchronizes the output phase of a tunable oscillator with the phase of a
reference clock, by means of negative feedback. Generally, it consists of a phase
detector, a low-pass loop filter, and a voltage-controlled-oscillator (VCO). The basic
PLL architecture is depicted in Figure 3-1.
A PLL is a phase-processing system and it should be analyzed in the phase
domain. The phase detector compares the phase difference between the reference
input and the feedback output signals, and it produces an output in terms of current or
voltage which is usually proportional to the phase difference. The output from the
phase detector is filtered and then used to drive the VCO in order to reduce the phase
difference. Ignoring the nonlinearities in the VCO, it is straightforward that a VCO is
an integrator in phase domain and its continuous-time transfer function is
( )VCO VCOH s K s= , (3-1)
where KVCO is the sensitivity of the VCO with a unit of Mrad/s/V.
Assuming that a simple first-order low-pass filter with -3dB bandwidth of ωLF is
employed as the loop filter in Figure 3-1 and the phase detector has a gain of KPD, the
loop gain of the PLL can be obtained as
33
( )( )
1PD VCO
OLLF
K KH ss s ω
=+
. (3-2)
Since Eq. (3-2) has only one pole at origin, this PLL is named as Type I. Another pole
exists at s=ωLF and the loop gain magnitude and phase response is plotted in Figure
3-2. In a Type I PLL, phase margin can be adjusted easily. The phase margin Фm of
Eq. (3-2) is simply
190 tan cm
LF
ωω
−Φ = − , (3-3)
where ωc is the crossover frequency or the open-loop unity gain frequency and it is
given by
Figure 3-2: Magnitude and phase response of the Type I PLL loop gain
34
2 2 2 242
LF LF PD VCO LFc
K Kω ω ωω
+ −= . (3-4)
With fixed ωc, increasing ωLF results in a larger phase margin.
The closed-loop transfer function of this Type I PLL can be written as
2
( )( )1 ( )
OL PD VCOCL
OL PD VCO LF
H s K KH sH s K K s s ω
= =+ + +
. (3-5)
Equation (3-5) can be rearranged as
2
2 2( )2
nCL
n n
H ss s
ωζω ω
=+ +
, (3-6)
where ωn and ζ are the natural frequency and the damping ratio respectively and they
are given by
n LF PD VCOK Kω ω= , (3-7)
12
LF
PD VCOK Kωζ = . (3-8)
The step response of this system can be overdamped, critically damped, or
underdamped, depending on the value of ζ. For 1ζ ≤ , the step response approaches
its final value exponentially with a time constant ( )1 nζω , thus the settling speed of
the PLL is directly related to
2LF
nωζω = . (3-9)
Though a large ωLF decreases the settling time of the system, it allows more
high-frequency components pass through the loop filter and compromises system
performance. This is a problem rising from the direct coupling of the above loop
35
parameters.
Another observation on Type I PLL is that a non-zero phase error between the
input and output is required to drive the VCO to the correct frequency. To examine
this problem, the input to phase error (Φin-Φout) transfer function can be derived as
2
2
2( )2
in out ne
in n n
s sH ss s
ζωζω ω
Φ −Φ += =
Φ + +. (3-10)
Assume an input frequency step of Δωinu(t) (where u(t) is the step function) occurs,
the steady-state phase error can be found as
( ) 20 0lim ( ) lim ( )in in
in out t e es sPD VCO
s s s H ss K Kω ω
=∞ → →
Δ ΔΦ −Φ = Φ = = . (3-11)
This result reveals that the steady-state phase error cannot be zero in this system
and it is directly related to KPD and KVCO, or the loop bandwidth. Generally, a
steady-state phase error of zero is preferred. Along with the limited lock-in range
problem [21], [22], i.e. the loop can acquire lock only if the difference between the
input and output is on the order of ωLF, Type-I PLL is not frequently used.
3.1.2 Type II PLL
Zero steady-state phase error can be achieved using the Type II PLL or the
charge pump PLL. A simple charge pump PLL with a first-order passive loop filter is
illustrated in Figure 3-3. A divider with division ratio N is also included to illustrate a
more general frequency synthesizer. The impedance of the loop filter can be found as
1 1
1
1( )LFsR CZ ssC+
= . (3-12)
With a charge pump output current ICP, the loop gain for this PLL is
36
( )1 12
1
1( )
2VCOCP
OL
K sR CIH sNs Cπ+
= . (3-13)
Though a first-order loop filter is used, since the VCO introduces another pole at
origin, this PLL is a second-order system. It is called the Type II PLL because there
are two poles at the origin. In practical designs, higher-order filters may be used to
suppress VCO control voltage ripples. Similarly, the PLL is always one-order higher
than the loop filter.
A zero
( )1 11z R Cω = (3-14)
is introduced by R1 and it serves for stabilizing purpose. Without the zero, the loop is
obviously unstable due to the two origin poles. Let KCP=ICP/2π, K=KCPKVCOR1/N, the
loop gain is rewritten as
( )2
1( ) z
OLz
K sH s
sω
ω+
= . (3-15)
The magnitude and phase response of Eq. (3-15) is plotted in Figure 3-4. The
zero stabilizes the loop by providing a positive phase shift. The phase margin Фm is
Figure 3-3: Second order Type II PLL block diagram
37
simply
1tan cm
z
ωω
−Φ = , (3-16)
and the crossover frequency ωc is given by
2 2 242
zc
K K K ωω
+ += . (3-17)
At the crossover frequency the phase shift is Фc, and we have
2sin c zc
c z c
K Kω ωω ω ω
Φ = − = − , (3-18)
Figure 3-4: Magnitude and phase response of the Type II PLL loop gain
38
180m cΦ = +Φ , (3-19)
With the use of the above two equations ωc can also be expressed as
sinc mKω = Φ . (3-20)
The closed-loop gain of this PLL can be found as
2
( )( ) zCL
z
K sH s Ns Ks K
ωω
+=
+ +. (3-21)
Equation (3-21) can be rearranged in the following form
2
2 2
2( )2
n nCL
n n
sH s Ns s
ζω ωζω ω
+=
+ +, (3-22)
where the natural frequency ωn and the damping factor ζ are
n zKω ω= , (3-23)
12 z
Kζω
= , (3-24)
By using Eq. (3-16) and Eq. (3-20), the above equations can be rewritten as
cosn c mω ω= Φ , (3-25)
sin12 cos
m
m
ζ Φ=
Φ. (3-26)
The closed-loop -3dB frequency for the loop can be found as
( ) ( )22 23 2 1 2 1 1dB nω ω ζ ζ− = + + + + . (3-27)
Using Eq. (3-25) and Eq. (3-26), the ratio ω-3dB/ωc versus damping factor is found
and plotted in Figure 3-5. With a reasonable damping factor, 3dB cω ω− ≈ . Thus the
39
open loop crossover frequency is referred to as the PLL bandwidth in future
discussion.
With an input frequency step of Δωu(t)/N occurs, the PLL output response is
( ) ( )out CLs H sNsωω Δ
Δ = . (3-28)
The time-domain step response of the PLL is found as shown in Eq. (3-29) using
inverse Laplace transformation on Eq. (3-28).
( ) ( ) ( )
( ) ( )
( ) ( ) ( )
2 2
2
2 2
2
( ) 1 cos 1 sin 1 0 11
( ) ( ) 1 1 1
( ) 1 cosh 1 sinh 1 11
n
n
n
tn n
tout n
tn n
u t e t t
t u t e t
u t e t t
ζω
ω
ζω
ζω ω ζ ω ζ ζζ
ω ω ω ζ
ζω ω ζ ω ζ ζζ
−
−
−
⎧ ⎧ ⎫⎡ ⎤⎪ ⎪⎪Δ − − − − < <⎢ ⎥⎨ ⎬⎪ −⎢ ⎥⎪ ⎪⎣ ⎦⎩ ⎭⎪⎪ ⎡ ⎤Δ = Δ − − =⎨ ⎣ ⎦⎪
⎧ ⎫⎡ ⎤⎪ ⎪ ⎪Δ − − − − >⎢ ⎥⎪ ⎨ ⎬−⎢ ⎥⎪ ⎪ ⎪⎣ ⎦⎩ ⎭⎩
(3-29)
The response is also plotted in Figure 3-6 for different damping factors. For most
practical designs, 0 1ζ< < . The first line of Eq. (3-29) can be rewritten as
( )1 2 2
2
1( ) ( ) 1 sin sin 1 11
ntout nt u t e tζωω ω ζ ω ζ
ζ− −
⎧ ⎫⎪ ⎪⎡ ⎤Δ = Δ − − − −⎨ ⎬⎢ ⎥⎣ ⎦−⎪ ⎪⎩ ⎭. (3-30)
Equation (3-30) indicates that the step response settles with a time constant
1/(ζωn) or 4πN/(ICPR1KVCO) and it also contains a decaying sinusoidal component.
Compared with the Type I PLL whose settling speed is strongly coupled with ωLF
only, the locking time of Type II PLL depends on multiple factors. It is clear that the
second term in Eq. (3-30) has a maximum value of 21/ 1 ζ− . Then the locking time
for a specific relative settling accuracy ε is
40
( )2ln 1lock
n
Tε ζ
ζω
−= . (3-31)
Figure 3-6: Time-domain output frequency response of a second-order Type II PLL
Figure 3-5: The ratio ω-3dB/ωc versus damping factor
41
The second-order Type II PLL is infrequently used because of large VCO control
voltage ripples generated by the loop filter. In order to solve this problem, one or
more additional poles in the loop filter are usually present in a practical design [23] as
shown in Figure 3-7 and a third- or higher order PLL is formed. The analysis of a
third-order Type II PLL (with R3=0 and C3=0 in Figure 3-7) is presented below and
design insights for higher-order systems can be obtained similarly.
The impedance of the loop filter can be found as
( ) ( )1 1 1 1
1 221 1 21 2
1 2
1 1( )11
zLF
p z
sR C s R CZ sC Cs sR C Cs s C C
C C
ωω ω
+ += =
+⎛ ⎞ ++ +⎜ ⎟+⎝ ⎠
, (3-32)
where ωz=1/(R1C1). Let n=(C1+C2)/C2, we have
( ) ( )2 1 2 2 1 1p zC C C R C nω ω= + = . (3-33)
Let K=KCPKVCOR1/N, the loop gain for this third-order PLL is
( )( )2
2
11( )1
zOL
z p
K snH sn s s
ωω ω
+−=
+. (3-34)
The bandwidth of a third-order Type II PLL is
Figure 3-7: Fourth order Type II PLL block diagram
42
12
1
cos(tan ) 1sin(tan )
c pc
c z
nKn
ω ωω
ω ω
−
−
−= . (3-35)
The loop gain phase margin can be found as
( ) ( )1 12tan tanm c z c pω ω ω ω− −Φ = − . (3-36)
By setting
0m
c
ddωΦ
= , (3-37)
the condition for the maximum phase margin can be found as
2c p z znω ω ω ω= = ⋅ . (3-38)
The maximum phase margin is
1,max
1tan2mn
n− −
Φ = . (3-39)
and the relationship between the maximum phase margin and n is plotted in Figure
3-8. In practice, (n-1) or C1/C2 is usually larger than 10 to allow sufficient phase
margin.
Figure 3-8: Maximum phase margin versus n
43
When Eq. (3-38) is satisfied the closed-loop transfer function of the PLL can be
found as
( ) ( )( )( )
( )( )2 32 3
max 2 22 2
2 1( )
21m
n nc cCL
n n nc c c
sN n sH s Ns s ss s n s
ζ ω ωω ωω ζω ωω ω ω
Φ
+ ++= =
+ + ++ + − +, (3-40)
where the damping factor ζ and the natural frequency ωn are
12
nζ −= , (3-41)
n cω ω= . (3-42)
The criterion for stability of the third-order Type II PLL is found as [23], [24]
( ) ( )( ) ( )( )
2
2 2
4 12 1
2 1 2 1 1
z ref
z ref z ref
n
n nref z ref
eK nn e e n n
π ω ω
π ω ω π ω ω
πω π ω ω
−
− −
+−<
+ + − −, (3-43)
where ωref is the input reference frequency. Under the maximum phase margin
condition, the loop bandwidth is reduced to
1c
nKn
ω −= . (3-44)
By using Eq. (3-38) and Eq. (3-44), Equation (3-43) can be rewritten as
( )( ) ( )2 22
22 1 112 2 4 1 0
nnnc c
ref ref
e ne enn
πππω ωπ π
ω ω
−−−
− −⎛ ⎞ ⎛ ⎞++ − + <⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠. (3-45)
A limit for the ratio ωc/ωref exists to assure a stable system. For the sake of
stability, loop bandwidth should be small enough compared with the input reference
frequency. The limit is plotted against n in Figure 3-9. If the ratio ωc/ωref falls below
the curve, then the loop is stable. It can be observed that the limit does not vary much
44
for large n. In practice, adding a safety margin accounting for parameter variations
and loop delay, a commonly used rule-of-thumb is ωc<ωref/10.
In PLLs, the phase detector and VCO may be highly nonlinear and the behavior
of the system will differ from the above liberalized model. However, for loop
bandwidth less than 1/10 of the reference frequency, it is good enough. Behavior
modeling and simulation can be carried out in order to investigate nonlinear issues of
a PLL [25]-[29]. Furthermore, nonlinear difference equations can be used to model
the dynamics for PLLs [30]-[34].
3.2 PLL Building Blocks
3.2.1 Phase/frequency detector
A phase detector senses the phase difference of the two inputs and gives an
output signal related to the difference. A simple phase detector example is the
exclusive OR (XOR) gate. The inputs and output of an XOR gate is plotted in Figure
3-9. The duration of the output pulse or the average output is proportional to the
Figure 3-9: XOR gate inputs and output Figure 3-9: Maximum ωc/ωref versus n
45
phase difference of the inputs. Though a XOR phase detector functions well when the
frequencies of the two inputs are very close to each other, due to its combinational
logic nature, the output does not contain any information about frequency difference.
This problem can limit the lock-in range of a PLL. It has been studied extensively that
the lock-in range for a simple Type I PLL is on the order of ωLF. If the frequency
difference of the inputs is larger than this range, the loop cannot acquire lock.
Because frequency is related to phase linearly, the transfer functions derived in
the previous section also applies to frequency. Therefore if a device has the ability to
sense both the phase and frequency difference of its inputs, it can help the loop
acquire lock in a much larger range, i.e., when the frequency difference is large, the
difference decreases due to the frequency feedback mechanism and when the
frequency difference is small, phase feedback mechanism is involved and the loop
finally locks. The lock-in range can be expanded to the tuning range of the VCO.
Such a device is called a phase/frequency detector (PFD) and its implementation and
input/output signal waveform are illustrated in Figure 3-11, where fref is the input
Figure 3-10: The inputs and output of an XOR gate
46
reference frequency of the PLL and fdiv is the divided output signal from the VCO.
The reset pulses (introduced by the delay block) are necessary in order to eliminate
the dead zone problem caused by the finite rising and falling time of clocks,
otherwise the linearity of the PFD would be compromised.
The PFD is an edge triggered circuit and its principle can be described by the
state machine diagram in Figure 3-12. When the rising edge of fref leads that of the fdiv,
there is an Up pulse at the PFD output. Down pulse is generated when the rising edge
fdiv leads. These pulses drive the charge pump to output currents with corresponding
polarities.
Figure 3-11: Implementation of a PFD
Figure 3-12: State machine diagram for the PFD
47
3.2.2 Charge Pump
A charge pump switches two complementary current sources based on the logical
outputs from the PFD. The conceptual schematic for a current steering [35] charge
pump is illustrated in Figure 3-13. Switching in drains in this configuration offers fast
transient response. The charge pump current sees the loop filter whose impedance is
Zlf and the VCO control voltage VCtrl is formed by the filtered current pulses. Though
the charge pump can be implemented with Up and Down switches only, the Up
and Down switches can reduce the transient current glitches [35] which undermine
the PLL performance because they directly contribute to ripples on the VCtrl. The
timing mismatch between Up and Down clocks can also disturb the control
voltage and cause performance degradation. To suppress this effect, the clock aligning
circuit shown in Figure 3-14 built with XOR gates can be used. Auxiliary techniques
can be employed to improve current matching or reduce non-perfections like charge
injection and charge sharing. [35]-[39]
Figure 3-13: Principle of charge pump with loop filter
48
3.2.3 Programmable Divider
The most widely used pulse-swallow programmable frequency divider is shown
in Figure 3-15. It consists of a high-speed dual-modulus prescaler and two
programmable counters. The division ratio is (P-1) for A times. Then the modulus
control signal changes and the division ratio is set to P for the remaining (M-A) times.
Thus the final division ratio is
( ) ( )1N A P M A P MP A= − + − = − . (3-46)
Figure 3-14: Clock aligning circuit
Figure 3-15: Block diagram of the divider
49
With different M and A programmed, different N can be obtained. Different integer
division ratio can be controlled dynamically by a digital delta-sigma modulator and
fractional-N PLL can be achieved.
When a phase signal passes through the divider, the divider down-samples the
signal, and the relationship between the input and output phase signal is
( ) ( )1out in Sk kT
Nθ θ= , (3-47)
where k is the output sequence index and TS is 1/fdiv.
3.2.4 Voltage Controlled Oscillator
LC oscillators are the primary choice for high-frequency low-noise applications.
The most common configuration called the negative-gm oscillator is illustrated in
Figure 3-16, where the cross-coupled transistors are shown separately. R is the
equivalent parallel resistance of each LC tank. To reveal the principle of this circuit,
ignoring channel-length modulation and body effect, the small signal equivalent
circuit of the cross-coupled transistors is shown in Figure 3-17, where VX is an
external voltage source added to calculate the input impedance seen at the drains of
the two transistors. Examine the voltages and currents and assuming gm1=gm2=gm, we
have
1 1 2 2X m mI g V g V= − = , (3-48)
1 2XV V V= − , (3-49)
( )1 21 1 2in X X m m mR V I g g g= = − + = − . (3-50)
50
Therefore, a negative trans-conductance/resistance is generated by the cross-coupled
transistors. It can be used to cancel the positive resistance in the circuit and an
oscillator can be obtained.
A CMOS on-chip inductor can be modeled by the circuit shown in Figure 3-18
where RLS and RLP are the equivalent serial and parallel resistance, and CLS and CLP
are the equivalent serial and parallel capacitance, respectively.
Decomposing circuit elements with their proper models, the oscillator equivalent
Figure 3-16: Toplology of the negtive-gm LC oscillator
Figure 3-17: Equivalent circuit for the cross-coupled transistors
51
circuit is given in Figure 3-19, where CL=CLS+CLP, CV is the capacitance of the
varactor and RC is its serial resistance. CP is all other capacitance which consists of
the parasitic capacitance of the transistors and the oscillator load. Ro is the finite
resistance of a transistor.
In order to simplify analysis, the RLC network transformation equation is applied
to find out the equivalent parallel resistance RLSP of RLS. Assuming the inductor has a
Figure 3-19: Equivalent circuit of the oscillator
Figure 3-18: Inductor model
52
quality factor of QL>>1 and resonant frequency of ω0, we have
( ) ( )202 2
21LSP LS L LS L LSLS
LR R Q R Q R
Rω
= + ≈ = , (3-51)
thus
( )20
0LSP LLS
LR Q L
Rω
ω≈ = . (3-52)
Similarly, for a varactor with a quality factor of QV>>1, its equivalent parallel
resistance is
0
VCP
V
QRCω
≈ (3-53)
The total positive trans-conductance of the tank is approximately
( )200 1 11
2 2 2LP LS V VL V
total
R R L C Q Rg g ggR
ω ω+ + ++ += = ≈ . (3-54)
The circuit oscillates if the absolute value of the negative trans-conductance is
equal or greater than the positive trans-conductance, or mathematically
2m
totalg g≥ , or ( )2
01 1m LP LS V Vg R R L C Q Rω ω≥ + + + . (3-55)
In practice, the trans-conductance of the cross-coupled transistor is usually taken as
more than 3 times of gtotal to account for circuit non-idealities.
3.3 Implementation Issues and Noise
3.3.1 Implementation Issues
The first problem with the charge-pump PLL is the large on-chip capacitors
required [40]-[42]. In the above analysis, it has been shown that a C1/C2 ratio of more
53
than 10 is usually required to achieve sufficient phase margin. This problem can be
better demonstrated by the following design example, with target parameters listed in
Table 3-1.
Table 3-1: Design parameters for a 2.4GHz PLL
Center Frequency 2.4GHz
Tuning Range 160MHz
KVCO 2π×160M rad/s/V
ICP 100uA
ωc 2π×100kHz
Reference Frequency 10MHz
The division ratio is 232~248. Chose n=16, and ωz=ωc/4, ωp2=4ωc. Phase margin
calculated from Eq. (3-39) is 62mΦ = . Using Eq. (3-44), we have
31 1 2 100 10 /CP VCOc
I K R n rad sN n
ω ππ
−= = × ×
2. (3-56)
R1 is found to be 10.05kΩ. ( )1 11 634zC R pFω= = and 2 42C pF= . If the capacitors
(especially C1) are implemented on-chip, they will take enormous space. In order to
counteract this problem, off-chip loop filters are often used. In other solutions, active
loop-filters can be employed. The disadvantage of these methods is performance
degradation by additional noise introduced to the PLL and additional power
consumed by the active elements.
Another issue with the Type II or charge-pump PLL is the reference spur caused
by the mismatch of the charge pump currents [43]-[48]. As shown in Figure 3-12, the
Up current is defined by a PMOS current source and the Down current is defined by a
54
NMOS current source. It is difficult to match the two currents accurately in CMOS
technologies and the presence of current mismatch leads to periodic ripples on the
VCO control voltage even when the loop is locked. This can be explained with the
help of Figure 3-20. When the loop is locked, the net charge injected into the loop
filter should be zero. If the Up current is smaller than the absolute value of the Down
current, the duration of the Up current pulse should be longer than the Down current
pulse. Then the loop filter will see a positive input current when the Up current is on
at the beginning. Later the input current becomes negative when the Down current is
also on. Thus the voltage on the loop filter will experience a ripple. Moreover, since
the currents are related to the drain voltages of the current source transistors, the
current mismatch relies on the control voltage or the VCO output frequency. Other
factors such as charge injection and clock feed-through from the switch transistors
and charge sharing of the parasitic capacitance at the drain nodes of the current source
transistors further increases the VCO control voltage ripple.
Jitter peaking is another factor that can affect the performance of Type II PLL
Figure 3-20: Mechanism of VCO control voltage ripples
55
[49][50]. It is caused by the stabilizing zero which gives a greater than one (for N=1)
closed-loop transfer function gain at frequencies approximately between the zero and
the second pole frequency. The magnitude response of a third-order Type II PLL
closed-loop transfer function is plotted in Figure 3-21. The zero and the second pole
are located at 1.6 MHz and 18MHz, respectively. If there is modulation on the input
signal, spectral components within the jitter peaking frequency band experience
excess phase excursion. In most applications, the jitter peaking problem can be
neglected as long as a large enough damping ratio is used.
3.3.2 Noise Consideration at Different Nodes
A PLL frequency synthesizer consists of multiple circuit blocks as described in
Section 3.2. Each of these sub-circuits injects noise into the frequency synthesizer and
it is necessary to examine the effects of the noise at each node to gain some design
insights. With a PLL open-loop gain HOL(s), the phase noise transfer function for each
Figure 3-21: Magnitude response of a third-order Type II PLL closed-loop transfer function
56
noise source are listed in Table 3-2. Their magnitude response for an example PLL is
plotted in Figure 3-23.
Table 3-2: PLL Phase noise transfer function for different noise sources
Noise Source Transfer Function
Input Noise ,
( ) ( )( ) 1 ( )
out ol
n in ol
s H sN
s H sθθ
=+
Low-pass
PFD/CP Noise ( ),
( ) ( )( ) 1 ( )
out ol
n CP CP ol
s H sN
i s K H sθ
=+ Low-pass
Loop Filter Noise,
( ) 1( ) 1 ( )
out VCO
n LF ol
s Kv s s H sθ
=+
Band-pass
VCO Noise ( ) 1( ) 1 ( )
out
VCO ol
ss H s
θθ
=+
High-pass
Divider Noise ,
( ) ( )( ) 1 ( )
out ol
n div ol
s H sN
s H sθθ
= −+
Low-pass
It can be observed that while the input noise transfer function has a low-pass
shape, the VCO noise transfer function has a high-pass shape. This introduces a
trade-off on the loop bandwidth when implementing a PLL. If noise from input clock
source is dominant, then reducing the PLL (noise) bandwidth reduces the phase noise
Figure 3-22: Lineralized PLL phase noise model
57
at the output. However, if the VCO noise is dominant, then a large bandwidth is in
need to reduce the output phase noise. Therefore, an optimal bandwidth which leads
to the minimum output phase noise exists. It can be found with the knowledge of
detailed parameters for each noise source.
Figure 3-23: PLL noise transfer function response
58
Chapter 4
Delta-Sigma A/D Converters
4.1 A/D Conversion Basics
Digital signal processing is extensively used in modern electronic systems due to
its simplicity, robustness and flexibility for design and implementation. However, in
an inherently analog world, analog-to-digital (A/D) or digital-to-analog (D/A)
converters are indispensable to interface signals in real world with the digital signal
processing blocks. With the rapid development of digital signal processing techniques,
the demand for high-speed high-accuracy data converters becomes ever-increasingly
large. While technology scaling imposes multiple difficulties in accurate analog
circuit implementation, a new technique suitable for low-power high-resolution
Multi-bit Delta-Sigma (ΔΣ) A/D converters is proposed and presented in this work.
This chapter reviews the basics of A/D and ΔΣ A/D converters.
4.1.1 Sampling and Quantization
Analog-to-Digital conversion can be accomplished by uniform sampling in time
and quantization in amplitude. As discussed in Section 2.1, a discrete-time
representation of the analog (continuous-time) signal can be obtained by taking
samples at uniform time instances nTS, where Ts is a sampling period. If the spectrum
of the analog signal is band-limited within [-fB, fB] and the sampling frequency is
59
equal or larger than its Nyquist-rate fN=2fB, the spectrum of the discrete-time sample
train consists of periodic spectrum replicas of the analog signal. Without aliasing, the
original baseband spectrum can be reconstructed by applying a low-pass filter.
Since this discrete-time signal is still continuous in amplitude, a quantization
procedure is necessary to finally convert it into a digital signal which is represented
by a finite set of amplitude values. Depending on whether there is a zero output or not,
quantizers can be classified as midtread or midriser as shown in Figure 4-1. A
quantizer with M levels can also be represented as N bits, where N = log2M. The least
significant bit (LSB) of a quantizer with maximum and minimum output values of Vm
and -Vm is
m m2 21 2 1LSB N
V VVM
= =− −
. (4-1)
The maximum non-overloading input amplitude equals
( ),max 2 / 2Nin LSBV V= . (4-2)
(a) 3-bit or 8-level midriser (b) 7-level midtread
Figure 4-1: Transfer characteristic of quantizers
60
For a quantizer, the quantization error between the output and input is confined
within the range of [-LSB/2, LSB/2]. In order to simplify analysis, a linearized model
for the quantizer can be obtained under the assumption that the error sequence e[n] is
a stationary white noise process with a uniform power spectral density (PSD).
Consequently, the quantization error or noise power can be calculated as
22
12LSB
eVσ = . (4-3)
Since the above white noise power is folded into baseband [-fS/2, fS/2], and repeats at
multiples of fS due to the sampling, the PSD of the quantization noise is
( )2 1
12LSB
eS
VS ff
= . (4-4)
With the use of an anti-aliasing filter at the input to limit its input band, the
model for a conventional ADC is illustrated in Figure 4-2.
When the sampling frequency of an ADC is close to the fN=2fB, it is classified as
a Nyquist-rate ADC. The dynamic range (DR) of an ADC is defined as the ratio of
the signal power of the maximum sinusoid input and that of the input resulting in a
SNR of 1. The dynamic range for a Nyquist rate ADC can be found with Eq. (4-2)
and (4-3) as
Figure 4-2: Model for a conventional ADC
Figure 4-2: Model for a conventional ADC
61
2,max 2
10 102
2 310log 10log 2 1.76 6.02 [ ]2
in N
e
VDR N dB
σ⎛ ⎞ ⎛ ⎞= = = +⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎝ ⎠⎝ ⎠
. (4-5)
4.1.2 Oversampling ADC
Compared with the Nyquist rate ADC, an oversampling ADC operates at a
sampling frequency much higher than the Nyquist rate. Defining the oversampling
ratio (OSR) as the ratio between the sampling requency and the Nyquist rate, or
mathematically
2S S
B N
f fOSRf f
= = . (4-6)
The spectral illustration for a Nyquist rate ADC and an oversampling ADC are
shown in Figure 4-3. Since the quantization noise can be modeled as white noise and
its power is constant for the band [-fS/2, fS/2] as expressed by (4-3), the oversampling
Figure 4-3: Spectral Illustration for a Nyquist rate ADC and an Oversampling ADC
62
ADC has a much smaller quantization noise power when a proper digital filter is
employed following the quantizer. Therefore its output in-band quantization noise
power is
22, 12
LSBe OSR
VOSR
σ = . (4-7)
The dynamic range of an oversampling ADC can be obtained as
101.76 6.02 10log [ ]DR N OSR dB= + + . (4-8)
Equation (4-8) indicates that every doubling of the OSR increases the dynamic
range by 3dB or 0.5 bit. This is one benefit of the oversampling ADC. On the other
hand, since the spectrum between fB and fS-fB does not alias in the signal band, the
transition of the analog anti-aliasing filter from pass to stop band can be much
smoother than that in the Nyquist-rate ADC case. This relaxed specification for the
anti-aliasing filter is another advantage. Nevertheless, the enhancement of dynamic
range in a pure oversampling ADC is achieved at the cost of increased power
consumption or reduced conversion rate. The trade-offs are not very power-efficient
and this makes the pure oversampling ADCs less attractive in practive.
4.2 Basics of Delta-Sigma ADCs
The Delta-Sigma (ΔΣ) ADC is an important category of oversampling ADCs
which conducts the noise shaping function, i.e., shapes the quantization noise out of
the signal band. It is a very attractive technique to implement high-resolution
analog-to-digital or digital-to-analog converters in low-cost CMOS processes, since
circuit errors and noise in signal-bands can be suppressed or shaped by the loop-filter
63
employed. The block diagram of a ΔΣ ADC is illustrated in Figure 4-4. A
discrete-time ΔΣ modulator implemented by switched-capacitor technique is adopted
in this ADC. An anti-aliasing filter and a sample-and-hold stage are present preceding
the ΔΣ modulator. The quantizer in the modulator has a low resolution (usually from
1- to 3-bit). With a proper low-pass loop filter H(z) and the feedback path in the
modulator, quantization noise sees a high-pass transfer function and thus can be
shaped to high frequencies. The modulator is followed by a decimation filter
consisting of a digital low-pass filter and a down-sampling-by-OSR stage. The
decimation filter has a cut-off frequency of fB and it filters out the high frequency
noise and then high-resolution data-conversion is achieved. Nyquist rate
high-resolution output is recovered by the down-sampling stage.
Replacing the quantizer with the linear white noise model, and assuming it has a
unity-gain, a linearized ΔΣ modulator model can be obtained as shown in Figure 4-5.
This approximation is good for multi-bit quantizers. For a single-bit quantizer in a ΔΣ
modulator, its gain is related to the scaling factor of the last integrator [51]. The
simplest loop filter that fits the above requirement, i.e., passing the input signal and
Figure 4-4: ΔΣ ADC Block Diagram
64
shaping quantization noise, is an integrator, which has a transfer function as
( )1
11zH z
z
−
−=−
. (4-9)
The transfer function of this system can be found as
( ) ( )( ) ( ) ( ) ( )1
1 1H z
Y z X z E zH z H z
= ++ +
. (4-10)
Define signal transfer function (STF) and noise transfer function (NTF) as
( ) ( )( )1
H zSTF z
H z=
+, (4-11)
( ) ( )1
1NTF z
H z=
+. (4-12)
With Eq. (4-9) as the loop filter, we have STF(z) = z-1 and NTF(z) = 1-z-1. The
transfer function for the first-order ΔΣ modulator can be obtained as
( ) ( ) ( ) ( )1 11Y z z X z z E z− −= + − . (4-13)
It can be observed that the STF is simply a delay and the NTF is a differentiator
which has a high pass magnitude response. Applying
2 / Sj f fz e π= , (4-14)
Figure 4-5: Linearized model of a ΔΣ modulator
65
the shaped quantization noise PSD can be analyzed as
( ) ( ) ( ) ( ) ( ) ( )22 2 / 21 4 sin /Sj f f
e e e SS f S f NTF f S f e S f f fπ π−= = − = . (4-15)
The effect of first-order ΔΣ noise shaping is plotted in Figure 4-6. Since most of
the quantization noise is pushed outside the signal band, the post-filtered in-band
noise is reduced significantly compared with that in a pure oversampling ADC. The
in-band quantization noise power for the first-order ΔΣ modulator is calculated as
( ) ( )22 2 2
21 32sin
12 36B B
B B
f f LSB LSBe ef f
S S
V VfP S f NTF f df dff f OSR
ππ− −
⎛ ⎞⎛ ⎞= = ≈⎜ ⎟⎜ ⎟⎜ ⎟ ⋅⎝ ⎠⎝ ⎠∫ ∫ , (4-16)
where sin(πf/fS) is approximated as πf/fS since OSR>>1. The dynamic range is
obtained as
1 106.02 3.41 30log [ ]DR N OSR dB= − + . (4-17)
We see that doubling the OSR gives a DR improvement of 9dB or 1.5 bits for this
first-order ΔΣ modulator. Compared with the case in a pure oversampling ADC, the
noise shaping technique enhances circuit performance greatly.
In spite of its simplicity, first-order ΔΣ modulator is rarely used in practice since
Figure 4-6: First-order ΔΣ noise shaping
66
it suffers from the limit cycle tones caused by quantizer nonlinearity [52]. In the
above analysis, the quantizer is modeled as a linear white noise source. However, in
reality, the quantization noise is correlated with the input signal, and this correlation
is not embodied in the white noise model. Unfortunately, in the first-order ΔΣ
modulator, the correlation is quite strong and the modulator output usually contains
significant tone structures if the modulator input is not a random signal or no
sufficient randomization is introduced into the circuit. This problem becomes more
pronounced if a DC input signal is fed into the modulator. The limit cycle tones can
be suppressed by adding a (pseudo) random dither signal to the input of the quantizer
or to the input of the modulator [52]. When the dither signal is introduced at the
modulator input, it has to be sufficiently small in order to keep the SNR degradation
at a tolerable level since noise at the modulator input is shaped by the loop. On the
other hand, in higher-order ΔΣ modulators, the input signal and the quantizer noise
samples are less correlated compared with the case in the first-order modulator and
the limit cycle problem is relieved. Although the theoretical prediction of the limit
cycle problem in higher order ΔΣ modulators depends on circuit topology and is quite
complicated [53][54], it can usually be investigated by behavioral simulations.
Moreover, the tones are usually located outside the signal band in higher-order ΔΣ
modulators and can be readily suppressed by the decimation filter. In digital ΔΣ
modulators for fractional-N PLLs, this problem is of more concern since it can
influence the out of band noise performance of a PLL significantly and extra care
should be taken in such an application.
67
4.3 Higher-Order Delta-Sigma ADCs
The block diagram for a second-order ΔΣ modulator is illustrated in Figure 4-7.
The transfer function of this second-order modulator is found as
( ) ( ) ( )2 2( ) ( )Y z STF z X z NTF z E z= + , (4-18)
where STF(z) = z-1 and NTF(z) = (1-z-1)2.
The square of the NTF magnitude is found as
( ) ( )2 42 2sin / SNTF f f fπ= ⎡ ⎤⎣ ⎦ . (4-19)
By taking integral of the filtered noise over the signal band and using sin(πf/fS) ≈ πf/fS
for OSR>>1, the in-band noise power can be found approximately as
2
2 5
460
LSBe
VPOSRπ
≈⋅
, (4-20)
The dynamic range of this second-order ΔΣ modulator is then found to be
2 106.02 11.14 50log [ ]DR N OSR dB= − + . (4-21)
It is shown here that the second-order modulator has a dynamic range gain of 15dB or
2.5bits/octave. This example demonstrates that by applying a higher order loop filter
in a ΔΣ modulator, more aggressive noise shaping is achieved and DR/SNR of the
Figure 4-7: Second-order ΔΣ modulator block diagram
68
ADC can be improved more significantly compared with the case in the first-order
ΔΣ modulator. Moreover, as discussed immediately above, the limit-cycle tones are
also relieved due to less correlation between the quantization noise and the modulator
input signal in a higher order ΔΣ modulator. Therefore, higher order modulators are
more attractive and practical for implementation.
Inferred from the above analysis on first- and second-order ΔΣ modulators,
ideally, an Mth-order modulator would have an NTF of an Mth-order differentiator or
NTFM(z)=(1-z-1)M. Then the gain of dynamic range would be (6.02M+3) dB/octave
and high resolution ADCs can be implemented in this way under a reasonable OSR
and power consumption. In practice, there are at least two ways to build a higher
order ΔΣ modulator. The first one is to use the single-loop topology. In a single-loop
modulator, though the second-order modulators are intrinsically stable, the
out-of-band gain of the higher order NTF increases rapidly resulting in a source of
instability. To guarantee system stability within a specific input amplitude range, the
ideal NTFs mentioned above is not a valid choice for single-loop modulators with
orders equal or greater than three. Therefore, the noise shaping effect is compromised
for loop stability. In order to overcome this instability issue and also the SNR
degradation, a higher order ΔΣ modulator can also be designed using the cascade of
intrinsically stable first- and second-order modulators which is known as the
Multi-stAge noise Shaping (MASH) structure. While an ideal higher-order NTF may
be achievable, the cascade/MASH topology is more sensitive to circuit imperfections
such as finite amplifier DC gain, limited amplifier bandwidth and non-zero switch
69
resistance. Moreover, its performance depends on accurate circuitry matching which
is in contradiction with the aim of ΔΣ modulation to implement high-resolution data
conversion with circuits of low-accuracy. With these implementation difficulties in
the MASH architecture, the single-loop topology is usually more favorable in spite of
its instability. The details on the two ΔΣ modulator structures and the stability issues
of single-loop modulators are discussed below.
4.3.1 Single-Loop ΔΣ modulators with Distributed Feedback Paths
Single-loop ΔΣ modulators contain only one quantizer. Figure 4-8 shows the
block diagram of an Mth-order single-loop ΔΣ modulator with distributed feedback
paths. It incorporates multiple integrators in the forward path of the modulator loop. A
feedback path exists for each integrator and integrators are weighted by coefficients ai,
i=1, …, M. For the modulator shown in Figure 4-8, with the unity-gain white noise
quantizer model, the STF and NTF are found to be
( )( )
( )1
11
1
MMii
MM M iji j i
I z aSTF z
a I z=
− += =
⋅=
+∏
∑ ∏, (4-22)
Figure 4-8: Block diagram for an Mth-order ΔΣ modulator with distributed feedback
70
( )( )1
1
11 MM M i
ji j i
NTF za I z− +
= =
=+∑ ∏
, (4-23)
where I(z)=z-1/(1-z-1). At low frequencies, the noise shaping behavior is dominated by
the largest term of the denominator in Eq. (4-23) and the magnitude of the NTF can
be approximated as
( )1
1
1M
Mii
zNTF z
a
−
=
−≈∏
. (4-24)
The in-band noise reduces exponentially with the increase of OSR. For stability
reasons, some or all of the scaling coefficients ai are less than one; therefore the
denominator of Eq. (4-24) is smaller than one. Quantization noise shaping effect is
thus degraded and noise power is scaled up by 1/(1
Mii
a=∏ ) compared with that in the
ideal Mth-order differentiator NTF.
This distributed feedback topology and its variations are widely used in practice.
In Figure 4-8, to obtain simple general mathematic expressions for the STF and NTF,
all the integrators carry unit-delays. However, all or some of the integrators can be
replaced with delay-free integrators as long as there is at least one unit-delay in the
loop for the sake of causality. And the STF and NTF should be recalculated
accordingly. The block diagram of a fourth-order single-loop ΔΣ modulator with all
delay-free integrators is demonstrated in Figure 4-9. The delay element in the outmost
feedback path guarantees the system is causal. The NTF is found to be
1 4
4 1 2 3 41 2 3 4 2 3 4 3 4 4 2 3 4 3 4 4 3 4 4 4
(1 )( )1 (4 ) (6 2 3 ) (4 3 ) (1 )th
zNTF za a a a a a a a a a z a a a a a a z a a a z a z
−
− − − −
−=
− − − − − + − − − − − − + −
(4-25)
71
By removing one or two integrators in this modulator, a third- (or second-) order ΔΣ
modulator can be obtained. Interestingly, the NTFs for the third- and second-order
modulator are
4 4 13 1
( )( )
(1 )th a
rd
NTF zNTF z
z=
−=−
, (4-26)
3 3 12 1
( )( )
(1 )rd a
nd
NTF zNTF z
z=
−=−
. (4-27)
Besides the SNR degradation, another drawback of this modulator topology is
that the outputs of the integrators track input signals and this can result in large
voltage swings which overload the quantizer. To understand this, we see that the
input to an integrator should be zero over time, so that the DAC output tracks the
modulator input signal closely. Since the inputs of integrators are the difference
between the feedback DAC signal and the output from the preceding integrator, the
integrator outputs consequently contain significant amount of input signals. On one
hand, this requires the active components in the integrators to have large output
swings. On the other hand, to avoid quantizer overloading for large input signals,
proper dynamic-range scaling should be carried out.
This feedback only topology also lacks flexibility for the selection of the STF.
Figure 4-9: Block diagram for a 4th-order ΔΣ modulator with weighted feedback and delay-free integrators
72
Comparing Eq. (4-22) with Eq. (4-23), once the NTF is optimized and settled, the
STF would be fixed. In order to optimize the STF as well, feed-forward paths can be
added as shown in Figure 4-10.
4.3.2 Single-Loop ΔΣ modulators with Feed-Forward Paths
It is discussed in the previous section that the feed-back topology requires that
the amplifiers have a large output swing. However, in deep-submicron CMOS
technologies, the amplifier output swing is often limited by the small power supply
voltages and the relatively larger transistor threshold. Therefore, it is worthwhile to
investigate ΔΣ topologies suitable for deep-submicron processes.
A ΔΣ modulator employing a single feedback path and weighted feed-forward
paths is illustrated in Figure 4-11. Using the unity-gain white noise quantizer model,
the STF and NTF are found to be
( ) ( )( )
11
111
M iM ii
M iM ii
a I zSTF z
a I z− +=
− +=
=+∑∑
, (4-28)
Figure 4-10: Block diagram for a Mth-order ΔΣ modulator with weighted feedback and distributed feedforward
73
( )( )11
11 M i
M ii
NTF za I z− +=
=+∑
, (4-29)
The expressions for the STF and NTF are similar to their counterparts in a
distributed feedback modulator and the quantization noise shaping performance is
substantially the same. In order to investigate the output swings of integrators,
third-order ΔΣ modulators with different single-loop topologies are designed and
behavior simulations in MATLAB are carried out. For the purpose of comparison,
integrator output swings versus input signal level for a weighted feed-forward
modulator and a distributed feedback modulator are plotted in Figure 4-12 and Figure
4-13, respectively. For the feed-forward topology, the outputs of the first two
integrators remain small and constant over the entire input range. The output of the
last integrator increases with inputs greater than about -30 dBFS but it is still smaller
than that in the feedback topology. As long as quantizer overloading is avoided, errors
at the output of the last integrator are shaped the same way as the quantization noise.
Figure 4-11: Block diagram for a Mth-order ΔΣ modulator with weighted feed-forward
74
Figure 4-12: Output swing of integrators in feed-forward topology
Figure 4-13: Output swing of integrators in feedback topology
75
Moreover, if necessary, a feed-forward path from the modulator input to the
summation node preceding the quantizer can decouple the correlation between the
input and the output of the last integrator. In the feedback topology, output swings of
all the three integrators are heavily correlated with the input signal. Their amplitudes
increase sharply for a large input signal levels. Especially for the last integrator, when
the input level is -3 dBFS, its output swing already occupies the full scale. Since the
errors at the first and second integrator output nodes are less shaped (first-order and
second-order, respectively), the integrators should have sufficient output swing
capability. The difference mentioned above makes the feed-forward topology more
attractive in deep-submicron CMOS technologies where amplifier swings are
relatively small.
The magnitude responses of STF and NTF of a sample multi-bit feed-forward
3rd-order modulator are plotted in Figure 4-14 and Figure 4-15. It can be noticed that
magnitude peaking occurs for the STF. This is a common phenomenon in the
feed-forward topology and care should be taken when designing the modulator to
avoid STF magnitude peaking in signal band. Otherwise, it can cause nonlinearities in
the quantizer.
4.3.3 Stability of single loop ΔΣ modulators
As discussed earlier, single-loop ΔΣ modulators with orders higher than two
suffer from instability. The stability issue is of primary priority when designing a
single-loop modulator and should be investigated exhaustively. Several methods
which can be used to provide insights for a stable loop design are discussed below.
76
Figure 4-15: NTF magnitude response of a 3rd-order modulator
Figure 4-14 STF magnitude response of a 3rd-order modulator
77
The stability of a linear feedback system is determined by its loop gain, or H(z)
in Eq. (4-10). However, the ΔΣ modulators are not linear systems and nonlinearities
have strong effects on their stability. For example, if the loop filter is not designed
properly, internal signals could grow so large to saturate the amplifiers. Additionally,
in previous analysis, the quantizer is modeled as a linear unity-gain white noise
source for simplicity. In reality, this is not true and the gain of the quantizer varies
under different conditions. For example, a one-bit (2-level) quantizer can have an
arbitrary gain since its output is simply the sign of the input signal. Simulations for
some specific ΔΣ modulators indicate that for moderate input signals, the quantizer
gain is related to the scaling coefficient of the last integrator and their product is a
constant. For a multi-bit quantizer, the unity gain is well defined by its transfer
characteristic for inputs with moderate amplitudes. However, if the input signal is so
small that the output changes between ±LSB only, the gain of the quantizer can be
larger than 1. On the other hand, if the quantizer is overloaded, the gain becomes
Figure 4-16: Block diagram for an Mth-order ΔΣ modulator with weighted feed-forward
78
smaller than 1. The variations of quantizer gain are closely related to the loop stability.
In the following analysis, kQ is used to denote the quantizer gain.
In a well-designed modulator, no severe internal signal saturation should occur,
and instability is mainly caused by the overloading of the quantizer. The input of the
quantizer is found as
( ) ( ) ( ) ( )( ) ( )1inQ z STF z X z NTF z E z= + − . (4-30)
Since the magnitude response of the STF is approximately 1 within the signal
band and no large signal is present out of the signal band at the input node of the
modulator, the stability of the modulator is primarily determined by the NTF and the
amplitude of the quantization error which is determined by the resolution or the
number of bits of the quantizer.
A 3rd-order ΔΣ modulator with weighted feed-forward paths is taken as the
example for loop stability analysis. The topology of the modulator is illustrated in
Figure 4-16. It consists of one delay-free integrator and two unit-delay integrators and
scaling coefficients a1, a2, and a3. The NTF of this integrator are found as
( ) ( )( ) ( ) ( )
31
1 2 31 2 1 2 3 1
1
1 3 3 2 1Q Q Q
zNTF z
a a k z a a a k z a k z
−
− − −
−=
⎡ ⎤ ⎡ ⎤− − + + − + − − −⎣ ⎦ ⎣ ⎦. (4-31)
The NTF root-locus of the third-order modulator shown in Figure 4-16 is plotted
in Figure 4-17 for different kQ values from 0 to infinity. The moving of the three pole
locations with kQ forms three curves. Another root-locus plot of a modulator with
different scaling coefficients is illustrated in Figure 4-18 for the purpose of
comparison.
79
Figure 4-17 Root-locus of a 3rd-order modulator with a1=1, a2=1, a3=0.5
Figure 4-18 Root-locus of a 3rd-order modulator with a1=1, a2=1, a3=1.5
80
The loci of three poles are shown in the plots above. Though the real pole
approaches -∞ with the increase of kQ in the plots, it does not contribute to instability
in reality since the instantaneous kQ will decrease when the quantizer is overloaded
and this will pull the pole back into the unit circle. This is known as a stable limit
cycle. In Figure 4-17 and 4-18, the term kQ,crit is the critical gain. If the quantizer has
a gain larger than kQ,crit, all the three poles are located inside the unit circle. According
to the linear control theory, then the system is stable. In the example modulators, the
kQ,crit is found to be 0.5 and 1.5 for a3=0.5 and a3=1.5, respectively. It is obvious that
the stable input range for the modulator with a3=0.5 is much larger. With an
assumption that a multi-bit quantizer is used, the modulator with a3=1.5 will
obviously fail, because kQ=1 for a multi-bit quantizer. On the contrary, the modulator
with a3=0.5 will still be stable even if light overloading happens. Since ΔΣ modulators
are nonlinear systems but the root-locus analysis is based on linear control theories,
simulations should be carried out as the final verification step for loop stability.
The above analysis explains the effect of variable quantizer gain on loop stability
and gives a general idea that kQ,crit should be kept low for a relatively large stable
input range. However, a small kQ,crit may compromise the noise shaping performance
of the modulator and degrade the otherwise achievable SNR. Also, specific NTF
requirements are not given to facilitate loop implementation.
In practice, based on extensive simulations and implementations of modulators
with different topologies, the Lee Criterion is widely accepted as a rule of thumb, i.e.,
a single-bit ΔΣ modulator is likely to be stable if its NTF has a maximum magnitude
81
less than 1.5 [55]. In [56], it is proposed that for modulators with 2-bit, 3-bit and 4bit
quantizers, the maximum NTF magnitude can be set at 2.5, 3.5, and 5 respectively.
These values give both a reasonable stable input range (80% full scale) and good
noise shaping effect.
Other techniques can also be used to assist the design of a stable higher order ΔΣ
modulator. In [57], a more elaborate and complicated modulator model with nonlinear
quantizer gain gives good prediction for its stable input range. Some cook-book like
design procedures are also available in [52]. However, when designing and
optimizing a specific modulator, extensive behavior simulations are still necessary for
verification purpose before implementation.
4.3.4 MASH modulators
As discussed before, higher order ΔΣ modulators can be implemented with the
Figure 4-19 A two-stage general structure for a MASH modulator
82
ideal NTF using the MASH topology. The basic concept for a MASH modulator is
illustrated in Figure 4-19. The output of the first stage is given by
( ) ( ) ( ) ( ) ( )1 1 1 1Y z STF z X z NTF z E z= + , (4-32)
where STF1 and NTF1 are the signal and noise transfer functions of the first stage,
respectively.
The input to the second stage is the difference between the quantizer input and
output, which is equal to –e1. Therefore the output of the second stage is
( ) ( ) ( ) ( ) ( )2 2 1 2 2Y z STF z E z NTF z Y z= − +⎡ ⎤⎣ ⎦ , (4-33)
where STF2 and NTF2 are the signal and noise transfer functions of the second stage.
The digital filters DF1 and DF2 are designed such that the quantization error of
the first stage (e1) is cancelled in the final output. Consequently, the following
condition should be satisfied
( ) ( ) ( ) ( )1 1 2 2 0NTF z DF z STF z DF z− = . (4-34)
The widely adopted solutions are
( ) ( )1 2DF z STF z= , (4-35)
( ) ( )2 1DF z NTF z= . (4-36)
Typically, both of the two stages are second-order modulators, and this yields
( ) ( ) 11 2STF z STF z z−= = , (4-37)
( ) ( ) ( )211 2 1NTF z NTF z z−= = − . (4-38)
Then the final output is given by
83
( ) ( ) ( ) ( )42 11 11Y z z X z z E z− −= + − . (4-38)
A fourth-order noise shaping NTF is obtained while the stability of this modulator is
that of a second-order one and the loop is intrinsically stable. Even higher order
modulator can be obtained by adding additional stages without the stability concern
as shown in the single-loop modulators. Nonetheless, since the input to the second
(next) stage is obtained using analog subtraction and noise cancellation depends on
accurate matching of analog filters, the quantization noise cannot be canceled ideally.
In other words, circuit imperfection introduces noise leakage into the next stage.
Unfortunately, the noise leakage is only shaped by a low order NTF and this
phenomenon may result in serious deterioration of the overall modulator performance.
In real circuits, the actual coefficients of a filter are influenced by the matching of
passive elements, the finite gain and the bandwidth of the active ones. Thus MASH
modulators are very sensitive to variations of the above factors. For this reason, the
MASH structure is not used in our design and it is not the emphasis of our work.
4.3.5 Techniques to enhance ΔΣ modulator performance
Using Eq. (4-24), the in-band noise of an Mth order ΔΣ modulator can be
obtained as
( )2 2
2, 2 12
1
112 2 1
MLSB
e M M Mii
VM OSRa
πσ +
=
=+ ∏
. (4-39)
Therefore several ways to reduce in-band noise can be obtained from the above
equation.
The first is to use a larger M or higher order modulator. If OSR is much larger
84
than π, more quantization noise may be shaped out of the signal band with a larger M.
Nevertheless, higher order single-loop modulator suffers from the instability issue
mentioned, and in order to maintain a reasonable stable input range, the product of the
scaling coefficients is usually less than one and may be reduced dramatically in
higher order modulators. Thus, the performance enhancement may not be significant
using this method for an already high order loop filter.
Second, in-band noise can be reduced by increasing the OSR. It is
straightforward that modulator SNR increases rapidly with the OSR. Also, it is easier
to construct the anti-aliasing filter for a larger OSR since the transition band can take
a larger frequency range. However, the increase in OSR is equivalent to increase in
amplifier bandwidth. In CMOS technologies, when a transistor operates in saturation
region, its bandwidth and power consumption have a square law relationship, i.e., in
order to increase its bandwidth to twice the original one, its power consumption
should be approximately four times the original. Therefore, this method may result in
a design which is not power efficient. Moreover, operating at high sampling
frequency, switched-capacitor may suffer from performance deterioration due to strict
clock requirement and the finite switch resistance.
Third, in the above discussed modulator topologies, the zeros of the modulator
NTF are all placed at z=1. However, a better noise shaping effect may be achieved by
optimally spreading zero locations on the unit circle. This can be done by adding local
feedback paths in the loop filter. In order to show this, optimal zero locations for a
third-order modulator is found exemplary. For a third-order modulator, its NTF zero
85
locations are z=1, z=e±jα, and it has a NTF given by
( ) ( )( )( )( )
1 1 11 1 1j jz e z e zNTF z
A z
α α− − − −− − −= , (4-40)
where A(z) is the denominator of the NTF. For signal band with a large OSR, the
magnitude of the NTF is
( ) ( )( )
2 2
1in bandNTF z
A zω ω α
−
−≈
=. (4-41)
The optimal zero locations yield minimum in-band noise. Therefore αopt can be found
by minimizing
( ) ( )( )2
2 2
0
BI dω
α ω ω α ω= −∫ . (4-42)
Differentiating I(α) with respect to α and equating the result to zero,
15 0.775opt B Bα ω ω= ± ≈ ± . (4-43)
Assuming the quantization noise is white and NTF poles have little effect on the
in-band noise, the SNR improves by 10log10(I(0)/I(αopt))=8dB. It can be observed that
with the decrease of OSR, ωB and thus αopt will decrease too. Since significant noise
reduction relies on exact placement of zeros, this method may not be precisely
realized for a modulator with a small OSR.
Another approach to enhance ΔΣ modulator performance is to use a multi-bit
quantizer. A multi-bit quanitzer reduces VLSB in Eq. (4-4) and the PSD of the
quantization noise is thus reduced by 6dB per extra bit. Also, from Eq. (4-30), a
smaller quantizer noise can also enhance the stability of the modulator. Therefore, a
86
more aggressive NTF with larger out-of-band gain can be employed as discussed
above to improve noise shaping effect and reduce in-band quantization noise further.
Nevertheless, when designing a ΔΣ ADC with a multi-bit quantizer, a highly-linear
feedback DAC matching the overall ADC accuracy is required, because the feedback
signal is subtracted from the analog input directly and no noise-shaping is carried out.
The feedback DAC is the major bottleneck when designing a multi-bit ΔΣ ADC, since
it is not a trivial task to design a highly-linear (>14bit) DAC in CMOS VLSI
technologies with the presence of inherent component mismatch. In the following
chapter, a nonlinearity-suppressed DAC is proposed and a multi-bit ΔΣ modulator is
designed with the proposed DAC.
4.4 Thermal Noise in ΔΣ ADCs
In a proper designed ΔΣ ADC, shaped quantization noise may take only a small
fraction of the total noise budget. Thermal noise usually becomes the dominant noise
source and it is investigated in the following example specifically.
The ΔΣ modulator shown in Figure 4-16 is plotted in Figure 4-20 with the noise
sources indicated. Assuming conventional OTA integrators are used, using the
integrator noise model derived in Chapter 2, seven noise sources are shown in the
figure. Vni1, Vni2 and Vni3 are the input-referred thermal noise at the inputs of the
integrators. Vno1, Vno2 and Vno3 are the opamp noises not included in the
input-referred calculation but present at the integrator outputs. Vnq represents the total
thermal noise present immediately preceding the quantizer.
Due to the under-sampling, the spectrum of each noise source is nearly white as
87
discussed in Chapter 2. Their single-sided PSDs are given by
2,
, / 2nix nox
ix oxS
VS
f= , (4-44)
where the integrator input noise power is
2 2 1 61 , 1, 2,31nix
Sx mx x
kTV xC g R
⎛ ⎞= + =⎜ ⎟+⎝ ⎠
, (4-45)
and the output noise power is
2 4 , 1,2,33nox
Lx
kTV xC
= = . (4-46)
Assuming for the quantizer, gmQRQ>>1, and the three input branches have scaling
coefficients as shown in Figure 4-20, and the unit capacitor is Cf, then the total input
noise for the quantizer is
( )( )
22
2 2.5 22.52.5
fnQ
ff
kT C kTVCC
= = . (4-47)
Each noise source has a specific transfer function and they are evaluated
separately. Assuming the quantizer is a unity-gain white noise source, the NTFs are
Figure 4-20: Noise analysis for an Mth-order ΔΣ modulator with weighted feed-forward
88
found to be
( ) ( )1 2 3
1 1 2
2 2.51 0.5iz z zNTF z STF z
z z
− − −
− −
− += =
− +, (4-48)
( ) ( )( )1 1 2
1 1 2
1 2 2.51 0.5o
z z zNTF z
z z
− − −
− −
− − +=
− +, (4-49)
( ) ( )( )1 1
2 1 2
1 1 0.51 0.5i
z zNTF z
z z
− −
− −
− −=
− +, (4-50)
( ) ( ) ( )21 1
2 1 2
1 1 0.51 0.5o
z zNTF z
z z
− −
− −
− −=
− +, (4-51)
( ) ( )21 1
3 1 2
1 0.51 0.5i
z zNTF z
z z
− −
− −
−=
− +, (4-52)
Figure 4-21 NTFs at different nodes for a 3rd-order ΔΣ modulator
89
( ) ( ) ( ) ( )31
3 1 2
11 0.5o q
zNTF z NTF z NTF z
z z
−
− −
−= = =
− +. (4-53)
The magnitude response of the above noise transfer functions are plotted in Figure
4-21. It is clear that vni1 is not shaped; vno1 and vni2 are first-order shaped; vno2 and vni3
are second-order shaped; vno3 and vnq are third-order shaped.
With the PSDs and NTFs for thermal noise sources, the in-band thermal noise
power can be found by applying integral from DC to fB=fS/(2OSR). With OSR>>1,
the results are
( ) 2/ 2 2 1, 1 1 10
Sf OSR nin i i i
vP S NTF dfOSR
= ≈∫ . (4-54)
( ) 2/ 2 2 1, 1 1 1 30
3.3Sf OSR non o o o
vP S NTF dfOSR⋅
= ≈∫ . (4-55)
( ) 2/ 2 2 2, 2 2 2 30
3.3Sf OSR nin i i i
vP S NTF dfOSR⋅
= ≈∫ . (4-56)
( ) 2/ 2 2 2, 2 2 2 50
19.5Sf OSR non o o o
vP S NTF dfOSR⋅
= ≈∫ . (4-57)
( ) 2/ 2 2 3, 3 3 3 50
19.5Sf OSR nin i i i
vP S NTF dfOSR
⋅= ≈∫ . (4-58)
( ) 2/ 2 2 3, 3 3 3 70
549.4Sf OSR non o o o
vP S NTF dfOSR
⋅= ≈∫ . (4-59)
( ) 2/ 2 2 1, 70
549.4Sf OSR nin q q q
vP S NTF dfOSR
⋅= ≈∫ . (4-60)
With OSR =40, it is obvious that the first term dominates the total thermal noise and
the thermal noise power is about
90
2, 1
1 1 1 1
2 1/ 61 5.8 101n n i
S m S
kT kTP POSR C g R C
−⎛ ⎞≈ = + ≈ ×⎜ ⎟⋅ +⎝ ⎠
. (4-61)
The thermal noise in a ΔΣ modulator is determined by the sampling capacitor of the
first integrator. Therefore, when the noise budget is settled for an ADC design, its
capacitor size can be found accordingly.
91
Chapter 5
PLL Design with a Low-Power
Active Switched-Capacitor Loop Filter
In this chapter, a low-power switched-capacitor loop filter is proposed for PLLs.
The design methodology and testing results of a high-performance PLL prototype
with this loop filter in a 0.18μm CMOS process is presented. Section 5.1 reviews
existing loop filter implementation topologies and in Section 5.2, the proposed loop
filter structure is explained in details. Section 5.3 describes the design of other blocks
of the PLL. Measurement results are provided in Section 5.4.
5.1 PLL Loop Filters in literatures
The basic passive RC loop filter of a PLL has been discussed in Chapter 3. In
spite of its simplicity, the large filter capacitor required is usually an integration
bottleneck. Many different loop filter structures for CMOS PLLs are reported. They
can be classified into three general categories: active continuous-time (CT) loop
filters, passive switched-capacitor loop filters and hybrid loop filters.
5.1.1 Active Continuous-Time Loop Filter
With the use of active filters, the origin pole and the stabilizing zero as required
for a Type II PLL can be realized separately and it is known as a dual path loop filter
92
[58]-[61]. In this configuration, two separate charge pumps provide the proper
currents to each path and the capacitor ratio requirement in a passive RC loop filter
now can be converted into that between the two charge pump currents, which is
simple to implement in CMOS technologies. The loop filters in [59] and [60] are
illustrated in Figure 5-1 and Figure 5-2, respectively. The two paths can be identified
as an integration path and a proportional path.
In order to investigate the principle of this approach, the transfer function of the
third-order dual-path loop filter shown in Figure 5-1 can be found as
( )11 1
p p zCP pCP CPsum z p
z p p z p p
sR C BCBI RI IV V VsC sR C sC sR C
+ += − = + =
+ +, (5-1)
3 31sum
CtrlVVsR C
=+
. (5-2)
The stabilizing zero is located at
( )1
zp z pR BC C
ω =+
. (5-3)
It can be observed that the scaling up of the proportional path current is equivalent to
scaling up the integration capacitor size. With the scaling factor B, the size of Cz
becomes more flexible. Similar results can be obtained for the loop filter in Figure
5-2, where only one Opamp is used.
The dual-path active loop filter has several disadvantages. Compared with the
passive RC loop filter, obviously, extra power is consumed and extra noise from the
active elements is introduced. Also, voltage ripple problem caused by current
mismatch are not improved. Moreover, the integration path current could be very
93
small for a large B and it could contribute significant noise.
5.1.2 Passive Switched-Capacitor Loop Filter
CMOS switched-capacitor (SC) or discrete-time circuits offer high accuracy for
analog signal processing. This technique can surely be used to design loop-filters for
PLLs. As discussed in Chapter 2, in an active SC filter, the amplifier bandwidth must
be sufficient large to assure adequate settling accuracy in SC circuits. For a
Figure 5-2: Dual-path loop filter 2
Figure 5-1: Dual-path loop filter 1
94
conventional OTA SC integrator, to achieve a settling accuracy of 0.1%, the unity
gain frequency of the amplifier should be at least 2.23/β times the sampling frequency,
where β is the feedback coefficient. Therefore, even for medium frequency operations,
the OTA can be power hungry.
To avoid high power consumption, simple passive SC filters can be used as
demonstrated in [61][62]. The conceptual schematic of the loop filter along with the
single-polarity charge pump employed is illustrated in Figure 5-3. Assuming the
timing diagram of the reference signal fref and feedback signal fdiv is as shown in
Figure 5-3, the clock timing schemes for each switch are plotted accordingly. It can
be identified that one operation cycle of this circuit consists of three phases. First, the
reset switch Φrst discharge Cs. Second, Φs is on and Cs is charged by a constant
current ICP for a period proportional to the phase difference of fref and fdiv. Third, Φh is
turned on and the charge is redistributed between the two capacitors. Since a specific
phase error corresponds to a specific VCO control voltage or output frequency in this
Figure 5-3: Passive switched-capacitor loop filter and its timing scheme
95
configuration, the PLL built with this loop filter is a Type I system. This conclusion
can also be obtained by investigating the transfer function of this circuit
mathematically as shown below.
The z-domain transfer function of the sample and hold circuit is found as [62]
( )( )
12
11 1h
s
zH z C zC
−
−=
+ −. (5-4)
Using
refj fz e ω= , (5-5)
1/ 2 1/ 2 2 sin2 ref
z z jfω−− = , (5-6)
equation (5-4) can be rearranged as
( ) 1
cos 1 2 sin2 2
h
ref s ref
H jCj
f C f
ωω ω
=⎛ ⎞
+ +⎜ ⎟⎝ ⎠
. (5-7)
At frequency much smaller than fref, equation (5-7) can be approximated as
( ) 121 s h
ref s
H sC Cs
f C
=⎛ ⎞+
+ ⎜ ⎟⎜ ⎟⎝ ⎠
, (5-8)
where s=jω. This is a simple first-order low pass filter and no DC pole is present.
Therefore, the PLL has only one DC pole provided by the VCO and the loop
dynamics is Type I. Extra poles can also be added for better filtering if necessary by
adding RC networks as shown in [62], where a third order low-pass filter is
implemented. Though not pointed out in literatures, it is straightforward that a hold
96
action exists in this SC filter and it has a sinc low-pass response in the frequency
domain. Therefore, the complete magnitude and phase response of the filter with the
sinc effect added should be investigated carefully during practical design.
This structure is simple and does not require large on-chip capacitors. By using
the sampling switch, the VCO tuning node is isolated from the charge pump output.
Therefore, the steady-state phase error doesn't have a significant effect on the
reference-spur performance. Also, the switched-capacitor pole location is well
defined by reference frequency and capacitor ratio.
However, as addressed earlier, a PLL with this loop filter is a Type I system. It
suffers from the limited lock-in range problem. Thus in the reported works [61][62], it
is mentioned that a VCO with digital coarse tuning should be used and this increases
circuit complexity. Also, because there is only one origin zero in the VCO noise
transfer function, compared with a Type II PLL, VCO output phase noise has a more
strong effect on the in-band phase noise in this Type I PLL [61].
5.1.3 Hybrid Loop Filter
In the previous section, it is shown that with the switched-capacitor technique,
the VCO tuning node is isolated with the charge pump. Considering the fact that the
net charge injected into the filter is zero in a locked Type II PLL, charge pump current
mismatch will have little effect on spurious performance if the SC technique can be
applied. In order to obtain SC Type II dynamics and keep power consumption low,
loop filters with a switched-capacitor first stage followed by a continuous-time
integrator to provide the origin pole are proposed [64][65]. These loop filters are
97
illustrated in Figure 5-4 and 5-5, where an OpAmp filter and Gm-C filter are
employed, respectively.
The active filter in Figure 5-4 provides a DC pole, a stabilizing zero at
ωz=1/(RzCz) and an additional pole at ωp=1/(Rz(1/Cz+1/Cp)-1).
In Figure 5-5, the output of the loop filter is a current therefore a
Current-Controlled-Oscillator (CCO) instead of a VCO should be used in cooperation.
Figure 5-4: Hybrid loop-filter in [64]
Figure 5-5: Hybrid loop-filter in [65]
98
The transfer function of the Gm-C filter is found as
( ) 12
18
Ctrl mGm m
SH LF
I GH s GV sC
⎛ ⎞= = +⎜ ⎟
⎝ ⎠, (5-9)
A DC pole and a stabilizing zero are obtained.
The hybrid loop-filter combines the improved spurious performance of the SC
stage and the flexibility of pole/zero locations for active continuous-time filters.
However, it dissipates extra power, and moreover, additional noise is introduced by
the active components and the resistor in the filter.
5.2 Proposed Low-Power Active Switched-Capacitor Loop Filter
5.2.1 Sub-Threshold Inverter Amplifier
While SC filters are very popular in CMOS analog signal processing for their
high accuracy, conventional SC filters consume more power compared to their
continuous-time counterparts, because the amplifier bandwidth must be large enough
for adequate settling accuracy as discussed above.
In our design, to achieve good power-efficiency for an active SC loop filter,
sub-threshold inverters are used as the active components instead of the conventional
OTAs. In [66], Sigma-Delta data converters designed with class-C inverter SC
integrators demonstrates even lower power consumption than continuous-time ones.
Low power consumption for the amplifier can be achieved by setting the
active-element/inverter power supply voltage close to the sum of NMOS and PMOS
thresholds; then, the inverter operates in a class-C manner [66]. Since the transistors
in the inverter are in the weak-inversion region most of the time and the static current
99
is small, power consumption is reduced significantly. In deep-sub-micron CMOS
processes, a moderate gain can be obtained by using the cascode structure as shown
in Figure 5-6. The dependency of DC gain and bandwidth of a cascode inverter on its
power supply in a 0.18μm CMOS environment is plotted in Figure 5-7. In this CMOS
technology, the summation of NMOS and PMOS transistor threshold voltage (Vtn
and Vtp) is approximately 1.2V for the minimum 0.18μm channel length, when thick
oxide transistors are used to increase the output swing. The figure shows that if the
inverter is powered at the boundary of weak and strong inversion, large DC gain and
unity gain bandwidth can be obtained simultaneously. High slew rate can also be
obtained during the short transition period when one of the inverter transistors is
shifted into the strong inversion due to input voltage change. This provides a
promising way to build power-efficient SC circuits, especially considering the fact
that the output voltage swing of conventional OTAs continues to drop with the
advancement of semiconductor technology.
Figure 5-6: Cascode inverter amplifier
100
In order to investigate the reliability of this sub-threshold inverter amplifier,
Monte-Carlo analysis has been carried out in Cadence design environment for this
0.18μm CMOS technology. The distribution histograms for the DC gain and offset
voltage with the presence of process variations are depicted in Figure 5-8. Simulation
results indicate that the DC gain and offset voltage of the amplifier are normally
distributed with standard deviations of 5.8% and 2.2% of their average values, or
2.7dB and 12.1mV, respectively. Therefore, this structure is robust in this commercial
CMOS process. In order to increase the output swing of the amplifier which allows
for a reduced VCO sensitivity, high-threshold transistors with minimum length
180nm are used for the inverter input transistors and VA is set to 1.2V.
Figure 5-7: Relationship of DC gain and bandwidth on an inverter's power supply volatge
101
5.2.2 Design of the Low-Power Active Switched-Capacitor Loop Filter
The low-power active SC PLL loop filter is illustrated in Figure 5-9, along with a
pair of complementary charge pumps. It can be identified that an integration path and
a proportional path exist in the loop-filter depicted in Fig 1. The positive charge pump
current Iin and CS1 form the integration input and the proportional input comprises the
negative charge pump current –Iin, CS2, the source follower and C2. CC is used for
auto-zeroing operation to cancel the offset voltage and suppress amplifier's 1/f noise.
The timing diagram of different clock phases is shown in Figure 5-10. The clock
generator circuit consists of two D flip flops, some simple combination logic cells and
delay elements. Its schematic is also depicted in Figure 5-10. The Up and Down
Figure 5-8: Distribution of the amplifier’s DC gain and offset voltage with the presence of process variations
102
signals are the outputs from a classic phase/frequency detector. The durations of Φ2
and ΦRST are defined by the two delay blocks and they are determined according to
the input reference frequency.
In the loop filter, when the charge pump current sources are turned on, Φ1 is on,
and CS1 and CS2 are charged or discharged accordingly. During the next phase, Φ2 is
turned on and the charge is redistributed among the capacitors and a corresponding
Figure 5-9: Proposed switched-capacitor PLL loop filter with complimentary charge pumps
Figure 5-10: Clocks generator circuit and a set of example clocks
103
output voltage is established at the inverter output. This voltage is taken as the VCO
control voltage when the delayed Φ2 is on. When Φ2 and Φ2d are off, ΦRST is on and
CS2 is reset to VREF and the filter is ready for the next update cycle. It is clear from the
schematic that one control voltage update cycle consists of different phases. Since the
charging phase (Φ1) is isolated from the voltage output phase (Φ2d) and the net
charge injected into the loop filter is zero when the loop is locked, the matching
requirement on the n and p charge pump current sources is relieved since charge
pump current mismatch no longer introduces ripples in the VCO control voltage.
With a source follower gain of α, and assuming CS1=CS2=CS, the discrete-time
phase to amplifier output voltage transfer function (Φ2d switch not included) of this
loop filter is
( )-1/ 2-1/ 2
2-1
( )1-
S SCP
S I I
T C C zzH z KC C Cz
α⎛ ⎞⎜ ⎟= ⋅ ⋅ +⎜ ⎟⎝ ⎠
, (5-10)
where KCP= IIN/2π and TS is the update period or the reference period when the loop
is locked. If we use the relationship in Eq. (5-6), Equation (5-10) can be rearranged as
Eq. (5-11), where m=αC2/CS.
( ) ( )( )
21 2 sin 2 sin( )
2 sin 2S SS
CPI S
m T j m TTH j KC j T
ω ωω
ω⎛ ⎞+ + ⋅
= ⎜ ⎟⎜ ⎟⋅⎝ ⎠. (5-11)
In PLLs, the low-frequency response of the loop filter is of greater interest because
the PLL loop bandwidth should be less than 1/10 of the reference frequency for
stability concerns as discussed in Chapter 3. For these frequencies, we can assume
104
( )sin / 2 / 2S ST Tω ω≈ . (5-12)
With (5-12), the SC filter transfer function can be approximated by the following
continuous-time transfer function
( )( )1 21 1( ) z zCP
I
j jKH jC j
ω ω ω ωω
ω+ +
≈ ⋅ , (5-13)
where
( )21 2 2z Sm m m Tω ⎡ ⎤= + +⎢ ⎥⎣ ⎦
, (5-14)
( )22 2 2z Sm m m Tω ⎡ ⎤= − + −⎢ ⎥⎣ ⎦
. (5-15)
In Figure 5-9, the Φ2d switch performs a sample and hold function and it has a sinc
response. Assuming the holding time is much larger than the sampling time, the
complete phase-to-control voltage transfer function approximation should be
( )( ) ( ) / 21 21 1 sin 2
( )2
Sj Tz z SCP
I S
j j T eKH jC j T
ωω ω ω ω ωω
ω ω
−+ +≅ ⋅ . (5-16)
The sinc low pass filter has a strong impact on the filter's magnitude and phase
behaviors. In order to simplify the analysis, a single pole ωp = 2/TS is used to
approximate the sinc filter's low frequency behavior. The phase and gain responses of
the sinc and its approximation single pole filters are plotted in Figure 5-11. Their
differences at 1/10 sampling frequency are also shown and the small deviations verify
105
the validity of this approximation. With this method, the open loop gain of this SC
loop filter can be further approximated by
( )( )( )
1 21 1( )
1 /z zCP
I p
s sKH sC s s
ω ωω
+ +≅
⋅ + (5-17)
where s = jω.
Equation (5-17) carries the necessities for a type II PLL loop filter. Unlike the
passive SC filters, the DC pole is preserved by the active SC integration. The
stabilizing zero ωz1 is also well defined since TS is the reference period. In addition, a
redundant right half plane (RHP) zero ωz2 exists in this loop filter. However, this RHP
Figure 5-11: Phase and gain responses of the sinc and single pole filters
106
zero has negligible effects on the loop stability since it is at a frequency much higher
than the frequency of the stabilizing zero (m>>1).
The loop phase margin can be found easily from (5-18), as
1 1 1
1 2
tan tan tanc c cm
z z p
ω ω ωφω ω ω
− − −⎛ ⎞⎛ ⎞ ⎛ ⎞
= + − ⎜ ⎟⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠ ⎝ ⎠, (5-18)
where ωc is the unity gain frequency of the open loop. Since 2z pω ω≅ − , the phase
margin reaches its maximum when
( )1 1
1
22
p z z pc
p z
ω ω ω ωω
ω ω−
=−
. (5-19)
A loop filter is designed following the above analysis. Its magnitude and phase
responses from 10KHz to 10MHz are depicted in Figure 5-12 and 4-13. The loop
filter is designed for a 2.4GHz PLL with a 10MHz reference frequency. A 51 degree
phase margin is chosen. From Figure 5-12 and 4-13, it is clear that at frequencies
smaller than 1/(10TS), equation (5-17) is a good approximation for the original
transfer function and this proves that the series of simplifications used above is valid.
Loop filter circuit simulation is also carried out in Cadence and the results follow the
theoretical prediction well.
A transistor-level PLL is designed with the proposed low power active SC loop
filter in a 0.18um CMOS environment. The loop filter is implemented in a differential
configuration and a differentially tuned VCO is used. For a 10MHz input reference
frequency, the sub-threshold inverter amplifier consumes a static current of about
107
110uA under a 1.2V power supply. The increase of inverter power supply voltage can
give a larger bandwidth, but the current will also rise. The source follower buffer is
biased at about 50μA. Figure 5-14 shows the VCO control voltages when a ring
oscillator is used in the PLL. The reason for using the ring oscillator is simply for a
more clear view of the results since less PLL output signal is coupled onto the control
voltage compared to a LC VCO case. However, in the prototype, a LC VCO is
integrated on-chip. In Figure 5-14, the asymmetry of the differential control voltages
at circuit start-up exists because the common mode voltage is not well established
during that time. After that, the loop settles quickly since the loop bandwidth is large.
Figure 5-12: Magnitude response of the active SC loop filters
108
This loop filter separates the charge pump charging phase and the control voltage
output phase, and the sample and hold action also provides a magnitude notch for the
filter's transfer function at multiples of the sampling frequency, thus reference spurs
would be mainly caused by switch imperfections, such as switch charge injection and
clock feed-through. Reference spur levels caused by rectangular voltage disturbance
from the switches are analyzed quantitatively in next section. Several measures can
be taken to effectively reduce their impacts. First, switches near the virtual ground
node in Figure 5-9 should be turned off first to minimize distortion and gain error.
Second, with the use of a half-size dummy output switch in series with the Φ2d
Figure 5-13: Phase response of the active SC loop filters
109
switch, both charge injection and clock feed-through effects can be suppressed at the
output node. Finally, with a differential configuration, common mode errors, like
leakage current and the above two, can be effectively reduced.
5.2.3 Reference Spur and Noise of the Loop Filter
In order to investigate the reference spur problem caused by VCO control voltage
variations quantitatively, the narrow-band frequency modulation theory is applied
with the assumption that the variations are small. The VCO output voltage can be
expressed as
( ) ( )( )0 0cos
t
out m VCO CtrlV t A t K V dω τ τ= + ∫ , (5-20)
where Am is the voltage amplitude of the oscillator and ω0 is its initial frequency and
the initial phase is set to zero. Equation (5-20) can be expanded as
Figure 5-14: Transient response of VCO control voltages
110
( ) ( ) ( )( ) ( ) ( )( )0 00 0cos cos sin sin
t t
out m VCO Ctrl VCO CtrlV t A t K V d t K V dω τ τ ω τ τ⎡ ⎤= −⎢ ⎥⎣ ⎦∫ ∫ . (5-21)
Assuming ( )0 max 2t
VCO CtrlK V d πτ τ∫ , equation (5-21) reduce to
( ) ( ) ( )( ) ( )0 00cos sin
t
out m VCO CtrlV t A t K V d tω τ τ ω⎡ ⎤≈ −⎢ ⎥⎣ ⎦∫ . (5-22)
When the PLL is locked, the variation of the VCO control voltage can be
modeled as a disturbance pulse train with period of TS. In a switched-capacitor loop
filter, the disturbance is mainly contributed by switch charge injection and clock
feed-through. Assume each pulse is rectangular and its amplitude and duration are v0
and t0, respectively. The pulse train can be decomposed into Fourier series as
( ) 2 Sj kt TCtrl k
kV t c e π
∞
=−∞
= ∑ , (5-23)
where
[ ]
( )( )
0
0
2
0 0 02
2
02
00 0
0
1 ( 2) ( 2)
1
sin
SS
S
S
T j kt Tk T
S
t j kt T
tS
S
S S
c v u t t u t t e dtT
v e dtT
k t Tv tT k t T
π
π
ππ
− 2
−
− 2
−
= ⋅ + − − ⋅
=
=
∫
∫ , (5-24)
Since VCtrl(t) is a real signal, Equation (5-23) can be rearranged as
( ) ( ) ( )0 01 1
Re 2 cos 2 2 cosCtrl k S k refk k
V t c c kt T c c k tπ ω∞ ∞
= =
⎡ ⎤= + = +⎢ ⎥⎣ ⎦∑ ∑ . (5-25)
Ignoring the DC component in VCtrl(t), the phase deviation of Eq. (5-20) is
( ) ( ) ( )0 0
1 1
sin 22 cos 2 / 2
2t t S
VCO Ctrl VCO k S VCO kk k S
kt TK V d K c k T d K c
k Tπ
φ τ τ π τ τπ
∞ ∞
= =
Δ = = =∑ ∑∫ ∫ .
111
(5-26)
Substituting Eq. (5-26) into Eq. (5-22), we have
( ) ( ) ( ) ( )
( ) ( ) ( )
0 01
0 0 01
cos sin sin
1cos cos cos2
VCO kout m ref
k
VCO km ref ref
k
K cV t A t t k tk
K cA t k t k tk
ω ω ωπ
ω ω ω ω ωπ
∞
=
∞
=
⎡ ⎤≈ −⎢ ⎥⎣ ⎦⎡ ⎤⎡ ⎤ ⎡ ⎤= + + − −⎢ ⎥⎣ ⎦ ⎣ ⎦⎣ ⎦
∑
∑. (5-27)
Equation (5-27) indicates that spurs occur at offset frequencies of integer
multiple of input reference frequency. The magnitude of the spur at offset kωref is
( )0 0, 2
sin20log
ref
VCO Sspur k
ref
K v k t TP
kω
ππω
⎛ ⎞= ⎜ ⎟⎜ ⎟
⎝ ⎠. (5-28)
In order to reduce the spur power, one should reduce the amplitude of the VCO
control voltage ripple and a low sensitivity VCO is preferred.
Some principles regarding the size of capacitors can be obtained by investigating
output noise of this loop filter. Assuming the inverter amplifier has a transconductance
gm, and all the switches have the same on-resistance Ron, for the integration path, its
thermal noise power at the amplifier output node is given by
( )( )
( )( )
21
int, 21 1
2 22 1 2 1
on m on mSn
I S C on m S on m
kT R g kT R gC kTPC C C R g C R g
γ γ⎛ ⎞+ +≈ + +⎜ ⎟⎜ ⎟+ +⎝ ⎠
, (5-29)
where γ is a process-dependent coefficient. The first and second terms within the
bracket account for thermal noise during Φ1. The third term is the contribution during
Φ2. For the proportional path, its output thermal noise power is
( )( )
222
, 22 2
22 1
on mprop n
I S on m
kT R gC kTPC C C R g
γα⎛ ⎞+
≈ +⎜ ⎟⎜ ⎟+⎝ ⎠, (5-30)
112
where the noise contribution from the source follower is ignored. Equation (5-29) and
(5-30) indicate that to achieve a low output noise design, capacitor CI, CC and CS2
should be large and small CS1 and C2 are favorable. In practical designs, C2 are usually
much larger than CS1 in order to set the stabilizing zero at a proper location. Thus the
size requirement on C2 and CS2 is of more concern.
A low-power low-noise differential switched-capacitor loop filter is designed for a
prototype PLL based on the above analysis, with Figure 5-9 as a half circuit. The input
reference frequency is selected to be 10 MHz and the loop bandwidth is around 500
KHz. All capacitors in the design are below 10 pF. Two charge pumps with opposite
current polarity are used for this differential loop filter and the magnitude of each
current is around 100μA.
5.3 Other Building Blocks of the PLL Prototype
Function-level PLL blocks are covered in Chapter 3. Circuit details about each
block in the prototype are presented in this section.
5.3.1 Phase/Frequency Detector
The phase/frequency detector (PFD) used in this PLL prototype design is
illustrated in Figure 5-15. It is the state-machine architecture as described in Chapter
3 and widely used in literatures. The reset pulse duration is set by the delay block.
5.3.2 VCO
A differentially-tuned negative-gm LC VCO is designed to interface with the
differential loop filter in the prototype and its schematic is shown in Figure 5-16. The
complementary structure (cross-coupled p and n transistor pairs) used offers superior
113
phase noise performance and a smaller 1/f3 noise corner compared with the nMOS
only oscillator [67]. The on-chip octagonal spiral inductor is about 2.5nH and its peak
Q factor is about 14. RF simulation tool ASITIC is used to aid the inductor design.
Figure 5-15: PFD schematic
Figure 5-16: VCO schematic
114
For quick inductance estimation, 20L n rμ≈ can be used, where n is the number of
turns and r is the radius of the spiral in meters. Accumulation-mode MOS transistors
(nAMOS and pAMOS) are used as the differential tuning varactors [68].
Accumulation-mode MOS (AMOS) varactors operate in the depletion and
accumulation regions and the formation of the inversion regions is inhibited. It
exhibits performance better than diode or inversion-mode varators [68]. In order to
investigate the tuning characteristics of the AMOS varactors, Cadence Periodical
Steady-State (PSS) simulations have been carried out and the admittance parameters
(Y parameters) are obtained to derive the capacitance and quality factors of the
varactors. The relationships between the capacitance C/quality factor Q and the Y11
are found as
11Im( )YCω
= , (5-31)
11
11
Im( )Re( )
YQY
= . (5-32)
While for an inductor L, the relationships are
11Im(1 )YLω
= , (5-33)
11
11
Im(1 )Re(1 )
YQY
= . (5-34)
The tuning characteristics for the varactors are plotted in Figure 5-17. It can be
observed that the complementary varactors give a capacitance ranging from Cmin to
115
about 2Cmin. However, considering the parasitic capacitance in presence, the tuning
range of the VCO would be much smaller. Simulation results demonstrate that the
tuning characteristic of the VCO is very close to a straight line and no special
linearization technique is employed.
Many efforts have been carried out to model the phase noise performance of
oscillators and to optimize their designs. A widely used linear time-invariant phase
noise model is deduced by Leeson [69] as shown in Eq. (5-35).
( )3
21/0210log 1 1
2f
s
ffFkTL fP Q f f
⎧ ⎫⎡ ⎤ Δ⎛ ⎞⎛ ⎞⎪ ⎪Δ = + +⎢ ⎥ ⎜ ⎟⎨ ⎬⎜ ⎟ ⎜ ⎟Δ Δ⎢ ⎥⎝ ⎠⎪ ⎪⎝ ⎠⎣ ⎦⎩ ⎭ , (5-35)
where F is the empirical active device noise factor, k is Boltzmann constant, T is
Figure 5-17: Tuning Characteristics for the nAMOS and pAMOS varactors
116
temperature, Ps is output signal power, f0 is center frequency, Q is the loaded quality
factor of the resonator, Δf is the offset frequency and Δf1/f3 is the corner frequency of
1/f3 phase noise. The phase noise model is plotted in Figure 5-18.
A more accurate oscillator phase noise model based on linear time-varying
analysis is developed in [70][71]. With the impulse sensitivity function (ISF) Γ(x), the
expression for the single-sideband phase noise is
( )2 2
2 2max
10 log2
n rmsi fLq
ωω
⎛ ⎞Δ ΓΔ = ⎜ ⎟⎜ ⎟Δ⎝ ⎠
, (5-36)
where 2ni fΔ is the power spectral density of the parallel current noise, Γrms is the
rms value of the ISF associated with that noise source an qmax is the maximum signal
charge swing.
The above oscillator phase noise model becomes invalid when the frequency
offset approaches zero. A general noise model based on nonlinear perturbation
analysis is proposed in [72], where the errors of models based on linear analysis are
Figure 5-18: Phase noise model in Eq. (4-35)
117
eliminated. With the knowledge of oscillator phase noise, design strategy can be
obtained to optimize phase noise, which is subject to various design constraints [73].
5.3.3 Programmable Divider
The pulse swallow programmable divider is discussed in Section 3.2.3. Compared
with the dual-modulus prescaler, the M and A counters operate at relatively low
speeds; therefore they are implemented with simple true-single-phase-clock (TSPC)
flip flops. This section focuses on the design and implementation of the high-speed
prescaler.
The block diagram of the dual-modulus phase-switching prescaler in this design
is shown in Figure 5-19, where MC is the modulus control signal from the divider.
The first and second divide-by-2 stages are implemented with the source-coupled
logic (SCL) without tail current [74]. Four 90-degree-spaced outputs (in-phase,
quadrature, and their reverse signals) are generated and fed into the 4:1 Mux. If MC is
high, phase switching occurs and the Mux output will change from p1 to p2, p2 to p3,
p3 to p4 or p4 to p1. Otherwise, the Mux output remains the same as the previous
cycle. It can be identified that compared with the conventional design [75], the
Figure 5-19: Block diagram of the prescaler
118
switching sequence are reversed in this design to avoid output glitch [76]. Thus the
modulus is (P-1)/P instead of P/(P+1), where P is 8 in this design.
The phase select signals S1, S2, S3 and S4 are generated with a simple state
machine. Encoding the four phases p1, p2, p3, and p4 as states of Y1Y2=00, 01, 11,
and 10, respectively, the phase select signals can be described by the state machine
shown in Figure 5-20. The circuit employed to implement this state machine is shown
in Figure 5-21, where D1 and D2 are defined by simple combinational logic derived
by the state machine and the Karnaugh maps are shown in table 4-1 and 4-2.
By using a simple decoder, the select signals can be obtained from Y1 and Y2. In
this prescaler, a systematic phase mismatch exists in the physical implementation and
it can cause spurs in the PLL output spectrum. If the division ratio is a multiple of P,
the phase mismatch does not have an effect since no phase switching occurs. If the
scenario is a fractional-N divider employing ΔΣ modulation technique [77], the spur
problem is generally eliminated due to the random phase switching. Thus, the spur is
most significant when an integer division ratio which is not a multiple of P is present.
Figure 5-20: State machine for the phase select signals
119
However, by careful circuit design and layout for good symmetry and matching of the
prescaler components, the spurs caused by prescaler phase mismatch can be
suppressed to a negligible level [78].
5.4 Prototype Measurement Results
The PLL prototype is fabricated in a commercial 0.18μm CMOS process. The die
photo of the PLL prototype is shown in Figure 5-22. It takes a space of about 0.55 by
0.65 mm2, among which the low-power active switched-capacitor loop filter takes
about 0.3 by 0.25 mm2. The die is enclosed in a PGA package and an evaluation
board providing the power supplies and the reference voltage is constructed to
facilitate circuit testing.
Figure 5-21: Circuit implementing the state machine in Figure 4-20
Table 5-1: Karnaugh map for D1
Table 5-2: Karnaugh map for D2
120
Under the integer-N configuration, at an input frequency of 10 MHz and an output
frequency of 2.56 GHz, the PLL output phase noise is depicted in Figure 5-23. The
phase noise is -86 dBc/Hz at 100 kHz offset and -124 dBc/Hz at 3 MHz offset. At low
offset frequencies, the PLL's output phase noise increase gradually. With the large
division ratio N used, calculation results indicate that the input reference noise
dominates in-band phase noise and the increase is caused by the reference quality
degradation at low offset. Due to the Type II loop dynamics, phase noise peaking can
be observed in the figure. Loop bandwidth is found to be about 350 kHz. In the loop
filter, the differential inverter amplifiers consume 230μA under a 1.2V power supply,
and the two source followers consume 100μA with a 1.8V power supply. The entire
PLL consumes about 16 mW. The output spectrum of the PLL is shown in Figure
5-24. With an output of -6.7 dBm, the reference spur is about -64 dBc. Its
Figure 5-22: PLL die photo
121
performance is compared to PLLs implemented with other loop filter architectures as
given in Table 4-3. With reduced power consumption and chip area, the PLL
employing the active switched capacitor loop filter achieves comparable reference
spur and phase noise performance.
5.5 Chapter Conclusion
In this chapter, a fully integrated type-II differential PLL with a proposed
low-power active switched-capacitor loop filter is designed and verified. In order to
facilitate the design procedures, the complete continuous-time equivalent transfer
function including the sinc holding effect and noise issues for the loop filter are
presented. Design details for each PLL block are also covered. Measurement results
demonstrate that the loop filter consumes only 3% out of the total PLL power. Space
taken by the loop filter is small. This architecture provides a power- and cost-efficient
way for high-performance PLL on-chip integration.
Figure 5-23: PLL phase noise measurement plot
122
Figure 5-24: PLL output spectrum
TABLE 5-3 PLL PERFORMANCE COMPARISON
[61] [79] [80] This Work
Freq. (GHz) 2.4 2.4 3.6 2.5
Technology 0.25μm CMOS 0.18μm CMOS 0.18μm CMOS 0.18μm CMOSLoop Filter Structure Passive SC Passive SC Hybrid Active SC
Reference Frequency 1MHz 12MHz 50MHz 10MHz
Power (mW) ? 66 110 16
Area (mm2) ? 4.8 2.7 0.36
Reference Spur -62dBc -70dBc -45dBc -64dBc
Phase Noise -126dBc/Hz @2MHz
-125dBc/Hz @3MHz
-155dBc/Hz @20MHz
-124dBc/Hz @3MHz
123
Chapter 6
A Multi-bit ΔΣ ADC with a Low-Power SC
Nonlinearity-Suppressed DAC
As mentioned in Chapter 4, a multi-bit ΔΣ ADC can enhance loop stability and
improve SNR by reducing quantization noise power and allowing more aggressive
noise shaping. In a multi-bit ΔΣ modulator, the low-resolution quantizer is simple to
design since non-idealities introduced by the quantizer are shaped by the loop filter.
However, nonlinearity from the feedback DAC is not shaped by the loop filter and the
DAC should match the overall accuracy of the ADC. Otherwise, nonlinearity or
distortion in the feedback DAC would degrade the performance of the ADC directly.
In this chapter, the problems of existing methods proposed to construct the demanded
high-linearity feedback DAC are reviewed. We propose a low-power
nonlinearity-suppressed DAC method in this work and a multi-bit ΔΣ modulator
topology compatible with this proposed method is implemented and verified.
6.1 Existing Techniques to Enhance DAC Linearity
Component mismatch is an inherent property in semiconductor technologies. In
Section 2.2.2, it has been shown that in a charge-redistribution (capacitor-array) DAC,
capacitor mismatch and capacitance voltage dependency can introduce non-linearity.
124
The effect of voltage dependency can be suppressed by differential structure and is
usually small compared with that of mismatch. Thus in practice, existing solutions
focus on techniques which can compensate or correct mismatches among unit
capacitors in the DAC.
6.1.1 Layout considerations for capacitor matching
The capacitance of a capacitor is ideally defined by permittivity, thickness and
area of the dielectric. In CMOS processes, errors usually arise from two main factors
when realizing a capacitor [81]. The first is over-etching, which results in a smaller
actual area than that of the mask. This effect can be suppressed by implementing
large capacitors from combinations of smaller, unit-sized capacitors. Then the ratio of
capacitors is converted into ratio of numbers of unit capacitors. The second issue is
the gradient of the oxide thickness. The measure to counteract this problem is to use
the common-centroid layout of unit capacitors. This is to try to keep the gradient
effect the same for both the capacitors. However, in reality, ratios between two large
capacitors are arbitrary and large capacitors may not be decomposed into unit
capacitors of exactly the same size. But the effect of over-etching can still be
minimized when the perimeter-to-area ratios are kept the same, even if the capacitors
have different sizes. Using Cox to represent the unit area capacitance, x and y to
represent the length and width of a capacitor, Δe to represent the absolute
over-etching error, the actual capacitance can be given by
( )( )1 1 1oxC C x e y e= −Δ −Δ . (6-1)
The absolute capacitance error is
125
( ) 21 1 1oxC C e x y e⎡ ⎤Δ = Δ + −Δ⎣ ⎦ . (6-2)
Ignoring the high order error, the relative capacitance error is
1 11
1 1
x yx y
ε += . (6-3)
Therefore, if the perimeter-to-area ratio is kept constant for capacitors, the relative
error remains approximately the same. When a non-unit-size capacitor Ck is needed,
assume it is 1<K<2 times the unit-size capacitor Cu. Its length xk and width yk can be
found as shown below. We have
2k k k
u u
C x yKC x
= = . (6-4)
We want
2
2k k u
k k u
x y xx y x+
= . (6-5)
From Eq. (6-4) and (6-5), we have
2k k ux y x K+ = . (6-6)
2k k ux y Kx= . (6-7)
Therefore, xk and yk can be solved. With careful layout matching, the error in the ratio
of two capacitors can be as low as on the order of 0.1% [82]. Behavior-level
simulations for a ΔΣ modulator are carried out to examine the effect of component
mismatch. In Figure 6-1, the output spectrum of a ΔΣ modulator with a conventional
7-level capacitor-array DAC is depicted. With a mismatch standard deviation of 0.1%,
besides the signal peak at 50KHz, significant undesirable tones are observed.
126
Therefore, the above layout technique cannot yield sufficient matching accuracy for
high-resolution data conversion and auxiliary techniques should be employed.
6.1.2 Calibration
The component mismatch errors can be measured and compensated with the aid
of additional analog or digital circuits. This is known as the calibration technique. In
the analog domain, the component measurement can be carried out at the factory and
the calibrated configuration can be stored in some memory elements. To avoid the
high cost due to the additional factory manufacturing steps in the above method, at
the price of more circuit complexity, on-chip measurement hardware can be
integrated on the same die. Then the measurement can be performed at circuit startup
Figure 6-1 Output power spectral density for a multi-bit ΔΣ Modulator
using a conventional DAC with a component mismatch standard deviation of 0.1%.
127
and the calibrated configuration can be determined by on-chip signal processing
circuits [83][84]. The problem with this approach is that the additional hardware and
the desired signal processing algorithm may take large space and require enormous
design efforts. Instead of trying to match the analog components, the calibration
process can also be done in the digital domain. It requires similar measurement step
as in the analog calibration case, but the quantizer output is compensated by a digital
correction block preceding the final output [85]. In general, the calibration methods
add significant circuit complexity and moreover, it is not effective for mismatches
caused by environmental variations, for example, temperature change. More details
on different calibration techniques can be found in [86].
6.1.3 Dynamic element matching
The calibration technique tries to match DAC components statically by setting
their values to a best configuration for a specific environment. However, in practice,
circuit working condition changes and the dynamic element matching (DEM) method
can be adopted to counteract the limitations of calibration.
Many DEM techniques have been reported in literatures [87]-[93], from simple
randomization to complicated higher order noise shaping. Among these methods, data
weighted averaging (DWA) is most interesting and the most widely used in prototype
designs for its reduced complexity and first-order noise shaping capability. For a 3-bit
DAC consisting of 7 unit elements, the algorithm of DWA is illustrated in Figure 6-2.
The shaded square indicates the unit elements in use and the blank square is the unit
elements not used. A register is used to store the position of the last unused unit
128
element (pt as shown in the figure). The summation of the current input code
xDAC(n)=(0 to 7) and the register value gives the next position of the last unused unit.
It has been analytically proven that this algorithm provides a first-order high-pass
mismatch shaping. Therefore, compared with the simple randomization method, the
additional in-band noise arising from tone spreading can be much smaller. When the
amplitude of input signal rises to a certain level, however, harmonic distortions in the
DAC output spectrum increase severely. But when the input signal amplitude gets
even larger, the distortions will start to reduce. This phenomenon causes significant
SNDR degradation for input signals within a certain range and is known as the
in-band tone problem. This problem is related to the interaction between the
pseudo-randomizations of the ΔΣ modulation and DWA. The SNR degradation effect
is influenced by the matching of the unit elements and other circuit parameters, such
as the finite gain of the amplifier and DC offset [94][95]. Considering its dependency
on element matching, it is argued that if the element matching is good enough (better
than 0.1%), then DAC error and distortion would be too small to degrade modulator
SNR. On the other hand, the noise floor also varies with the input signal amplitude in
Figure 6-2 Element selection algorithm for DWA
129
DWA due to the DAC error changes. This also requires sufficient good matching of
unit elements in implementation, so as to keep the noise floor variations small and
masked by other noise sources, for example, thermal noise. Unfortunately, in practice,
it is difficult to achieve the required matching accuracy without the help of calibration.
Therefore, SNR degradation for a certain range of input levels is often observed for
DWA in literatures. Though many approaches have been proposed to solve this
problem, an effective solution is still absent.
6.2 ΔΣ ADCs with Low-Power Nonlinearity-Suppressed DACs
Component mismatch is a major source for nonlinearity in DACs built with unit
element arrays. On the other hand, if the DAC can be made independent on ratioed
components, the circuit linearity would not depend on component mismatch either.
This implies that the DAC linearity can be improved by ways other than element
matching, on which calibration and DEM techniques are based. In Section 6.2.1, the
ratio-independent multiply-by-N circuit is used as the feedback DAC for a multi-bit
ΔΣ ADC. To improve power efficiency, in Section 6.2.2, a new
nonlinearity-suppressed DAC is proposed based on a gain-boosted inverter amplifier.
A multi-bit ΔΣ ADC topology suitable for employing this new DAC is presented.
6.2.1 Switched-capacitor ratio-independent multiply-by-N circuit
A switched-capacitor (SC) ratio-independent multiply-by-two circuit was first
built for algorithmic analog to digital converters as stated in [96]. The
fully-differential ratio-independent multiply-by-two circuit and the corresponding
clock sequences are shown in Fig. 6-3. A multiply-by-two operation can finish in 4
130
phases: 1) input sampling, 2) charge transfer, 3) second sampling and 4) charge
summation. It can be observed that by repeating phases 2 and 3 (N-1) times prior to
phase 4, a ratio-independent multiply-by-N function can be achieved. Then the output
voltage can be any integer multiple of the input reference, and therefore this circuit
can be used as a DAC. A simple logic control module can be employed to control the
switches. Thus a proper output voltage can be obtained according to each digital input
code.
The accuracy of this circuit depends on the completeness of charge transfer
between the two capacitors, which is limited by the finite DC gain of the op amp. In
algorithmic ADC’s, since the multiplied signals are quantized directly, absolute errors
in the multiplied results are critical, resulting in a stringent requirement on the
Figure 6-3 Ratio-independent multiply-by-two circuit
131
opamp's DC gain. On the other hand, when this circuit is used as a multi-level
feedback DAC in ΣΔ modulators, it is the linearity among the output multiples that is
critical. Though other non-idealities such as gain deviation and DC offset are also
present in the DAC outputs, the former can be compensated by loop filter coefficients
very easily if necessary and the latter will be simply represented as a modulator
offset.
In order to investigate the linearity dependency on the opamp DC gain, the
transfer function is derived for this DAC circuit in the single-ended configuration. It
can be shown that the DC offset of the amplifier can be cancelled. For an op amp DC
gain of A0, ignoring capacitance voltage dependency, the output voltage for
multiply-by-N can be expressed as
1 2_( 1) 2( )N in C NV V C V Cα −= ⋅ ⋅ + ⋅ , for N≥2, (6-8)
where Vin is the input reference voltage and
0
0 1 2(1 )A
A C Cα =
+ ⋅ +. (6-9)
VC2_(N-1) is the voltage across C2 at the end of the next-to-last phase and
2_ 1 2_( 1) 2( )C N in C NV V C V Cβ −= ⋅ ⋅ + , for N≥2, (6-10)
with
0
0 2 1
1(1 )
AA C C
β +=
+ ⋅ +, (6-11)
and for N=1
0 12_1
0 2 1
(1 )(1 )
inC
V A CVA C C⋅ + ⋅
=+ ⋅ +
. (6-12)
132
For a standard 3-bit DAC used in a fully differential ΣΔ modulator, the ideal
eight output levels are [-7Δ, -5Δ, -3Δ, -Δ, Δ, 3Δ, 5Δ, 7Δ], where Δ is 1LSB. With the
Eq. (6.8) through (6-12), the 7 DAC output levels can be calculated. During the
calculation, the op amp DC gain of 60dB and 5% capacitance mismatch between C1
and C2 are assumed. A maximum feedback of 3 volts is used. For comparison purpose,
the corresponding values on the best-fit straight line are also derived. Figure 6-4 (a)
shows the deviation away from the linear levels for this 3-bit DAC. It can be observed
that the magnitude of deviation is comparable to that caused by 0.1% component
mismatch. This DAC circuit can be improved in different ways, in terms of power
consumption and linearity. The transfer characteristics for the 3-bit and 7-level
Figure 6-4 (a) Linearity deviation for the 3-bit DAC
Figure 6-4 (b) Linearity deviation for the 7-level DAC
133
quantizers are plotted in Figure 6-5. With one level less, the outputs can be arranged
as [-3(2Δ'), -2(2Δ'), -(2Δ'), 0, (2Δ'), 2(2Δ'), 3(2Δ')]. A maximum multiplication
number of 3 is required instead of 7 in the 3-bit case. Much fewer multiplications are
in need and the linearity for this 7-level DAC is plotted in Figure 6-4 (b). Much
smaller non-linearity is observed compared to the standard 3-bit DAC case and
settling requirement is relieved. If an op amp with DC gain of 92dB is used, the
maximum deviation reduces to less than 8 micro volts for the 7-level configuration.
With the capacitor-multiplex technique proposed in [97], an op amp with moderate
DC gain can be used, at the cost of extra on-chip area for additional capacitors. From
the analysis above, it can be concluded that the switched-capacitor multiply-by-N
DAC can produce highly linear feedback signals suitable for ΣΔ modulators. The
standard 3-bit multiply-by-N DAC is used in the verification circuit.
A 3-bit 3rd-order fully-differential ΣΔ modulator with two different DACs was
(a) 3-bit (b) 7-level
Figure 6-5 Transfer characteristics for different quantizers
134
built on printed circuit boards to verify the former argument. One DAC is the
ratio-independent multiply-by-N circuit and the other one is a voltage ladder built
with 1% tolerance resistors. According to the previous analysis, though not best, the
standard 3-bit multiply-by-N DAC should provide obvious improvement for
verification purpose. The discrete op amps used in the switched-capacitor integrators
and the multiply-by-N DAC are all the TI THS4121 with a typical DC gain of 66dB.
Though the distortion performance may be a concern according to its specification,
the amplifier used is one of the few fully differential CMOS op amps available in the
market and the input amplitude was kept low during testing.
The modulator topology used for implementation is illustrated in Figure 6-6.
Coefficients of 0.51, 0.51 and 1 are used for K1, K2 and K3, respectively. Simulation
results show that these coefficients result in both good noise shaping performance and
reasonable stable input range for the 3-bit modulator. With the maximum stable input,
the outputs for all three stages are close to full scale and a dynamic range scaling was
considered not necessary. Considering the fact that the selected op amp is not
optimized for switched-capacitor applications, a large integration capacitor of 1nF
Figure 6-6 Sigma-Delta modulator topology
135
was used for the loop filter. A large capacitor can also reduce the impact of pad
capacitance in this discrete component implementation. All the capacitors used have a
rated tolerance of 5 percent. φ1 is the input sampling phase for the integrators.
The schematic of the quantizer used in this modulator is shown in Figure 6-7. It
consists of 7 comparators. Fourteen 1% tolerance resistors form a resistor ladder,
which not only provides comparator reference inputs but also serves as the resistor
Figure 6-7 Quantizer Schematic
136
ladder DAC. The reference and feedback levels are taken from different nodes in the
ladder. The same op amps are used in the pre-amplification stage. One quantization is
finished in two phases. During φ1, the 7 capacitors are charged to the corresponding
reference levels. During φ2, the difference between the input signals and the reference
levels are amplified and the results are latched into the flip flop on the edge of φlat.
Eight output codes representing the quantization results are then available after the
exclusive OR operation. For the resistor ladder DAC case, these output codes control
the feedback switches directly. For the multiply-by-N DAC case, these codes are fed
into the digital logic module and the proper clock signals for the switched-capacitor
circuits will be generated. φ1 and φ2 are the same clock signals as in the integrators.
A fully differential multiply-by-N circuit was built with the op amp mentioned
above. The standard 3-bit multiply-by-N DAC as described was used. Thus the DAC
should be able to output 3, 5 and 7 multiples of its input. Polarity for output signals
can be inverted by changing the switch pairs at the input. The number of
multiplications to be carried out for each feedback signal is determined by the
switching sequences generated by the digital logic module.
To achieve better performance, surface mount components were used for this
circuit, including capacitors and resistors. The IC used to provide the 3V Vref is the
ultra-low-noise voltage reference ADR443 by Analog Devices, Inc. The logic control
module for the multiply-by-N DAC was implemented on an FPGA device, coded
with VHDL.
Circuit testing for this PCB prototype was carried out. A modulator sampling
137
frequency of 40 KHz was used to guarantee sufficient op amp settling with the large
load. In integrated circuit design, much smaller loads are expected thus sampling
frequency good for audio applications are readily achievable in ICs. The input to the
modulator was generated by DS360, which is a low distortion function generator by
Stanford Research Systems, Inc.
Using an input signal with 0.3V amplitude and a frequency of 200Hz, the
modulator output spectra for the resistor ladder DAC and multiply-by-N DAC are
plotted in Figure 6-8 and Figure 6-9, respectively. Onboard jumpers are used to
switch between the two DAC's, leaving the loop filter and quantizer the same.
Comparing the two figures, by using the multiply-by-N DAC, suppression for
different order harmonics is observed and significant distortion performance
improvement is achieved. This is consistent with the theoretical analysis performed in
Section II. Since a standard 3-bit multiply-by-N DAC was used in this verification
circuit, the linearity can be potentially improved further by using the 7-level
configuration.
Compared to the conventional capacitor-array DAC, less on-chip area may be
required by using this switched-capacitor multiply-by-N DAC. However, more power
is burned in the multiply-by-N DAC. If the 7-level scheme mentioned in Section III is
used, 6 multiplication phases should complete in half to one modulator sampling
cycle, depending on the speed of the integration op amps. This means the op amp in
the multiply-by-N DAC must be able to settle three to six times faster than the
integration op amps. This is the main drawback of this method.
138
Figure 6-8 Modulator output power spectral density using the resistor ladder DAC.
Figure 6-9 Modulator output power spectral density using the resistor ladder DAC.
139
6.2.2 Low-power SC nonlinearity-suppressed DAC
With the ratio-independent method, the in-band tone problem as in the DWA
techniques is eliminated, since this is not based on the pseudo-random selection of
unit elements. However, the high power consumption of the above ratio-independent
DAC still hinders its application. In this section, we show that the
power-consumption of the method can be reduced to a very low level with the use of
the low-power nonlinearity-suppressed DAC proposed below, which can make the
multi-bit ΔΣ ADC designs utilizing the ratio-independent DAC more practical.
6.2.2.1 Gain-Boosted Inverter Amplifier
It has been shown in [98] that a class-C inverter powered close to the sum of
NMOS and PMOS threshold voltages exhibits both a moderate DC gain and a large
unity-gain bandwidth. The input transistors can enter saturation region dynamically
thus the desired slew rate can also be obtained. Since the inverter stays in the weak
inversion region most of the time, its power consumption can be even lower than
continuous-time filters. The performance of a class-C inverter based amplifier is
analyzed in [98], which also demonstrates that its performance is sufficiently good to
replace SC integrator operational-transconductance-amplifiers (OTAs) in several ΣΔ
modulators. However, in ratio-independent applications, circuit performance relies on
amplifiers' high DC gain which a simple class-C inverter cannot provide. For a 1.2V
signal swing, a 16-bit accuracy corresponds to a LSB/2 of 9.2μV. An amplifier DC
gain of about 90dB is required to achieve this accuracy using the ratio-independent
method. But a minimum length cascode sub-threshold inverter in a 130nm technology
140
can only provide a DC gain of about 40dB, or 8-bit accuracy. Thus the gain-boosted
inverter amplifier is proposed as shown in Figure 6-10. The inputs of the top and
down transistors are connected together as the amplifier input to maintain high DC
gain for entire rail-to-rail span of input signals. Also, the power supply VA is selected
to be close to the sum of threshold voltages. Since the gain boosting amplifiers have
much smaller loads than the main amplifier stage, they can be biased at small currents
and still maintain sufficiently large bandwidth to assure fast settling (i.e., their
bandwidth should be larger than the SC circuit's closed-loop -3dB bandwidth.). In a
commercial 0.13um CMOS process, with a static current of 100μA for the inverter
and 25μA for each of the gain boosting amplifiers, a DC gain of 90dB and a unity
gain frequency of 100MHz for a 5pF load are achieved. Simulation results also
indicate that the amplifier's bandwidth depends on static current linearly, instead of
the square-law relationship in conventional OTAs. Thus power efficiency can be
greatly improved especially for high frequency applications.
Figure 6-10 Gain-boosted inverter amplifier
141
Since this amplifier is powered at a relatively low power supply voltage, another
concern is the output voltage swing which a large enough gain can support. Two
measures are taken to enhance its output voltage swing. First, high threshold
transistors (with length of 120nm) are selected as the input transistors, thus even with
a relatively high VA=1.2V applied, they still operate in the sub-threshold
(weak-inversion) region. Second, regular transistors with lower threshold values are
selected for the cascode ones; therefore, when biased close to rails, they can remain in
saturation. The voltage transfer characteristic of the gain-boosted inverter is plotted in
Fig 6-11 using Cadence Spectre in a commercial 130nm CMOS process. It can be
observed that for a DC gain of 89dB, the output voltage swing is more than 600mV.
The gain is almost constant in that range. With a sufficient gain, bandwidth and a
reasonable output swing, this very-low-power amplifier is a proper alternative to
Figure 6-11 Voltage transfer characteristic of the gain-boosted cascode inverter
implies a large-gain differential output swing of more than 600mV
142
conventional OTAs, whose output voltage swings shrink quickly with technology
scaling.
In order to investigate the reliability of this amplifier, a 500-run Monte Carlo
analysis has been carried out in the Cadence design environment. The gain and offset
voltage distributions are illustrated in Figure 6-12. Simulation results show that with
the presence of process variations, the offset voltage (amplifier output when input and
output are shorted) and DC gain are normally distributed with standard deviations of
3.6% and 1.6% of their mean values, or 24.1mV and 1.4dB, respectively. It can be
concluded that this structure is robust in this commercial 0.13μm CMOS process.
6.2.2.2 Nonlinearity-suppressed DAC
A half-circuit schematic of the analog part of the proposed
nonlinearity-suppressed DAC using the low-power amplifier described above is
shown in Figure 6-13. The timing scheme for a triple output is also plotted. Cp1, Cp2
Figure 6-12 Gain and Voff varation statistics due to process varactions
143
and Cp3 are the parasitic capacitance at the corresponding nodes. When Φrst is on, C2
is charged to the offset voltage of the inverter Voff. During Phase 1 (Φ1 on),
depending on the digital input word, one set of the input switches (Φ1x and Φ1xd, x =
a, b or c) will be turned on. C1 will be charged to Vref=Vp-Vn, -Vref=Vn-Vp or 0.
Charge will be transferred onto C2 during phase 2 (Φ2 on). An output of Voff ± Vref
or Voff is expected ideally, assuming C1=C2. With the repetitions of Phase 1 and
Phase 2, outputs of Voff ± 2Vref, Voff ± 3Vref and so on can be obtained. A digital
clock control module is also included in the DAC. Based on the input word to the
DAC, it gives the correct clocks to each switch, thus the correct number of charge
transfers can be carried out. The clock control module consists of shift registers and
some simple combinational logics.
It can be seen that Cp2 is either connected to ground or virtual ground, thus its
effect can be ignored. Cp3 can also be ignored due to the same principle. With a finite
Figure 6-13 Schematic of the proposed non-linearity-suppressed DAC (Analog Part)
144
amplifier DC gain A0, assuming Φ1a and Φ1ad are used for input, it can be shown
that the output voltage VN after N charge transfers is
0 1 1NN offV V m m m −= + ⋅Δ + ⋅Δ + ⋅⋅⋅+ ⋅Δ , (6-13)
where
( )( ) ( )
1 1
0 2 1 1 01 1/ /p n nV V C V CpA C C Cp A− ⋅ − ⋅
Δ =+ ⋅ + +
, (6-14)
and
1 1
2 0
1
1(1 )
m C CpC A
=+
++
. (6-15)
By replacing Vp with Vn in Eq. (6-14) and vice versa, the transfer function for
reversed input polarity (Φ1c and Φ1cd used for input path) can be obtained.
Comparing expressions for different input polarities, it can be observed that this
circuit is insensitive to mismatches between Vp and |Vn|, as long as Cp1 is much
smaller than C1, since Vp and Vn are referred to each other on C1 and the mismatch
only has an influence on Cp1. This is the benefit from using multiple Φ1 (Φ1a, Φ1b
and Φ1c) switches at the virtual ground node. On the contrary, if only one Φ1 switch
is used at that node (as shown in Figure 6-14), it will be connected to ground and Cp1
can also be ignored. Though the output would have a smaller gain error, a positive
and a negative reference voltage (Vrefp and Vrefn) referred to ground are required
and the mismatch will be applied on C1, and the circuit will be more sensitive to
reference voltage mismatch.
In order to evaluate the linearity of this DAC, equation (6-13) can be rearranged
145
as
1 (1 )N N offV m V m V−= ⋅ + Δ + − ⋅ . (6-16)
Equation (6-16) implies that the value of the linear coefficient m is not affected by the
ratio between (C1+Cp1) and C2 significantly, provided that A0 is large enough. In
order to satisfy this condition, the gain-boosted amplifier is required in the DAC. On
the other hand, the mismatch and the parasitic capacitance could introduce gain and
offset errors to the circuit, as denoted in (6-14) and (6-15). However, their effects can
be tolerated in ΔΣ data converters.
As discussed previously, a standard 3-bit quantizer has a transfer characteristic
shown in Figure 6-5 (a). A maximum of 7 charge transfers is required in this topology
to generate a proper analog output since a 3-bit (or 8-levels) feedback DAC is in need.
To reduce speed requirement and improve poer efficiency, the 7-level DAC is
adopted since the maximum number of charge transfers is reduced to 3.
In the modulator design, a 7-level differential highly linear DAC is constructed
with Figure 6-12 as a half circuit. In this differential design, mismatches between the
Figure 6-14 A DAC with one virtual ground Φ1 switch
146
two half circuits can cause inconsistency in circuit parameters. A 500-run Monte
Carlo analysis in the design environment shows that, with the presence of instance
mismatches, the offset voltage and the DC gain of the gain boosted inverter amplifier
are normally distributed with a standard deviation of 0.2% and 1.4% of their average
values, or 1.3mV and 1.2dB, respectively. More critically, they have a negligible
effect on linearity, as long as the difference in the offset voltages is present in all the 7
differential output levels. This can be assured by using one half-circuit as the positive
output at all times and the other one as the negative output. This is also the reason for
that the polarity switching is implemented at the input of the DAC and not the output.
A behavior model is defined in MATLAB for the DAC. Along with the amplifier
statistic properties mentioned above, the positive and negative reference voltage
mismatch and capacitor ratio mismatch in the differential DAC are assumed to have a
0.5% standard deviation, which is readily achievable in CMOS processes. An average
DC gain of 88 dB is assumed. Differential output voltage swing is about 1.2V. A
1000-run Monte Carlo analysis indicates that the mean of each level's absolute
deviation from the best fit straight line plus 3 times standard deviation (which covers
99.7% of all cases) is less than 5.2μV for the multiple Φ1 switches design and 9.5μV
for the single Φ1 switch design as shown in Figure 6-15. For the multiple Φ1
switches, the deviation value is 5μV and 6.5μV for perfect reference/cap matching
and 1% mismatch cases, respectively. It can be concluded that the DAC linearity is
not sensitive to circuit mismatches, especially for the multiple Φ1 switches design
shown in Figure 6-12.
147
Transistor level simulation is also carried out in Cadence Spectre. To reduce
output noise, C1 is selected to be about 4pF and C2 is twice the size of C1. The
transistor and capacitor mismatches between the two half circuits are randomly
assigned within 1%. Transistor level simulation confirms that the linearity of the
differential outputs is insensitive to circuit mismatches.
Figure 6-15 Linearity deviation plots
Figure 6-16 Block diagram for the logic and clock control circuits
148
The block diagram for the logic and clock control block in the ΔΣ modulator is
shown in Figure 6-16. RN is the reset signal. The input clock Clk is set to four times
the modulator sampling frequency, or 8 MHz. It goes through a 2-bit counter and
some combinational logics for the generation of ΔΣ integrator clock signals, Pint1 and
Pint2, and quantizer clock signals, PQ1 and PQ2, all at the ΔΣ sampling frequency. The
Prst signal is the reset clock for the DAC (Φrst) as shown in Figure 6-13. PDAC is an
intermediate clock composed of all the phases required for the maximum number of
Figure 6-17 Schematic of the DAC logic control circuits
149
DAC charge transfers. The six phases of the PDAC are completed during one ΔΣ
sampling period. A DACCLKMSK signal is generated by the DAC logic control block
(whose schematic is shown in Figure 6-17). This control block assures that the DAC
carry out a correct number of charge transfers based on the input digital word [A0:A6].
PDACd is delayed PDAC to avoid clock glitches.
The DACCLKMSK signal is defined by three mask pattern bits D0, D1 and D2,
which controls the number of charge transfers to be carried out. Since the first charge
transfer occurs for all [A0:A6] values, D0 is set to 1 permanently in the circuit, which
is accomplished by tying the R input of the left most flip-flop (the first pattern bit for
next DAC operation cycle) to VDD in the schematic. When a digital word is available
from the ΔΣ quantizer, the other two mask pattern bits D1 and D2 are then computed
from [A0:A6], and fed into the parallel to serial shift registers. Clocked by the PDAC
signal, the desirable DACCLKMSK waveform is obtained from the shift register.
6.2.2.3 Noise analysis for the nonlinearity-suppressed DAC
In order to investigate its noise, the gain boosted amplifier illustrated in Figure
6-10 is redrawn with noise sources as depicted in Figure 6-18 (a). With e2n1 and e2
n2
as the input-referred noise voltage for the input transistors, M1 and M2 are noise-free
transistors. The noise contribution from M3 and M4 and the gain-boosting opamps
are negligible due to the cascode structure. Replacing the cascode stage with its
effective output impedance, the small signal equivalent circuit for the amplifier can
be drawn as in Figure 6-18 (b). Ro3 and Ro4 are defined by
150
( )( )1 3 3 3 1 3 3 3 3 11 1o m o B o o B m o oR g r A r r A g r r= + + + ≈ , (6-17)
( )( )2 4 4 4 2 4 4 4 4 21 1o m o B o o B m o oR g r A r r A g r r= + + + ≈ . (6-18)
The output noise is found to be
( )( )22 2 2 2 21 1 2 2 1 2out m n m n o oe g e g e R R= + . (6-19)
The input-referred noise voltage can be obtained as
( ) ( ) ( )
2 2 2 2 22 1 1 2 2
2 2 21 2 1 2 1 2
out m n m nin
m m o o m m
e g e g eeg g R R g g
+= =
+ +. (6-20)
Assume perfect matching among the n and p transistors, or gm1=gm2=gm/2, the
input-referred noise voltage can be simplified as
2 22 1 2 2
2 2 / 2n n
inm
e e kTeg
γ= = = , (6-21)
where γ is 1/2 for a weak inversion transistor and 2/3 for strong inversion.
(a) (b)
Figure 6-18 Amplifier schematic and equivalent circuit for noise analysis
151
During the reset phase, the equivalent circuit for the DAC with noise sources
indicated is shown in Figure 6-19. For the input capacitor C1, its noise power is
simply kT/C1. The right half circuit have multiple noise sources at different nodes.
Noise introduced to C2 by Rra, Rrb and the amplifier can be found by investigating the
transfer functions.
Considering noise of Rra first, the small signal equivalent circuit for the right half
circuit in Figure 6-19 is depicted in Figure 6-20. Equation set (6-22) can be obtained
by applying Kirchhoff laws on to the circuit and the transfer function from VC2 to Vin
can be found as Eq. (6-23).
Figure 6-19 The equivalent circuit for the DAC during the reset phase
Figure 6-20 The equivalent circuit for noise of Rra
152
( )( ) ( )( )
( )( )
1 1 2
2 2 1
1 , 1 1
2 2 2
1m
C rb
in ra C m ra
C
g V I I
I sC I sC R
V V I sC g V R
V I sC
= − +⎧⎪
= +⎪⎨
= + −⎪⎪ =⎩
. (6-22)
( )( )
( )( ) ( )( )
22
, 2 2
11 1
C m rb C
in ra m ra C rb m ra C m
V s g sR CV s s g R C C R s g R C C g
+= −
+ + + + +. (6-23)
The total noise power on C2 due to Rra is found to be
( )( )
( )( )( ) ( )
( )( ) ( ) ( )
2
2
2, , 0
,
22
2 2
2
22 2 2
1 42
1
1
1 1
Cn C ra ra
in ra
m m ra m rb Cra
m ra C
m ra m ra rb C
m ra C m ra C
V jP kTR d
V j
g C g R g R CkTR
g R C C C
g R g R R CkTg R C C g R C C C
ωω
π ω∞
=
+ +=
+ +
⎛ ⎞= +⎜ ⎟
⎜ ⎟+ + + +⎝ ⎠
∫
, (6-24)
Similarly, the noise power on CC due to Rra is calculated as
( )( ), ,21
m ran Cc ra
m ra C
kTg RPg R C C
=+ +
. (6-25)
Figure 6-21 The equivalent circuit for noise of Rrb
153
The small signal equivalent circuit for noise from Rrb is depicted in Figure 6-21.
The equation set describe its behavior is given by Eq. (6-26). Its transfer function can
be found similarly as Eq. (6-27).
( )( ) ( )( )
( )( )
1 1 2
2 2 1 ,
1 1 1
2 2 2
1m
C rb in rb
C m ra
C
g V I I
I sC I sC R V
V I sC g V R
V I sC
= − +⎧⎪
= + +⎪⎨
= −⎪⎪ =⎩
. (6-26)
( )( )
( )( ) ( )( )
22
, 2 2
11 1
C m C m ra
in rb m ra C rb m ra C m
V s g sC g RV s s g R C C R s g R C C g
+ += −
+ + + + +. (6-27)
The total noise power on C2 due to Rrb is found to be
( )( )
( )( )( )( )
( ) ( )( )
2
2
2, , 0
,
2
2 2 2
2 1 2 1 2
1 42
11
1
Cn C rb rb
in rb
C m ra m rbrb
m ra rb
C m rb
m ra
V jP kTR d
V j
C g R g R CkTR
g R C C C R
C g RkTC C C g R C C
ωω
π ω∞
=
+ +=
+ +
⎛ ⎞= +⎜ ⎟⎜ ⎟+ + +⎝ ⎠
∫
. (6-28)
Similarly, the noise power on CC due to Rrb is calculated as
( )2
, ,2
n Cc rbC C
kTCPC C C
=+
. (6-29)
The small signal equivalent circuit for noise from the inverter amplifier is
depicted in Figure 6-22. Its transfer function is found to be Eq. (6-30), based on the
equation set which describe its behavior given by Eq. (6-31).
( )( )
( )( ) ( )( )
22
, 2 2
11 1
C m rb C
in amp m ra C rb m ra C m
V s g sR CV s s g R C C R s g R C C g
+=
+ + + + +. (6-30)
154
( )( ) ( )( )
( )( )
1 1 2
2 2 1
1 ,
1 1
2 2 2
1m
C rb
x in amp
x m ra C
C
g V I I
I sC I sC R
V V V
V g V R I sC
V I sC
= − +⎧⎪
= +⎪⎪ = −⎨⎪ = − +⎪⎪ =⎩
. (6-31)
Therefore the noise power on C2 due to the amplifier can be calculated from Eqs.
(6-21) and (6-30) as
( )( )
( )( )( ) ( )
( )( ) ( ) ( )
2
2
2, , 0
,
22
2 2
22 2 2
1 42
1
1
11 1
Cn C amp rb
in amp
m m ra m rb C
m m ra C
m rb C
m ra C m ra C
V jP kTR d
V j
g C g R g R CkTg g R C C C
g R CkTg R C C g R C C C
ωω
π ω
γ
γ
∞=
+ +=
+ +
⎛ ⎞= +⎜ ⎟
⎜ ⎟+ + + +⎝ ⎠
∫
. (6-32)
Similarly, the noise power on CC due to the amplifier is calculated as
( )( ), ,21n Cc amp
m ra C
kTPg R C C
γ=
+ +. (6-33)
Assuming gmRra<<1, gmRrb<<1, and CC is comparable with C2, then the
Figure 6-22 The equivalent circuit for noise of the inverter amplifier
155
approximated total noise power on C2 during the reset phase is
2
2, ,
2
Cn C rst
C
C CP kTC C
γ⎛ ⎞+≈ ⎜ ⎟+⎝ ⎠
. (6-34)
The approximated total noise power on CC during the reset phase is
2, ,
2C
Cn C rst
C
C CP kTC C
γ⎛ ⎞+≈ ⎜ ⎟+⎝ ⎠
. (6-35)
The reset phase happens once for each output level calculation cycle. Additional
sampling phases don't change the sampled noise on CC and the accumulated noise on
C2 since charge on these two capacitors does not change during the sampling phase.
For each additional sampling phase, the noise on C1 will increase by kT/C1.
During the charge transfer phase, assuming R=R1a+R1b, the small signal
equivalent circuit for the DAC is depicted in Figure 6-23. The equation set describing
Figure 6-23 The equivalent circuits for DAC charge transfer phase
156
its behavior is found to be
( )
1 2 2
, 1 ,2 2
11
m C
in r Cc in ampC
g V sC VV V V V
sC VR sC
= −⎧⎪ − − −⎨ = −⎪ +⎩
. (6-36)
Then circuit transfer function from noise inputs to VC2 is found to be Eq. (6-37) and
the -3dB bandwidth is ω-3dB=1/(C1(R+1/gm)).
( )( ) ( ) ( ) ( )
2 1
, , 2 1
11 1
C
in r Cc in amp m
V s CV s V s V s C sC R g
= −− − + +
. (6-37)
The noise sampled onto CC during the reset phase does affect the total noise. The
voltage across CC doesn't change during the charge transfer phase since one plate of
the capacitor is open. Thus it's a DC signal after the reset phase and the noise increase
on C2 contributed by VCC is calculated as
( )( )
22
2 1, , , , 2
2
00
Cn Cc rst n Cc rst
Cc
V s CP PV s C
==
=. (6-38)
Since the resistor noise and amplifier noise are uncorrelated, based on Eq. (2-49)
and (6-37), the total noise power increase on C2 during the charge transfer phase is
( )( )
( )( )
2
2 23 31 1
, , , ,2 22 2
221 1
2 22 2 2
221
22 1 2
4 44 4
1
dB dBn C tran n Cc rst
m
m C
m C
C
C
kTR kTC CP PC g C
kT R g kT C CC CC R g C C C
C CC kTC C C C
ω γω
γ γ
γγ
− −⎛ ⎞= + +⎜ ⎟
⎝ ⎠+ +
≈ ++ +
⎛ ⎞+≈ +⎜ ⎟+⎝ ⎠
. (6-39)
Considering the fact that the noise sampled onto C1 during the reset phase is
transferred to C2 during the charge transfer phase, the total noise power on C2 after a
157
reset phase and a charge transfer phase is found to be
2
22 21 1
, , 2 22 2 2 1 2
C Cn C rst tran
C C
C C C CC CP kT kT kTC C C C C C C
γ γγ+
⎛ ⎞ ⎛ ⎞+ +≈ + + +⎜ ⎟ ⎜ ⎟+ +⎝ ⎠ ⎝ ⎠
. (6-40)
The first term comes from the sampling noise on C1 during the reset phase. The
second term is the reset noise on C2. The third term is the approximation of noise
during the charge transfer phase. For each additional charge transfer, one more
kTC1/C22 term is added for the sampling phase and one more
221
22 1 2
C
C
C CC kTC C C C
γγ⎛ ⎞++⎜ ⎟+⎝ ⎠
term is added for the charge transfer phase. Then, the noise
power on C2 before the Nth charge transfer phase is carried out is
( )2
22 21 1
, , 2 22 2 2 1 2
1C Cn C N
C C
C C C CNkTC CP kT N kTC C C C C C C
γ γγ⎛ ⎞ ⎛ ⎞+ +≈ + + − +⎜ ⎟ ⎜ ⎟+ +⎝ ⎠ ⎝ ⎠
. (6-41)
If the output is taken at the end of the charge transfer phase, adding a load
capacitor CL to the output node as shown in Figure 6-24. The transfer function from
VC2 to Vout can be found as
Figure 6-24 The equivalent circuits for DAC charge transfer phase
158
( )( )
2
2
11
out m
C L m
V s sC gV s sC g
−=
+. (6-42)
Due to sampling, the accumulated noise on C2 is represented as a DC signal before
the final output phase. Let s=0, we have Vout(s=0)/VC2(s=0)=1. Therefore, the total
output noise would be the summation of VC22 (multiplied by Vout(s=0)/VC2(s=0)=1)
and the output noise generated in the final charge transfer phase.
The transfer functions for different noise sources to Vout are found to be
( )( )
( )( )
1 22
, 1 2 1 2 1 2 1 2 2
out m
in r L L L m m
V s C sC gV s s C C C R s C C C C C C g RC C g C
−=
+ + + + +, (6-43)
( )( )
( )( )
( )( )
1 2 1 22
, 1 2 1 2 2 1 1 2 2C
out out m
in amp C L L L m m
V s V s g C C sRC CV s V s s C C C R s C C C C C C g RC C g C
+ += =
+ + + + +. (6-44)
The noise power at the Vout node due to all the noise sources in the final charge
transfer phase is calculated to be
( ) ( )( )( )( )( )
( )22 2 2
1 2 1 1 2 1 2 1 22, 2
2 22 1 2 1 2 1X
m L L mC
n VCL L L m
kT C C g RC C C C C g RC C C CC CP kT
C C CC C C C C C C C g R
γ γ+ + + + +⎛ ⎞+= + ⎜ ⎟++ + + ⎝ ⎠
, (6-45)
where the first term is the noise from the switches and the amplifier, the second term
is the noise from CC.
The final output noise for N charge transfers Pn,N is the summation of the
accumulated noise on C2 expressed by Eq. (6-41) and the output noise of the last
phase expressed by Eq. (6-44).
In ΔΣ converters, the DAC output varies pseudo-randomly among the N levels,
therefore, the average output noise power can be expressed as
159
,1
nn ii
n
PP
N== ∑ . (6-46)
6.2.2.4 ΔΣ ADC using the low-power nonlinearity-suppressed DAC
A third-order multi-bit ΔΣ modulator is designed using this low-power 7-level
nonlinearity-suppressed DAC. It is designed with a sampling frequency of 2MHz.
The signal bandwidth is 25 kHz or audio band, and the over-sampling-ratio is 40. It is
targeted for high-definition audio applications.
The ΔΣ modulator topology used for implementation is illustrated in Figure 6-25.
Several favorable properties exist in this topology. First, there is only one feedback
path in this feed-forward configuration, thus the load of the nonlinearity-suppressed
DAC is reduced and the interface between the DAC and the integrator would be
easier to implement compared to multiple feedback configurations. Different from
widely used feed-forward ΔΣ modulators, there is no path from the input to the
summation node preceding the quantizer. Without this path, the DAC load is further
Figure 6-25 The topology of the designed ΔΣ modulator with the ratio-independent DAC
160
reduced. It can be calculated that the resulting STF does not have a sharp out-of-band
peak but a relatively slow changing larger than 1 out-of-band gain. With the effects of
the input anti-aliasing filter and the decimation filter, its impacts are limited. Second,
this topology is not only suitable for implementation using integrators built with
traditional OTAs (integrators with or without unit delay), it can also be adapted for
class-C inverter integrators, where half-delay is present. To show this, we can split
the "Unit Delay 1" in Figure 6-25 to two half delay elements. One goes to integrator 1
and the other goes to the feed-forward branch and integrator 2. Similar changes can
be made on "Unit Delay 2" and all three integrators would carry half-delays. Third,
the feed-forward structure can reduce the amplifier DC gain required [99] by the
modulator as discussed before. In other words, the gain or phase error of the
integrators become less critical compared to the feed-back structures. This is
especially beneficial to a class-C inverter implementation.
The stability and noise issues of this modulator are investigated in Chapter 5. The
gain coefficients in this topology are chosen such that the quantization Noise Transfer
Function (NTF) takes a form of a Butterworth filter with the maximum NTF gain of
3.2, considering that a 7-level quantizer is used. It can be shown that coefficients used
in this design lead to a NTF very close to the ones extracted from extensive behavior
simulations.
6.3 Chip Measurement Results
The multi-bit ΔΣ modulator described above with the proposed 7-level
nonlinearity-suppressed DAC has been designed and fabricated in a commercial
161
0.13μm CMOS process. The modulator die photo is shown in Figure 6-26. The ΔΣ
modulator occupies a space of about 0.8mm by 0.6mm, in a 0.13μm CMOS process.
Its profile on the die is blocked by the top level metal fills. Its layout is therefore
shown in Figure 6-27. To suppress the effects of switch charge injection and clock
feed-through, dummy switches are used at certain switching nodes in the DAC and
first integrator in the prototype. No bootstrapping technique is used.
Figure 6-26 Die photo for the ΔΣ modulator prototype
Figure 6-27 Layout for the ΔΣ modulator prototype
162
The ΔΣ modulator die is enclosed in a QFP package and it is mounted on a
printed circuit board for evaluation purpose. The amplifiers, comparators, control
logic and clock generation core utilize a 1.2V supply voltage. On the other hand,
switches and level shifters/clock buffers at 3.3V are used to reduce on-resistance and
improve settling speed. The board provides a 1.2V and a 3.3V power supply voltages
from ordinary regulator ICs for the prototype. An on-board reference chip is used to
generate the DAC input voltage. As mentioned in Section II-A, only one input
reference to the DAC is used during testing. The 8MHz main clock is from a logic
analyzer. All other signals are generated inside the chip.
The differential input signal swing to the ΔΣ modulator is 1 Vpp. The output
Figure 6-28 ΔΣ modulator output spectrum
163
spectrum for a 2-kHz 0.5 Vpp differential signal is plotted in Figure 6-28. The input
signal to the prototype is generated by DS360, which is a low distortion signal
generator. A -94dBc 3rd-order harmonic in the spectrum is present. The SNDR and
SNR of the ΔΣ modulator versus input signal level are plotted in Fig. 11. For a
bandwidth of 20 Hz to 25 kHz, or an OSR of 40, the peak SNDR and SNR are 75-dB
and 79-dB, respectively. No significant distortion variation or in-band tone problem is
observed during the testing. At ΔΣ sampling rate of 2MHz, the modulator consumes
2.2 mA and 0.2 mA from the 1.2V and 3.3V power supply, respectively, and
approximately 0.6mA from 1.2V is dedicated to the analog part of the DAC.
For a 2 MHz ΔΣ sampling frequency, the modulator's performance is
Figure 6-29 SNDR and SNR versus input signal level
164
summarized in Table 6-1. Performance of other designs reported in literatures
employing calibration or DEM techniques is also listed for comparison. Our design
achieves good linearity performance and takes small space, while consuming
reasonable power. In the comparison, the power consumption of our method can be
further reduced by using a DAC with fewer output levels. The 7-level DAC has to
operate at least 3-times faster than the ΔΣ modulator and speed request for the first
integrator is also stringent. However, if the number of DAC levels is reduced to three,
then significantly lower power penalty would be present.
6.4 Chapter Conclusion
A 7-level audio-band ΔΣ modulator with a nonlinearity suppressed DAC is
designed and verified in this work. The approach does not rely on unit element
matching and thus related problems with existing methods are not present.
Measurement results show that a 94-dB SFDR is achieved, without
dynamic-element-matching or calibration techniques.
TABLE 6-1 PERFORMANCE SUMMARY AND COMPARISON
[100] [101] This work
ΔΣ Sampling Frequency 10 MHz 6.144 MHz 2 MHz Signal Bandwidth 21.7 kHz 24 kHz 25 kHz
OSR 230 128 40
SFDR ~80 dB @ -3.4 dBFS
~96 dB @ -6 dBFS
94 dB @ -6 dBFS
Peak SNR 80.1 dB 91 dB 79 dB Peak SNDR 73.4 dB 89 dB 75 dB Input Range 2 Vpp 1.1 Vpp 1 Vpp
Power Consumption 6.6 mW 1.5 mW 3.3 mW Area 1.2 mm2 (core) 1.44 mm2 (core) 0.48 mm2 (core)
Number of DAC levels 5 3 7 Technique Calibration DEM NS DAC
Power Supply 1.8 V 0.9 V 1.2 V Process 0.18μm CMOS 0.13μm CMOS 0.13μm CMOS
165
Chapter 7
Conclusion
This thesis proposed and verified approaches to design mixed-signal and
radio-frequency integrated circuits in modern deep-submicron CMOS technologies.
Circuit design problems with conventional methods in the two illustrative
applications, a RF PLL and a delta-sigma modulator, can be circumvented by using
the proposed techniques.
7.1 Main Contributions
In the RF PLL design, the new active low-power switched-capacitor loop filter
proposed is the first practical active SC loop filter architecture for high performance
RF applications. It reduces chip area taken by conventional passive RC loop filters,
while its power consumption accounts for only 3% of that of the whole PLL. Good
phase noise and reference spur performances are achieved by this method. Compared
with other active designs, its power consumption and noise introduced are low.
Compared with passive switched-capacitor filters, this loop filter assures Type II loop
dynamics. Measurement results from a fully-integrated PLL prototype fabricated in a
0.18μm CMOS process have verified the advantages of this approach.
In the multi-bit ΔΣ ADC design, the low-power nonlinearity-suppressed feedback
DAC offers a new solution other than dynamic-element-matching (DEM) and
166
calibration to design highly linear multi-bit ΔΣ ADCs. Unlike conventional linearity
enhancement techniques, this approach suppresses the sensitivity of DAC linearity on
the matching of unit elements. Thus related problems with existing methods, such as
in-band tones with DEM and complexity with calibration algorithms, are eliminated.
A ΔΣ modulator topology suitable for incorporating this DAC is also presented. A
7-level audio-band ΔΣ modulator with the proposed nonlinearity-suppressed DAC is
successfully designed and verified on silicon in a 0.13μm CMOS process.
7.2 Future Research
Measurement results from the two prototypes demonstrate the validity of these
methods. However, there are still several topics worth further investigation, for the
purpose of robustness and high-yield in practice. The first one is to stabilize the
biasing current for the inverter amplifiers, and make it independent of both
temperature and power supply voltage variations. No significant performance
variations were observed during our testing under room temperature and with the use
of ordinary voltage regulators. But since the static current is related to temperature
exponentially for sub-threshold MOS transistors, comprehensive performance
evaluation should be carried out over the full temperature range for a specific
application. A possible solution is to use temperature independent current sources.
Another topic is to increase the speed and/or power efficiency of the multi-bit
nonlinearity-suppressed DAC, in order to fit it into high-speed applications. This may
be realized in two ways. First, adding a buffer to the DAC output. This can isolate the
DAC and first integrator, and the loading effect of the first integrator during the DAC
167
output phase is relieved. Thus it results in easier design for high-speed operations. On
the other hand, the ΔΣ modulator implementation described in this thesis has a 7-level
feedback DAC. From performance comparison in Table 6-1, other designs have 3- or
5-level DACs. The power efficiency of our solution can be increased significantly by
decreasing the number of DAC levels employed.
168
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