Device Modeling for Analog andRF CMOS Circuit Design

Trond YtterdalNorwegian University of Science and Technology

Yuhua ChengSkyworks Solutions Inc., USA

Tor A. FjeldlyNorwegian University of Science and Technology

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Device Modeling for Analog andRF CMOS Circuit Design

Device Modeling for Analog andRF CMOS Circuit Design

Trond YtterdalNorwegian University of Science and Technology

Yuhua ChengSkyworks Solutions Inc., USA

Tor A. FjeldlyNorwegian University of Science and Technology

Copyright 2003 John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester,West Sussex PO19 8SQ, England

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Contents

Preface xi

1 MOSFET Device Physics and Operation 11.1 Introduction 11.2 The MOS Capacitor 2

1.2.1 Interface Charge 31.2.2 Threshold Voltage 71.2.3 MOS Capacitance 81.2.4 MOS Charge Control Model 12

1.3 Basic MOSFET Operation 131.4 Basic MOSFET Modeling 15

1.4.1 Simple Charge Control Model 161.4.2 The Meyer Model 181.4.3 Velocity Saturation Model 191.4.4 Capacitance Models 211.4.5 Comparison of Basic MOSFET Models 251.4.6 Basic Small-signal Model 26

1.5 Advanced MOSFET Modeling 271.5.1 Modeling Approach 291.5.2 Nonideal Effects 311.5.3 Unified MOSFET C –V Model 37

References 44

2 MOSFET Fabrication 472.1 Introduction 472.2 Typical Planar Digital CMOS Process Flow 482.3 RF CMOS Technology 60

References 67

3 RF Modeling 693.1 Introduction 693.2 Equivalent Circuit Representation of MOS Transistors 713.3 High-frequency Behavior of MOS Transistors and AC Small-signal

Modeling 78

vi CONTENTS

3.3.1 Requirements for MOSFET Modeling for RF Applications 793.3.2 Modeling of the Intrinsic Components 803.3.3 HF Behavior and Modeling of the Extrinsic Components 833.3.4 Non-quasi-static Behavior 98

3.4 Model Parameter Extraction 1013.4.1 RF Measurement and De-embedding Techniques 1013.4.2 Parameter Extraction 106

3.5 NQS Model for RF Applications 113References 115

4 Noise Modeling 1194.1 Noise Sources in a MOSFET 1194.2 Flicker Noise Modeling 119

4.2.1 The Physical Mechanisms of Flicker Noise 1204.2.2 Flicker Noise Models 1224.2.3 Future Work in Flicker Noise Modeling 123

4.3 Thermal Noise Modeling 1264.3.1 Existing Thermal Noise Models 1264.3.2 HF Noise Parameters 1284.3.3 Analytical Calculation of the Noise Parameters 1324.3.4 Simulation and Discussions 1344.3.5 Induced Gate Noise Issue 138

References 138

5 Proper Modeling for Accurate Distortion Analysis 1415.1 Introduction 1415.2 Basic Terminology 1425.3 Nonlinearities in CMOS Devices and Their Modeling 1455.4 Calculation of Distortion in Analog CMOS Circuits 149

References 151

6 The BSIM4 MOSFET Model 1536.1 An Introduction to BSIM4 1536.2 Gate Dielectric Model 1536.3 Enhanced Models for Effective DC and AC Channel Length and Width 1556.4 Threshold Voltage Model 157

6.4.1 Enhanced Model for Nonuniform Lateral Doping due to Pocket(Halo) Implant 157

6.4.2 Improved Models for Short-channel Effects 1596.4.3 Model for Narrow Width Effects 1616.4.4 Complete Threshold Voltage Model in BSIM4 163

6.5 Channel Charge Model 1646.6 Mobility Model 1676.7 Source/Drain Resistance Model 169

CONTENTS vii

6.8 I –V Model 1726.8.1 I–V Model When rdsMod = 0 (RDS(V ) �= 0) 1726.8.2 I–V Model When rdsMod = 1 (RDS(V ) = 0) 175

6.9 Gate Tunneling Current Model 1766.9.1 Gate-to-substrate Tunneling Current IGB 1766.9.2 Gate-to-channel and Gate-to-S/D Currents 178

6.10 Substrate Current Models 1796.10.1 Model for Substrate Current due to Impact Ionization

of Channel Current 1796.10.2 Models for Gate-induced Drain Leakage (GIDL) and

Gate-induced Source Leakage (GISL) Currents 1806.11 Capacitance Models 180

6.11.1 Intrinsic Capacitance Models 1816.11.2 Fringing/Overlap Capacitance Models 188

6.12 High-speed (Non-quasi-static) Model 1906.12.1 The Transient NQS Model 1906.12.2 The AC NQS Model 192

6.13 RF Model 1926.13.1 Gate Electrode and Intrinsic-input Resistance (IIR) Model 1926.13.2 Substrate Resistance Network 194

6.14 Noise Model 1946.14.1 Flicker Noise Models 1956.14.2 Channel Thermal Noise Model 1966.14.3 Other Noise Models 197

6.15 Junction Diode Models 1986.15.1 Junction Diode I–V Model 1986.15.2 Junction Diode Capacitance Model 200

6.16 Layout-dependent Parasitics Model 2016.16.1 Effective Junction Perimeter and Area 2016.16.2 Source/drain Diffusion Resistance Calculation 204References 206

7 The EKV Model 2097.1 Introduction 2097.2 Model Features 2097.3 Long-channel Drain Current Model 2107.4 Modeling Second-order Effects of the Drain Current 212

7.4.1 Velocity Saturation and Channel-length Modulation 2127.4.2 Mobility Degradation due to Vertical Electric Field 2137.4.3 Effects of Charge-sharing 2137.4.4 Reverse Short-channel Effect (RSCE) 214

7.5 SPICE Example: The Effect of Charge-sharing 2147.6 Modeling of Charge Storage Effects 2167.7 Non-quasi-static Modeling 218

viii CONTENTS

7.8 The Noise Model 2197.9 Temperature Effects 219

7.10 Version 3.0 of the EKV Model 220References 220

8 Other MOSFET Models 2238.1 Introduction 2238.2 MOS Model 9 223

8.2.1 The Drain Current Model 2248.2.2 Temperature and Geometry Dependencies 2278.2.3 The Intrinsic Charge Storage Model 2318.2.4 The Noise Model 233

8.3 The MOSA1 Model 2358.3.1 The Unified Charge Control Model 2358.3.2 Unified MOSFET I –V Model 2378.3.3 Unified C –V Model 241

References 241

9 Bipolar Transistors in CMOS Technologies 2439.1 Introduction 2439.2 Device Structure 2439.3 Modeling the Parasitic BJT 243

9.3.1 The Ideal Diode Equation 2459.3.2 Nonideal Effects 246

References 247

10 Modeling of Passive Devices 24910.1 Introduction 24910.2 Resistors 249

10.2.1 Well Resistors 25110.2.2 Metal Resistors 25210.2.3 Diffused Resistors 25210.2.4 Poly Resistors 253

10.3 Capacitors 25410.3.1 Poly–poly Capacitors 25510.3.2 Metal–insulator–metal Capacitors 25610.3.3 MOSFET Capacitors 25710.3.4 Junction Capacitors 258

10.4 Inductors 260References 262

11 Effects and Modeling of Process Variation and Device Mismatch 26311.1 Introduction 26311.2 The Influence of Process Variation and Device Mismatch 264

11.2.1 The Influence of LPVM on Resistors 26411.2.2 The Influence of LPVM on Capacitors 26611.2.3 The Influence of LPVM on MOS Transistors 269

CONTENTS ix

11.3 Modeling of Device Mismatch for Analog/RF Applications 27111.3.1 Modeling of Mismatching of Resistors 27111.3.2 Mismatching Model of Capacitors 27111.3.3 Mismatching Models of MOSFETs 273References 277

12 Quality Assurance of MOSFET Models 27912.1 Introduction 27912.2 Motivation 27912.3 Benchmark Circuits 281

12.3.1 Leakage Currents 28212.3.2 Transfer Characteristics in Weak and Moderate Inversion 28312.3.3 Gate Leakage Current 284

12.4 Automation of the Tests 285References 286

Index 287

Preface

We are fortunate to live in an age in which microelectronics still enjoy an acceleratinggrowth in performance and complexity. Fortunate, since we are experiencing a remark-able progress in science, in communication technology, in our ability to acquire newknowledge, and in the many other wonderful amenities of modern society, all of whichare permeated by and made possible by modern microelectronics. This exponential evolu-tionary trend, as described by Moore’s Law, has now lasted for more than three decades,and is still on track, fueled by a seemingly unending demand for ever better performanceand by fierce global competition.

A driving force behind this fantastic progress is the long-term commitment to a steadydownscaling of MOSFET/CMOS technology needed to meet the requirements on speed,complexity, circuit density, and power consumption posed by the many advanced appli-cations relying on this technology. The degree of scaling is measured in terms of thehalf-pitch size of the first-level interconnect in DRAM technology, also termed the “tech-nology node” by the International Technology Roadmap for Semiconductors. At the timeof the 2001 ITRS update, the technology node had reached 130 nm, while the smallestfeatures, the MOSFET gate lengths, were a mere 65 nm. Within a decade, these numbersare expected to be close to 40 nm and 15 nm, respectively.

Very important issues in this development are the increasing levels of complexity ofthe fabrication process and the many subtle mechanisms that govern the properties of deepsubmicrometer FETs. These mechanisms, dictated by device physics, have to be describedand implemented into circuit design tools to empower the circuit designers with the abilityto fully utilize the potential of existing and future technologies.

Hence, circuit designers are faced with the relentless challenge of staying updated onthe properties, potentials, and the limitations of the latest device technology and devicemodels. This is especially true for designers of analog and radio frequency (RF) integratedcircuits, where the sensitivity to the modeling details and the interplay between individualdevices is more acute than for digital electronics. A deeper insight into these issues istherefore crucial for gaining the competitive edge needed to ensure first-time-right siliconand to reduce time-to-market for new products.

Existing textbooks on analog and RF CMOS circuit design traditionally lack a thoroughtreatment of the device modeling challenges outlined above. Our primary objectives withthe present book is to bridge the gap between device modeling and analog circuit designby presenting the state-of-the-art MOSFET models that are available in analog and SPICE-type circuit simulators today, together with related modeling issues of importance to bothcircuit designers and students, now and in the future.

xii PREFACE

This book is intended as a main or supplementary text for senior and graduate-levelcourses in analog integrated circuit design, as well as a reference and a text for selfor group studies by practicing design engineers. Especially in student design projects,we foresee that this book will be a valuable handbook as well as a reference, both onbasic modeling issues and on specific MOSFET models encountered in circuit simulators.Likewise, practicing engineers can use the book to enhance their insight into the principlesof MOSFET operation and modeling, thereby improving their design skills.

We assume that the reader already has a basic knowledge of common electronicdevices and circuits, and fundamental concepts such as small-signal operation and equiv-alent circuits.

The book is organized into twelve chapters. In Chapter 1, the reader is introducedto the basic physics, the principles of operation, and the modeling of MOS structuresand MOSFETs. This chapter also discusses many of the issues that are important in themodeling of modern-day MOSFETs. Chapter 2 walks the reader through the fabricationsteps of modern MOSFET and CMOS technology. In Chapter 3, the special concernsand the challenges of accurate modeling of MOSFETs operating at radio frequenciesare discussed. Chapter 4 deals with modeling of noise in MOSFETs. Distortion analysis,discussed in Chapter 5, is of special concern for analog MOSFET circuit design. InChapters 6, 7, and 8, we present the state-of-the-art MOSFET models that are commonlyused by the analog design community today. The models covered are BSIM4, EKV, MOSModel 9 and MOSA1. These chapters are written in a reference style to provide quicklookup when the book is used like a handbook. Chapters 9 and 10 are devoted to themodeling of other devices that are of importance in typical analog CMOS circuits, suchas bipolar transistors (Chapter 9) and passive devices, including resistors, capacitors, andinductors (Chapter 10). The remaining two chapters deal with essential industry-relatedissues of circuit design. Chapter 11 discusses the important topic of modeling of processvariations and device mismatch effects and Chapter 12 deals with the quality assuranceof the device models used by the design houses.

The book is accompanied by two software application tools, AIM-Spice and MOSCalc.AIM-Spice is a version of SPICE with standard SPICE parameters, very familiar to manyelectrical engineers and electrical engineering students. Running under the Microsoft Win-dows family of operating systems, it takes full advantage of the available graphics userinterface. The AIM-Spice software will run on all PCs equipped with Windows 95, 98,ME, NT 4, 2000, or XP. In addition to all the models included into Berkeley SPICE(Version 3e.1), AIM-Spice incorporates BSIM4, EKV, and MOSA1, which were cov-ered in Chapters 6, 7, and 8. A limited version of AIM-Spice can be downloaded fromwww.aimspice.com . The second tool, MOSCalc, is a Web-based calculator for rapid esti-mates of MOSFET large- and small-signal parameters. The designer enters the gate lengthand width, and a range of biasing voltages and/or the transistor currents, whereupon quan-tities such as gate overdrive voltage, effective threshold voltage, drain-source saturationvoltage, all terminal currents, transconductance, channel conductance, and all small signalintrinsic capacitances are calculated. MOSCalc is available at ngl.fysel.ntnu.no.

These dedicated software tools allow students to solve real engineering problems, whichbrings semiconductor device physics and modeling home to the user at a very practicallevel, bridging the gap between theory and practice. AIM-Spice and MOSCalc can be usedroutinely by practicing engineers during the design phase of analog integrated circuits.

PREFACE xiii

We are grateful to the following colleagues for their suggestions and/or for reviewingportions of this book: Matthias Bucher and Bjørnar Hernes. We would also like to expressour appreciation to the staff at Wiley, UK, and in particular to Kathryn Sharples, formaking possible the timely production of the book.

Finally, we would like to thank our families for their great support, patience, andunderstanding provided throughout the period of writing.