ece375 lab 5web.engr.oregonstate.edu/~jinyo/ece375/pdf/ece375_lab5... · 2019-10-30 · 10/30/2019...

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10/30/2019 1 ECE375 Lab 5 TA: Youngbin Jin School of Electrical Engineering and Computer Science Oregon State University Large Number Arithmetic AVR 8-bit instruction set Perform arithmetic operations on numbers that are larger than 8 bits Practice Memory Manipulation The Skeleton Code includes operands for ADD16, SUB16, MUL24, and Compound

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10/30/2019

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ECE375 Lab 5

TA: Youngbin JinSchool of Electrical Engineering and Computer ScienceOregon State University

Large Number Arithmetic

AVR 8-bit instruction set

Perform arithmetic operations on numbers that are larger than 8 bits

Practice Memory Manipulation

The Skeleton Code includes operands for ADD16, SUB16, MUL24, and Compound

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16bit Adder

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$97 $0105 :$01 $0106 :

16bit Adder

FUNCTION:ldi XL, $00ldi XH, $01ldi YL, $02ldi YH, $01ldi ZL, $04ldi ZH, $01

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

X Y Z

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16bit Adder

FUNCTION:ldi XL, $00ldi XH, $01ldi YL, $02ldi YH, $01ldi ZL, $04ldi ZH, $01

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

X Y Z

16bit Adder

FUNCTION:ldi XL, $00ldi XH, $01ldi YL, $02ldi YH, $01ldi ZL, $04ldi ZH, $01

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

X Y Z

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16bit Adder

FUNCTION:ldi XL, $00ldi XH, $01ldi YL, $02ldi YH, $01ldi ZL, $04ldi ZH, $01

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

X Y Z

16bit Adder

FUNCTION:ldi XL, $00ldi XH, $01ldi YL, $02ldi YH, $01ldi ZL, $04ldi ZH, $01

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

X Y Z

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$16$17

R16R17

SREGC=0

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$17

R16R17

SREGC=0

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$17

R16R17

SREGC=0

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$77

R16R17

SREGC=0

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$77

R16R17

SREGC=0

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$77

R16R17

SREGC=0

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$77

R16R17

SREGC=0$76C=1

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$76

R16R17

SREGC=1

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$76

R16R17

SREGC=1

$76

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$00 $0104$00 $0105 :$00 $0106$00 $0107 :

$FF$76

R16R17

SREGC=1

$76

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$00 $0105 :$00 $0106$00 $0107 :

$A2$76

R16R17

SREGC=1

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$00 $0105 :$00 $0106$00 $0107 :

$A2$F4

R16R17

SREGC=1

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$00 $0105 :$00 $0106$00 $0107 :

$A2$97

R16R17

SREGC=1

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$00 $0105 :$00 $0106$00 $0107 :

$A2$97

R16R17

SREGC=1

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$00 $0105 :$00 $0106$00 $0107 :

$A2$97

R16R17

SREGC=1

$97

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$00 $0105 :$00 $0106$00 $0107 :

$A2$97

R16R17

SREGC=1

$97

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$97 $0105 :$00 $0106$00 $0107 :

$FF$76

R16R17

SREGC=1

16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$97 $0105 :$00 $0106$00 $0107 :

$FF$76

R16R17

SREGC=1

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16bit Adder

ld R16, X+

ld R17, Y+

add R17, R16

st Z+, R17

ld R16, X

ld R17, Y

adc R17, R16

st Z+, R17

brcc EXIT

st Z, XH

EXIT:

ret

$FF $0100$A2 $0101 :$77 $0102$F4 $0103 :$76 $0104$97 $0105 :$00 $0106$00 $0107 :

$FF$76

R16R17

SREGC=1

$01

Program Memory to Data Memory

$D1$D2$D3$D4

$0100$0101$0102$0103

$FF$77$00

$0200$0201$0202

$A2$F4$00

Program Memory Data Memory

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Program Memory to Data Memory

$D1$D2$D3$D4

$0100$0101$0102$0103

$FF$77$00

$0200$0201$0202

$A2$F4$00

Program Memory Data Memory

$FF$A2$77$F4

Program Memory to Data Memory

$D1$D2$D3$D4

$0100$0101$0102$0103

$FF$77$00

$0200$0201$0202

$A2$F4$00

Program Memory Data Memory

$FF$A2$77$F4

$FF$A2$77$F4$76$97$01

OperationsADDSUBMUL

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Program Memory to Data Memory

$D1$D2$D3$D4

$0100$0101$0102$0103

$FF$77$00

$0200$0201$0202

$A2$F4$00

Program Memory Data Memory

$FF$A2$77$F4

$FF$A2$77$F4$76$97$01

$D1$D2$D3

$0104$0105$0106

$76$97$01

Demo Check

Insert Break Points◦ ADD16◦ SUB16◦ MUL24◦ COMP◦ DONE

TA will only check these break points

You cannot modify memory during Demo

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Checklist for Lab 5

Demo Checklist◦ Correct ADD16 result w/ direct operands◦ Correct SUB16 result w/ direct operands◦ Correct MUL24 result w/ direct operands◦ Correct ((D – E) + F)^2 result◦ Good explanation of changes required to make

MUL16 into a working MUL24?

Challenge Checklist◦ MUL24 implemented using shift-and-add, and

used for ((D – E) + F)^2 calculation

Questions?