7/31/2019 Eda Introduction

1/45

CAD for VLSI @ Indian Institute of Science 1

Introduction to EDA11 January 2005

Nachiket Urdhwareshe

7/31/2019 Eda Introduction

2/45

CAD for VLSI @ Indian Institute of Science 2

Design & Manufacturing

ConceptualizeSpecify

Verify

Refine

Implement

Verify

Test

Ship

Package

DESIGN

MANUFACTURING

7/31/2019 Eda Introduction

3/45

CAD for VLSI @ Indian Institute of Science 3

Concept

Philosophical Abstract

What I want the product to be! Tools

Human Brain

7/31/2019 Eda Introduction

4/45

CAD for VLSI @ Indian Institute of Science 4

Specification

Details of the functionality How the product is supposed to behave

Formal Useful for exchange of the concept Not ambiguous

7/31/2019 Eda Introduction

5/45

7/31/2019 Eda Introduction

6/45

CAD for VLSI @ Indian Institute of Science 6

Verification

Ascertain that specification captures theintent (concept) correctly and completely

Ascertain that the parameters are correctand adequate

Tools

Analysis: mathematical Modeling and running (executing)

7/31/2019 Eda Introduction

7/45

CAD for VLSI @ Indian Institute of Science 7

Refinement

Add more details to the specification Take it closer to implementability

Synthesize!

7/31/2019 Eda Introduction

8/45

CAD for VLSI @ Indian Institute of Science 8

Verification

Ascertain that refined specification implementsthe specification correctly and completely

Ascertain that the refined parameters are correct

and adequate Tools

Analysis: mathematical

Modeling and executing prototyping

7/31/2019 Eda Introduction

9/45

CAD for VLSI @ Indian Institute of Science 9

Implementation

Take the refined design specificationthrough the process of manufacturing

Output Physical product

7/31/2019 Eda Introduction

10/45

CAD for VLSI @ Indian Institute of Science 10

Testing

Ensure that the product meets the specification Eliminate the possibility of error in the manufacturing

process Variation in processes

Variation in manufacturing environment Defects in manufacturing equipment

Run the actual product Under all possible operating conditions and inputs

Under stress Beyond specified operating parameters

Detect and diagnose the error

7/31/2019 Eda Introduction

11/45

CAD for VLSI @ Indian Institute of Science 11

Package

Make the product suitable for end-userusage Aesthetics Safety Regulation

READY TO BE SHIPPED

7/31/2019 Eda Introduction

12/45

CAD for VLSI @ Indian Institute of Science 12

Design & Manufacturing of VLSI

ConceptualizeSpecify

Verify

Refine

Implement

Verify

Test

Ship

Package

DESIGN

MANUFACTURING

7/31/2019 Eda Introduction

13/45

CAD for VLSI @ Indian Institute of Science 13

Concept

Automatically process the data and generatethe desired output as desired by the user

Processor!

7/31/2019 Eda Introduction

14/45

CAD for VLSI @ Indian Institute of Science 14

Specification

Details of the functionality How the user directions are to be interpreted How the data has to be processed What output has to be generated When the input has to be read

When the output has to be generated

7/31/2019 Eda Introduction

15/45

CAD for VLSI @ Indian Institute of Science 15

Specification: Processor

If (instruction = 1)o/p = i/p+1;

If (instruction = 2)

o/p = i/p + temp;...

instruction

i/p datao/p data

7/31/2019 Eda Introduction

16/45

CAD for VLSI @ Indian Institute of Science 16

Specification

Parameters Performance Speed: clock frequency of processor Through put: amount of o/p data per clock

Resource constraints Area: size of the processor circuit Power: allowed power dissipation per cycle

Regulatory constraints Safety: non-toxic, radiation emission

Miscellaneous Testability: should be able to test each instruction stage Reliability: mean time to failure, failure rate,

7/31/2019 Eda Introduction

17/45

CAD for VLSI @ Indian Institute of Science 17

Verification

Ascertain that specification captures theintent (concept) correctly and completely

Ascertain that the parameters are correctand adequate

Tools

Analysis: mathematical Modeling and running (executing)

7/31/2019 Eda Introduction

18/45

CAD for VLSI @ Indian Institute of Science 18

VerificationIf (instruction = 1)o/p = i/p+1;

If (instruction = 2)o/p = i/p + temp;

.

.

.

instruction

i/p data

o/p data

C++ Model

compile

m/c executableModel

instruction

i/p datao/p data

Mathematical

Model

Compute &Prove

7/31/2019 Eda Introduction

19/45

CAD for VLSI @ Indian Institute of Science 19

Refinement

Add more details to the specification Clock-wise behavior of processor Details of control circuit, data processing

circuit, interconnection, storage Gates to be used Geometry of components

Take it closer to implementability Synthesize!

7/31/2019 Eda Introduction

20/45

CAD for VLSI @ Indian Institute of Science 20

RefinementIf (instruction = 1)o/p = i/p+1;

If (instruction = 2)o/p = i/p + temp;

.

..

instruction

i/p data

o/p data Control ckt

Data ckt

Registerfile

instruction

i/p data

o/p data

7/31/2019 Eda Introduction

21/45

CAD for VLSI @ Indian Institute of Science 21

Refinement

Memory Data Circuit

and and xor

inv or and nor nand

dff or

X-axis

Y-axis

7/31/2019 Eda Introduction

22/45

CAD for VLSI @ Indian Institute of Science 22

Verification

Ascertain that refined specification implementsthe specification correctly and completely Ascertain that the refined parameters are correct

and adequate

Tools Analysis: mathematical Modeling and executing

Prototyping

Different tools and techniques used after eachrefinement step

7/31/2019 Eda Introduction

23/45

CAD for VLSI @ Indian Institute of Science 23

Implementation

Take the refined design specificationthrough the process of manufacturing Mask preparation

Chemical process Photolithography

Output Manufactured raw IC

7/31/2019 Eda Introduction

24/45

CAD for VLSI @ Indian Institute of Science 24

Testing

Ensure that the product meets the specification Eliminate the possibility of error in the manufacturingprocess Variation in processes

Variation in manufacturing environment Defects in manufacturing equipment

Run the actual product Under all possible operating conditions and inputs

Under stress Beyond specified operating parameters

Detect and diagnose the error

7/31/2019 Eda Introduction

25/45

CAD for VLSI @ Indian Institute of Science 25

Package

Make the product suitable for end-user usage Aesthetics: form factor of processor for board mounting Pin locations

On periphery

On surface Safety:

EM radiation, interference Mechanical vibrations

Electrical isolation Heat dissipation

READY TO BE SHIPPED

7/31/2019 Eda Introduction

26/45

CAD for VLSI @ Indian Institute of Science 26

Methodology

Systematic process Plan the design activity Execute the steps in design

Methodology needs to be customized Type of design

New concept Extension of a product

Type of target manufacturing process technology Fully customized Semi customized Field assembly, implementation Reuse of procured components

Complexity of the target process

7/31/2019 Eda Introduction

27/45

CAD for VLSI @ Indian Institute of Science 27

Motivation for EDA

Help Electronic System Designer Complexity of electronic systems Size Feature sizes Conflicting performance parameters

Application specific requirements Mobile computing

Time to market obsolesence

7/31/2019 Eda Introduction

28/45

CAD for VLSI @ Indian Institute of Science 28

Motivation for EDA

Mass adaptation of technology

time

users

experts

Ordinary massusers

laggards

7/31/2019 Eda Introduction

29/45

CAD for VLSI @ Indian Institute of Science 29

EDA Tools: classification

HDLs Spec Charts Flow graphs

Languages Compilers Code analyzer

Specification

performance verification rule chekers

Static

Simulation Testing

Dynamic

Analysis

Partition Transformation Optimization

Synthesis

GUI Viewer/Editor Converter ATPG

Support

ESDA Tool

7/31/2019 Eda Introduction

30/45

CAD for VLSI @ Indian Institute of Science 30

History

Type Year Complexity(# Gates)

Technolog(micron)

SSI 1960s < 100 10 -15MSI 1970s 0.1 - 1K 5 - 10LSI 1970s -1980s 1K - 100K 3 - 5VLSI 1980s-1990s 100K - 1M 2 - 3

ULSI 1990s 10M 0.25 - 0.62004 > 50M 0.09, 0.06

7/31/2019 Eda Introduction

31/45

CAD for VLSI @ Indian Institute of Science 31

Moores Law

Number of transistors on an IC doubleevery 18 months

7/31/2019 Eda Introduction

32/45

CAD for VLSI @ Indian Institute of Science 32

Methodology

Full custom designs only method in 1960s-70s all stages of design done manually with some

assistance from tools Today used for large volume, general purpose

chips: memories, microprocessor, ...

7/31/2019 Eda Introduction

33/45

CAD for VLSI @ Indian Institute of Science 33

Methodology Semi-custom designs

Standard cells all masks need to be produces cell masks available technology independent

Gate arrays only metal masks need to be made

ISSP, Structured ASICs FPGA Place & Route tools can be used in place of

manual layout

7/31/2019 Eda Introduction

34/45

CAD for VLSI @ Indian Institute of Science 34

Methodology IP (core) based designs

design reuse at high level becoming popular

7/31/2019 Eda Introduction

35/45

CAD for VLSI @ Indian Institute of Science 35

Tool UsagePeriod Tool UsageTill 1980s Circuit Simulator, Digital Logic Simulator

Layout Editors, DRC/ERC

1980s Logic Simulators (Modeling with HDLs)Place & Route Tools

Parameter extraction and back annotationCell characterization

1990s Logic Synthesis, Timing analysis, Test compilers,ATPG

Future High level synthesis, Design for testability, Hardware-software co-design, formal verification, Layout drivensynthesis,

7/31/2019 Eda Introduction

36/45

CAD for VLSI @ Indian Institute of Science 36

Techniques in design/EDA

Abstraction Deal with only the issues and details that arerelevant at any stage

Hierarchy Divide and conquer Reuse

Collaborative design Object oriented

7/31/2019 Eda Introduction

37/45

CAD for VLSI @ Indian Institute of Science 37

Abstraction levels and domainsof h/w descriptions

architecture

Register Transfer

Logic Gates

Transistors

I/O Specs

Behavior, Processes

Register Transfers

Boolean EquationsDifferential Equations

Masks

Stick Diagrams

Standard Cells

Floor Plan

High Level SynthesisControl Path Synthesis

Logic Synthesis

Technology Mapping

FUNCTIONALSTRUCTURAL

PHYSICAL

7/31/2019 Eda Introduction

38/45

CAD for VLSI @ Indian Institute of Science 38

structure

functional

7/31/2019 Eda Introduction

39/45

CAD for VLSI @ Indian Institute of Science 39

Design Flow

System Specs

SystemSimulation

H/wspecification

partition

Behavioralsimulation

High levelsynthesis

Synthesizablespecification

RTLsimulation

Logicsynthesis

Gate levelspecification

Gate levelsimulation

Placement &routing

Geometricspecification

High level h/wspecification

Synthesizablespecification

Gate levelspecification

Back annotation

extraction

ATPGFault

Simulation

Test

compiler

Device

testing

7/31/2019 Eda Introduction

40/45

CAD for VLSI @ Indian Institute of Science 40

Skills needed for EDA

Domain knowledge System design Logic design

Physical design Package design Mask design Test automation

7/31/2019 Eda Introduction

41/45

CAD for VLSI @ Indian Institute of Science 41

Skills needed for EDA

Software Conceptualization and Specification Data structure design Algorithm design and analysis Heuristic techniques GUI

Software Engineering Processes Tools

7/31/2019 Eda Introduction

42/45

CAD for VLSI @ Indian Institute of Science 42

The Course Structure and Objective

Issues and Concepts Emphasis on real-life problems State of the art tools and approaches

Software orientation Algorithms Data Structures

Emphasis Tool development rather than tool usage Re-use of already available software infrastructure to build tools

(which is the more practical scenarios for fresh recruits) Current trends and open problems along with historical issues

Others Extra guest lectures from experts Seminars and course projects Possibility of working on industry projects

7/31/2019 Eda Introduction

43/45

CAD for VLSI @ Indian Institute of Science 43

Course Contents

Introduction to CAD A little bit of Philosophy

Design Entry and Modeling Hardware Description Languages

Design paradigms and methodologies Standard cells, Gate-arrays, FPGAs, Structured ASICs,

Re-configurable platforms, etc Design Verification

Simulation, Formal Verification, Timing Analysis Relevant data structures and algorithms

Synthesis Behavioral synthesis, logic synthesis Relevant data structures and algorithms

7/31/2019 Eda Introduction

44/45

CAD for VLSI @ Indian Institute of Science 44

Course Contents (contd)

Physical Design Automation Partitioning Floorplanning

Placement Routing DRC, LVS and Parasitics Extraction

Testing

Automatic Test Generation Fault Simulation Design for Test (DFT) Automatic Testers, Failure Analysis and Silicon Debugging

Advanced Topics Post-layout CAD Design for Manufacturability and Yield System Level Design Re-configurable architectures

7/31/2019 Eda Introduction

45/45

CAD for VLSI @ Indian Institute of Science 45

Instructors from outside IISc From SoftJin

Prof. PCP Bhatt Ph.D. from IITK in 1969 Professor at IITK, IITD, IIITB etc

Supervised more than 100 students in Ph.D., Masters and Bachelorsprojects Technical advisor at SoftJin

Nachiket Urdhwareshe M.Tech from IITB in 1992

Worked in Sasken (1992-2000) and promoted SoftJin in 2000 Expertise in Front-end (verification, synthesis) design tools

Dr. Ravi Pai Ph.D. from IITB in 1991 Worked in Sasken (1991-2000) and promoted SoftJin in 2000

Expertise in physical design (floorplanning, placement, routing) andpost-layout design tools

Guest Lectures from domain experts from industries andacademia