eece 321: computer organization - kfupmfaculty.kfupm.edu.sa/coe/mayez/ps-coe301/aub... · – 2...

EECE 321: Computer Organization

Mohammad M. MansourDept. of Electrical and Compute Engineering

American University of BeirutAmerican University of Beirut

Lecture 1: Introduction

Administrative

Instructor– Dr. Mohammad M. Mansour, Associate Professor of ECE– Office: 501 Bechtel– Extension: 3597– Email: [email protected]

Send emails with Subject: EECE321– Will try to reply back during office hours

Course Webpage:

Prof. M. Mansour

Course Webpage:– http://webfea.fea.aub.edu.lb/mmansour/eece321/index.htm

Teaching Assistant (TA): – Nadida Raad ([email protected])

Office hours to be announced Lecture hours:

– MWF: 10:00 – 11:00 am in room 541 Bechtel

EECE 321: Computer Organization 2

Course Policy Grading (tentative)

– Homework (10%) – 2 Midterms (40%) --- [Include Homework questions]– Project (15%)– Final Exam (30%) --- [Includes Homework questions]– Participation/attendance (5% up to instructor)

Final course grade will not be assigned based on a curve Attendance taken randomly during the semester at the start of the lecture

– Late arrivals are considered as absences (no excuses allowed) Assignments:

– Reading assignments: Assigned every lecture. ~20% course questions on exams.– Weekly homework: Direct HW questions will be part of the midterms and final exam

Prof. M. Mansour

– Weekly homework: Direct HW questions will be part of the midterms and final exam– Deadlines are sharp, late submissions will not be accepted.– Cheating: All parties involved will automatically get a grade of zero on the 10% homework grade.– Final homework grade = (Grade on HW assignments) x (HW grade on exams / 100)

Projects: Groups of three students– Must assemble teams early– Project will be done in several phases– Direct project questions will be part of the midterms and final exam– Cheating: All parties involved will automatically get a grade of zero on the 15% project grade.– Final project grade = (Grade on course project) x (project grade on exams / 100)


Course Policy

Lecture slides will be posted on line– Must come to class prepared to take notes, so bring pens & notebooks– Lectures begin on the hour. Students arriving late may be refused entry to the classroom.

Exams are closed book and comprehensive. Students are responsible for all material covered in class, as well as other material posted on the web.

– No makeup exams will be given for missing any midterm (70% of your grade will be based on whatever exams were taken)

– If you miss the final exam, your course grade will be Incomplete (I)• Do not make any travel arrangements during the final exams week of the semester• Must sit for final exam on campus

Reviewing your final course grade at the end of the semester must be accompanied

Prof. M. Mansour

Reviewing your final course grade at the end of the semester must be accompanied with a signed letter from the Associate Dean

– Any student who sends emails objecting for his/her course grade or asking for more grades will be automatically reported to the FEA Student Affairs Committee, which may result in a Dean’s Warning in addition to failing the course.

Don’t even think about cheating !!!– Zero tolerance policy; Reported to Student Affairs Committee for appropriate action.

This course policy must be read and understood clearly by all students before registering in the course


Course Syllabus

Main Textbook (P&H)– David Patterson and John Hennessy, “Computer Organization & Design: The

Hardware/Software Interface,” 4th edition, Morgan Kaufmann Pub., Inc., 2009.

Prerequisites– EECE 230: C/C++ Programming

Prof. M. Mansour

– EECE 230: C/C++ Programming– EECE 320: Digital Logic Design– Assumption is that you know

• C/C++ programming: loops, functions, etc. • 2’s complement and unsigned numbers• Basic digital logic gates, truth tables• Basic combination gates: Adders, shifters, multipliers• Basic sequential gates: Flip flops, registers• Finite state machines• VHDL

– You are responsible for reviewing all the above material

EECE 421: Computer Architecture 5

Outline

Topics Computer Abstractions Machine Instructions, Assembly Language and Programs MIPS/x86 Instruction Set Architectures: RISC vs. CISC Microprocessor Datapath Design Basics Instruction Sequencing and Datapath Control Pipelining Memory Systems Input/Output Organization Introduction to multi-cores/multi-processors

Prof. M. Mansour

Introduction to multi-cores/multi-processors

Detailed outline found in course syllabus.

Material is mainly based on Patterson and Hennessy (P&H), 4th edition

Project: You will apply these ideas to design and implement a substantial course project.


Course Objectives

Introduce the main components of a computer system. Datapath & Control (=processor) Memory System Input and Output (I/O) system

Present an overview of the state-of-the-art microprocessors, memory systems, and I/O techniques.

Use commercial microprocessors to demonstrate these concepts. Understand the full internal workings of a typical RISC microprocessor including the

utilization of the various hardware resources during the execution of instructions. Introduce assembly language programming, and use a software simulator to

Prof. M. Mansour

Introduce assembly language programming, and use a software simulator to simulate the execution of machine code on a MIPS microprocessor.

Introduce the design and implementation of a microprocessor’s datapath and control using a hardware description language (HDL).

Introduce modern memory technologies, and modern memory systems. Introduce the design of microprocessor interfacing, basic I/O hardware, and I/O

techniques and protocols: polling, interrupts, DMA. Introduce new trends in multi-core/multi-processor systems


In this course we will use the MIPS 32-bit RISC microprocessor

Basic Structures of Computers

Prof. M. Mansour

Basic Structures of Computers


Basic Structure of Computers: Five Main Components

Since 1946, all computers have had five main components Datapath, Control, Memory, Input, Output

Processor = Control + Datapath

Processor

Computer

Memory

(where

IO System

Keyboard, Mouse

Disk

Prof. M. Mansour EECE 321: Computer Organization 9

Control(“brain”)

Datapath(“brawn”)

(where programs, data live whenrunning)

Input

Output

Display, Printer

Disk(where programs, data live whennot running)

Inside a “Modern” Processor

AMD Barcelona processor: 4 cores


The Big Picture

Coordination of many layers of abstraction

I/O systemProcessor

CompilerOperating

System(WinXP)

Application (ex: Matlab)

Instruction SetArchitectureMemoryHardware

Software Assembler

EECE 321


I/O systemProcessor

Digital DesignCircuit Design

Architecture

Datapath & Control

Transistors

MemoryHardware

Devices

Instruction Set Architecture (ISA)

ISA is the interface between hardware and the lowest-level software. It is an abstraction layer through which hardware designers and software designers

communicate.– It includes anything programmers need to know to make a binary machine language program

work properly.– It defines the specs that hardware designers need to implement.

There are many implementations of an ISA (called microarchitectures)– Varying cost and performance, but run identical software– Example: Intel and AMD implement different processors of the Intel 80x86 ISA

• Pentium Processors by Intel• Athlon Processors by AMD

Prof. M. Mansour

• Athlon Processors by AMD

An ISA comprises:– Organization of memory– Data types and data structures: Encodings and representations– Instruction set– Instruction formats– Modes of addressing and accessing data items and instructions– Exceptional conditions

Modern instruction set architectures:– 80x86/Pentium/K6, PowerPC, MIPS, SPARC, HP


Levels of Representation in EECE 321

High-level LanguageProgram (e.g., C)

temp = v[k];v[k] = v[k+1];v[k+1] = temp;

Compiler

Assembly LanguageProgram (e.g., MIPS)

lw $t0, 0($2)lw $t1, 4($2)sw $t1, 0($2)sw $t0, 4($2)

Assembler

Machine LanguageProgram (MIPS)

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001


Program (MIPS) 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

ArchitectureInterpretation

ArchitectureImplementation

Hardware ArchitectureDescription (e.g., VHDL)

signal dataBus: std_logic_vector(31 downto 0);Component regFile

port (dataBus :in std_logic_vector(31 downto 0);A,B:out std_logic_vector(31 downto 0) );

end component;Component ALU

port (A,B:in std_logic_vector(31 downto 0);dataBus: out std_logic_vector(31 downto 0) );

end component;

Logic Circuit Description(VHDL)

signal x, y: std_logic;y <= A xor B;X <= y and C;

Machine Language, Assembly Language

Machine language: Binary representation used for communication within a computer system. Assembly language is more readable than machine language because it uses symbols instead

of bits. The symbols in assembly language name commonly occurring bit patterns, such as opcodes and register specifiers so they are more readable.

Assembler: A tool that translates assembly language into machine language. Example: A routine to compute and print the sum of the squares of integers between 0 and

100.Machine language code Assembly language code


Linker

Linker: A systems program that combines independently assembled machine language programs and resolves all undefined labels into an executable file.


Announcements

Reading assignment:– Chapter 1 (P&H)– Review material from EECE 230– Review material from EECE 320 + VHDL

HW 1 will be posted– Due next Monday at the beginning of the lecture


eece 321: computer organization - kfupmfaculty.kfupm.edu.sa/coe/mayez/ps-coe301/aub... · – 2...

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