eee454 vlsi i laboratory laboratory module 5: design of...

©ABM H. Rashid, Dept. of EEE, BUET 17/08/2014

Department of Electrical & Electronic Engineering Bangladesh University of Engineering & Technology

EEE454 VLSI I Laboratory

Laboratory Module 5: Design of CMOS ring oscillator, cascaded drivers and different types of digital

delay circuits using cadence virtuoso

Objectives: The objectives of this module are to become familiar with Virtuoso schematic editor, learn how to create the symbol view of basic primitives, compose symbols hierarchically, and verify the design through simulation. In order to achieve these objectives, ring oscillator configurations is considered. This configuration is widely used as formalism for technology characterization: to estimate the speed of technology in terms of gate delay. The numbers obtained here will thus become essential tool in estimating delays of complex circuits. Again some gate outputs in a design such as clock signals need to be connected to a large number of gates and thus drive a large capacitive load. The effect of an output driving many inputs results in unacceptably large edge time (rise time/fall time) which is proportionate to Cout/(W/L), where Cout is the load capacitance of the gate driving the signal and W/L is the aspect ratio of the transistor. A very large size buffer can not be used because it will increase the input capacitance thus causing loading to the input signal. To mitigate the effect of large output capacitance, cascaded drivers are used. In the second part of this module we will design cascaded drivers circuit and simulate its effect in mitigating delay due to large capacitive load. Finally students will experiment with different types of digital delay circuits. 5-1 Hierarchical Design of a CMOS ring oscillator circuit 5-1-1 Entering design schematic to create a basic CMOS inverter with unit drive strength.

1. We are going to create the inverter sized for unit drive strength (typically indicated as “1x”). In the Library Manager, click to select your working library (e.g. eee458lab) and then click File > New > Create cellview to create schematic view for the new cell.

2. Type INVX1 in the Cell Name field as illustrated.


3. Click OK. After you click OK, Virtuoso Schematic Editing window will pop up.

4. Instantiate NMOS and PMOS transistors as described in Tutorial 1. The unit (“1x”) inverter has Wp/Wn ratio of around 2, where Wn is 2x the minimum width. In our technology, Wmin = 120nm, so the unit inverter is Wp/Wn = 480nm/240nm. Next, we are going to add input and output pins, which are needed to describe connectivity information for the symbol view. To instantiate a pin, type “p” in the schematic editor and following dialog will show up:


5. Type A VDD GND under Pin Names to define input pins, click Hide and place the pins in the schematic. Follow the same procedure to place output pin Z. Wire up the schematic (reminder: press “w” to enter wiring mode / Esc to exit). The final schematic should look like this (type “f” to fit the drawing to page):

6. Click Design Check and Save or type “X” to check and save the design. Watch the CDS.log window for any potential warnings. In the log window, you should see following messages:

Schematic check completed with no errors. “gpdktraining INVX1 schematic” saved.

5-1-2 Creation of a Symbol for the CMOS Inverter Creation of a Symbol 1. In the inverter schematic window execute Create → Cellview → From Cellview.


The Cellview From Cellview form appears. With the edit options function active, you can control the appearance of the symbol to generate. 2. Verify that the From View Name field is set to schematic, and the To view Name field is set to symbol, with the Tool/Data Type set as Schematic-Symbol. 3. Click OK in the cellview From Cellview form. The Symbol Generation Form appears.

4. After you click OK, the following window will appear indicating that input pins A GND and VDD will be placed on the left and that output pin Z will be placed on the right:


5. Click OK and the default box-shaped symbol view is created as shown below:

5-1-3 Editing a Symbol In the steps below you will modify your inverter symbol to look it more meaningful.

1. Move your cursor over the symbol, until entire green rectangle is highlighted (selected). Click left to select it.

2. Click the delete icon in the symbol window. 3. Execute Create → Shape → Polygon. Follow the prompt at the bottom of the schematic,

and draw the triangle shown in the final picture. 4. Draw a selection box around the A label and right click the mouse. Select move from the

selection box. Move the text to the desired location. 5. Repeat step 4 above for the Z, GND and VDD text.


6. Edit properties (reminder: select the object and press “q”) of the [@partName] label and specify justification to centre Left. This will ensure that the INVX1 label is nicely aligned within the shape (as you are going to see in the next section).

7. To save your edited symbol view to disk, click the Save icon in the symbol editor window. When you save the final version, make sure it is bug-free. As in the schematic entry, check the CDS.log window. It should display following message for the correctly designed symbol view: “INVX1 symbol” saved.

8. Now we can instantiate this symbol to build other circuits such as ring oscillator and cascaded drivers circuit.

5-1-4 Hierarchical Design: Ring Oscillator

1. By now you are already an expert in creating new cells, so let’s make another one. Go to the Library Manager window and add Ring_OSC cell to your working library.

2. We are going to create a 15-stage ring oscillator in order to measure the delay of the 1x inverter. In the Virtuoso Schematic Editor window, now instantiate INVX1 cell (symbol view) from your working library. Furthermore, we are going to place the 15 inverters in three rows, 5 in each row, to make the schematic easily readable. To place the first row of cells, in the array field specify 5 columns (meaning you want to place 5 instances in a column-like fashion). Click hide (or press Enter) and place the first instance.


3. Then move the mouse pointer over to the right to define the location for other instances. You should see yellow flylines with 5 INVX1 cells. After suitably adjusting the flylines the first row of instances should look something like this:

4. For easy routing of global signals VDD and GND, we are going to flip and rotate the second row of cells. In the Add Instance menu, specify again 5 columns, but also click once on Sideways and Upside Down buttons. Finally, create the third row in the same way the first row was created and place the third row below the second row. Instantiate vdd and gnd cells from analogLib and wire up the schematic (reminder: press “w” to enter wiring mode / Esc to exit).


Also label one of the points in the ring – this point will be used as a test point to measure the delay. You can either execute Add Wire Name from the drop down menu or press “l” (small “L”) to add the label. Add label named TP and place it at the output of the last inverter in the first row. The final placement should look like this:

5-1-5 Ring Oscillator delay simulation

1. Invoke simulation environment by choosing File Analog environment from the Virtuoso schematic editor window (review Spectre Simulation section of Tutorial 1 if needed). In addition to the setup in Tutorial 1, we also need to set up global source such as vdd!. In the Analog Design Environment, Click Setup Stimuli...

2. Click on Global Sources. Make sure vdd! is high lighted. Click on Enabled. Enter 1.0 in DC voltage. Then Click the change button. Click OK.


3. Since there is no start-up circuit a ring oscillator may not oscillate. In order to help with convergence we can also set up some initial conditions, for example make the right-most node a zero. Go to SimulationConvergence AidsInitial Condition then click on the right most node in the schematic. A big zero should appear on top of the net. Click OK.

4. Set up the models, select transient analysis with duration of 20ns and moderate accuracy.

5. Select TP as the output to be plotted. You should get the following graph as the simulation

result.

6. Now, let’s calculate the oscillation period. Click on calculator button as highlighted above. In the Calculator window (shown below), select vt. Now go to special function submenu and select delay. Virtuoso Schematic Editor window will pop up for you to select the waveform you want to probe: select TP and go back to the Calculator window.

7. Both Signal1 and Signal2 fields should read VT(“/TP”). Set Threshold Value 1 to 0.5

(VDD/2=0.5V) and Edge Number 1 to rising (falling is also OK). Next specify Edge number 2 and specify it to rising.


8. Click Eval button to evaluate the delay expression highlighted above. The expression evaluates to 400ps. This is the period of oscillation. In terms of gate delay, period T has a total of 15 low-to-high and 15 high-to-low transitions.

T = N∙(tpLH + tpHL), where N is the number of stages (N=15) Gate delay = tp = (tpLH+tpHL)/2 Therefore: tp = T/2N For N = 15: tp = 400/30 = 13.3ps This is the delay of an inverter in which output is loaded with an identically sized inverter. This is also called the delay of a fan out-of-one (FO1) inverter.

5-2 To create a basic CMOS inverter with transistor size as a variable which can be passed through the hierarchy. 5-2-1 Creating the basic CMOS inverter with transistor size as variable.

1. Design the inverter circuit as in Lab 3. We will use input signal pin A, Supply pin VDD, ground pin GND output pin Z.

2. The size of the NMOS and PMOS will be stored as a variable which can be passed during the instantiation of the inverter symbol. Cadence can use component parameter types which may be static constants, global variables or dependent variables. These can be used in combination with mathematical expression to create parameters. We will use inherited parameter value function pPar which will pass parameter in the design as you set it during the instantiation of the symbol. To begin with in the inverter circuit above select the NMOS and execute Edit Properties Object. In the CDF parameter window of the NMOS, write pPar(“Wn”) M to specify the total width. Observe that the finger width field is automatically changed to iPar(“w”)/iPar(“fingers”) M. Similarly in the PMOS CDF parameter field write pPar(“Wp”) M to specify the total width.


The inverter designed in this way will be similar to the figure shown below.


5-2-2 Creation of a Symbol for the CMOS Inverter for Buffer Chain Follow the procedure in 5-1-2 and create a symbol for the CMOS inverter. Creation of a Symbol 1. In the inverter schematic window execute Create → Cellview → From Cellview. The Cellview From Cellview form appears. With the edit options function active, you can control the appearance of the symbol to generate. 2. Verify that the From View Name field is set to schematic, and the To view Name field is set to symbol, with the Tool/Data Type set as Schematic-Symbol.

3. Click OK in the cellview From Cellview form. The Symbol Generation Form appears. Complete the symbol and save the symbol view.

4. Now we will edit the CDF for this component. For this purpose execute CIW Tools CDF Edit. The Edit Component CDF form appears.

5. Make sure the CDF type is BASE, and click add in the component Parameters section to add the component parameter Wn.

6. The Add CDF Parameter form appears. 7. In the Add CDF Parameter form,

a) Set param type to string b) Set parse as Number to yes c) Set the units to lengthMetric d) Set parse As CEL to yes e) Set name to Wn f) Set default value to an appropriate value. g) Click OK on both the Add CDF Parameter and Edit Component CDF forms. When

placing an instance, specify the value of Wn and it will get passed to the schematic view.

5-2-3 Create the Hierarchical Design : Buffer Chain

1. In the CIW, execute File → New → Cellview 2. Setup the Create New File form with cell name: Buffer, View Name: Schematic and tool

:Schematic. 3. Click OK when done.


4. From the data sheet it is given that each of the minimum size NMOS and PMOS has a W=120 nm and L=100 nm and Gate oxide thickness=2.33 nm. Calculate the gate capacitance of the minimum size inverter. Now calculate the relative size of each inverter with respect to the previous inverter(n) and number of inverters required (m) to drive a load capacitance (CL) of 0.1 pF. Given ox=3.9x8.854x10-14 F/cm, nlogen=Cout/Cin+n, m=loge(CL/Cin)/logen, where Cout and Cin are the input and output capacitance of the minimum sized inverter. Assume Cout=2Cin. The above data gives n4. Calculate the value of m from the above data.

5. Now instantiate each inverter by executing create → Instance. The add instance form appear. Make sure that cell inverter1 and view symbol is selected as shown below:

6. Instantiate the symbol as many times as you need to simulate the buffer chain. Now for each instantiation select the symbol and execute Edit Object Properties. You will see that CDF parameter values are shown with wn and wp variable. Enter the value of Wn=240n and Wp=480n for the 1x inverter.

7. Add as many inverter as required according to the calculation done above and create the buffer chain. In the way shown in 6 above enter appropriate values for the Wn and Wp parameters for all the instantiation so that delay through the inverter chain becomes minimum for a capacitive load of 0.1pF.

8. Add the load of C=0.1pF. Add a input waveform of the type pulse with Period=400 ps, delay=0ps, rise time=3ps, fall time=3ps pulse width=200ps. Also do not forget to add Vdc


source from analog library between the Vdd and gnd terminals. The buffer chain would look something like below.

9. Now simulate the Buffer circuit and determine the rise time, fall time and propagation dealy.

Exercise and Report Follow the stand report writing template for EEE454. You must also include the following : Ring Oscillator 1. Measure the oscillation frequency of the ring oscillator and show its wave shape. Report the Fan out-of one (FO1) inverter delay. From this delay estimate the delay of a FO4 inverter using linear delay model. 2. Why a start-up circuit is needed in real life with a ring oscillator? Show the design of a suitable start-up circuit and explain its operation. Buffer Circuit 1. Measure the rise time and fall time, fall time and propagation delay of the output signal when the clock signal is driven by the minimum sized inverter only. 2. Measure the rise time, fall time and propagation delay of the output signal when the clock signal is driven by the buffer chain. Also give a netlist of the buffer chain to confirm that the parameters have been successfully passed to the netlist. 3. Measure the rise time, fall time and propagation delay of the output signal when the clock signal is driven by the buffer chain with minimum sized inverter in all the buffer instances. Also give a netlist of the buffer chain to confirm that the parameters have been successfully passed to the netlist. 4. Compare the delays in all the above three cases and make comment on their values. 5. Explain why a buffer circuit is used in VLSI design? Explain how a optimal buffer circuit should be designed.

eee454 vlsi i laboratory laboratory module 5: design of...

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