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Enabling the A.I. Era: From Materials to Systems

Sundeep Bajikar

Head of Corporate Strategy & Market Intelligence, Applied Materials

A.I. Summit at Semicon Korea | January 23, 2019

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Forward-Looking Statements

This presentation contains forward-looking statements, including those regarding

anticipated growth and trends in Applied’s businesses and markets, industry outlooks,

technology transitions, and other statements that are not historical facts. These statements

are subject to risks and uncertainties that could cause actual results to differ materially

from those expressed or implied by such statements and are not guarantees of future

performance. Information concerning these risks and uncertainties is contained in Applied’s

most recent Form 10-Q and other filings with the SEC. All forward-looking statements are

based on management's current estimates, projections and assumptions, and Applied

assumes no obligation to update them.

2

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Key Messages

* A.I. refers to Machine Learning and Deep Learning approaches.

A.I. Computing

Requires a New

Semiconductor

Playbook

A.I.* Requires

New Computing

Architectures

PART 1 PART 2

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Key Messages

A.I. Requires

New Computing

Architectures

PART 1

What is different

about A.I. computing?

Empirical analysis –

A.I. / IoT unaffordable

with current

computing model

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2017 2018E 2022E

HOME and BUILDINGS

HUMANS

INFLECTION YEAR Data generated by machines > humans

SMART FACTORIES

SMART VEHICLES

Humans

Machines

1.5ZB 2ZB

>10ZB

53% 44% <10%

SAFETY and SECURITY

SOURCE: Applied Materials model based on forecasts published by Cisco, Intel, Western Digital

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Explosion of Data Generation

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Source: Computer Architecture: A Quantitative Approach, Sixth Edition, John Hennessy and David Patterson, December 2017, Applied Materials internal analysis

Deep Learning Enabled by Processing Abundant Data

What’s different about

A.I. computing?

Memory Bound

Performance limited by memory latency

and memory bandwidth

High Data Parallelism

Identical operations can be done on

multiple chunks of data in parallel

Low Precision

Training and inference require much

lower floating point (16 bit) and integer

(8 bit) precision

Relative to traditional

CPU architectures

Traditional multi-level on-die cache

architecture is unnecessary

Traditional deep instruction pipeline

and out-of-order execution are

unnecessary

Traditional 64 bit or higher precision

data paths are unnecessary

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Data Algorithms

ML / DL

RELATIONSHIP BETWEEN

Complexity of algorithms

VERSUS

Abundance of (training) data

+ affordable high-

performance computing

AI is about

“relentless classification”

Data quality and size are

making AI a reality

Source: Applied Materials internal analysis.

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ML / DL

CASE STUDY: Google Translate Circa 2010

► Complex algorithms based on

grammar and semantic rules

► Developed by team of linguists

70% accuracy

Source: Applied Materials internal analysis.

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ML / DL

CASE STUDY: Google Translate Today

► Simple algorithm

► Trained using every single web page

available in English and Chinese

► No Chinese speakers on team

98% accuracy

Source: Applied Materials internal analysis.

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Homogeneous / Discrete Compute Era

10

From Homogeneous to Heterogeneous Computing

CPU

Normal Compiled

/ Managed Code (Office, OS, Enterprise)

CPU

Client CC, Search,

Audio, VOIP

GPU

CPU

Imaging,

Video Playback

GPU

ASIC / FPGA

CPU

Gaming, HPC, Highly

Parallel Workloads

GPU

CPU

AI Workloads: Training, Inference,

Analytics, etc.

GPU

ASIC / FPGA

Heterogeneous Compute Era

CPU 0

CPU 2

CPU 1

CPU 3

CPU 4

GPU

Media

ISP

Audio

ASIC

FP

GA

Exploits data level parallelism

Uses the most energy-efficient

compute engine for a given job

Source: Applied Materials internal analysis.

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y = 0.0081x1.3065

R² = 0.9563

-

5

10

15

20

25

- 100 200 300 400 500

DR

AM

Sh

ipm

en

ts (

EB

)

Incremental Data Generation (EB)

11

In Current Compute Model…

y = 0.0022x2.0399

R² = 0.9569

-

100

200

300

400

500

- 100 200 300 400 500

NA

ND

Sh

ipm

en

ts (

EB

)

Incremental Data Generation (EB)

DRAM NAND

Source: Cisco VNI, Cisco, Gartner, Factset, Applied Materials internal analysis

2006 to 2016 data from Cisco and Gartner. 2017 to 2020 projections from Cisco for data generation (VNI IP traffic), and industry average estimates for DRAM and NAND content shipments

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y = 0.0081x1.3065 R² = 0.9563

-

20

40

60

80

100

120

140

160

180

- 500 1,000 1,500 2,000 2,500

DR

AM

Sh

ipm

en

ts (

EB

)

Incremental Data Generation (EB)

1% adoption

of L4/L5

Smart Car

y = 0.0022x2.0399

R² = 0.9569

-

2,000

4,000

6,000

8,000

10,000

12,000

14,000

- 500 1,000 1,500 2,000 2,500

NA

ND

Sh

ipm

en

ts (

EB

)

Incremental Data Generation (EB)

1% adoption

of L4/L5

Smart Car

12

A.I. / Big Data Era Needs New Compute Models

Source: Cisco VNI, Cisco, Gartner, Factset, Applied Materials internal analysis

2006 to 2016 data from Cisco and Gartner. 2017 to 2020 projections from Cisco for data generation (VNI IP traffic), and industry average estimates for DRAM and NAND content shipments

1% SMART CAR

ADOPTION

5X MORE DATA

8X MORE DRAM

IN 2020

1% SMART CAR

ADOPTION

5X MORE DATA

25X MORE NAND

IN 2020

DRAM NAND

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A.I. Needs New Energy-Efficient Compute Models

0%

5%

10%

15%

20%

25%

0

50

100

150

200

250

2016 2017 2018E 2019E 2020F 2021F 2022F 2023F 2024F 2025F

A.I

. a

s a

% o

f G

lob

al E

lec

tric

ity C

on

su

mp

tio

n (

%)

A.I

. TA

M (

$B

)

TR

AIN

ING

IN

FE

RE

NC

E

Source: Applied Materials internal analysis.

Estimated current

computing models

for A.I. represent 25%

of global energy

consumption by 2025

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Key Messages

A.I. Computing

Requires a New

Semiconductor

Playbook

PART 2

From classic 2D scaling

to architecture

innovation

From traditional

materials to materials

breakthroughs

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“Classic 2D Scaling” to Architecture Innovation

Source: Applied Materials internal analysis . Performance broadly refers to speed or power efficiency. ~2x refers to doubling of performance every two years consistent with Moore’s Law.

ISS Blog post #1: Nodes, Inter-nodes, Leading-Nodes and Trailing-Nodes

ERA

ORIGINAL

PERFORMANCE

PERFORMANCE

GAIN HOW

1x ~2x PC, Mobile

Classic 2D scaling When Moore’s Law scaling was

at it’s peak. Assumes no major

architecture changes

1x ~2x to

2,500x A.I. / IoT

Architecture Innovation Small benefit from Moore’s Law

scaling

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Litho-enabled Moore’s Law is Slowing

PERFORMANCE IMPROVEMENTS OVER TIME (VS. VAX-11/780)

100,000

10,000

1,000

100

10

19

78

19

86

20

03

20

11

20

15

20

18

25% per year

52% per year

23% per year

12% per year

3.5% per year

End of Dennard Scaling

Limits of parallelism of Amdahl’s Law

End of Moore’s Law

VAX-11/780

TIME BETWEEN LOGIC NODES IN YEARS

5.3

2.5

2

1.8

14 to 10nm

22 to 14nm

32 to 22nm

45 to 32nm

SOURCE: Computer Architecture: A Quantitative Approach, Sixth Edition, John Hennessy and David Patterson, December 2017 SOURCE: Bernstein

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A.I. Enabled by Materials Breakthroughs

Source: Applied Materials internal analysis . Performance broadly refers to speed or power efficiency. ~2x refers to doubling of performance every two years consistent with Moore’s Law

ISS Blog post #2: Nodes, Inter-nodes, Leading-Nodes and Trailing-Nodes.

ERA

ORIGINAL

PERFORMANCE

PERFORMANCE

GAIN

MATERIALS

ENGINEERING

1x ~2x PC, Mobile Unit Materials

1x ~2x to

2,500x A.I. / IoT

Materials Breakthroughs New devices, 3D techniques,

Advanced packaging

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Architecture Innovation

High Memory Bandwidth

Performance limited by memory

latency and memory bandwidth

High Data Parallelism

Identical operations can be done on

multiple chunks of data in parallel

Low Precision

Training and inference require

much lower floating point (16 bit)

and integer (8 bit) precision

enabled by

Materials Engineering

New Devices

On-die memory – e.g. MRAM

New memory – e.g. Intel® 3D XPoint™ technology

3D Techniques

Self-aligned structures – e.g. vias,

multi-color patterning

“Side-to-side” to “top-to-bottom”

– e.g. COAG

Advanced Packaging

Stacked DRAM – e.g. HBM / HBM2

Logic-DRAM

Sensor-Logic

Intel and 3D XPoint are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

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NEW PLAYBOOK NEEDED

Design + Manufacturing 19

ENABLED BY

Advanced packaging

New structures / 3D

New ways to shrink

New architectures

New materials PPAC

POWER

PERFORMANCE

AREA-COST

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Example: STT-MRAM

SAF PINNED LAYER

CAPPING

MGO CAP

FREE LAYER

TUNNEL BARRIER REFERENCE LAYER

SEED LAYER

New Memory Device Enabled By Materials Breakthrough

Source: Applied Materials internal analysis .

20

>15 individual layers of film

in MTJ stack

Each layer 0.2-to-2nm thin

Requires highly complex

process equipment

Requires materials

(Element, Composition,

Stack) and Etch co-

optimization

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Investments to Enable New Semiconductor Playbook

Maydan

Technology Center Applied Ventures META Center

Applied Packaging

Development Center

AI DESIGN FORUM

A. I. Design Forum

World’s most advanced

300mm R&D lab with

$300M invested in

past 3 years

>$250M assets

under management and

>30 active companies

Expands R&D capability

to support new types of

collaboration from

lab to fab and accelerate

innovation from materials

to systems

Announced November 2018

Scheduled to open in 2019

Fully-integrated 300mm

advanced WLP process

flow and a full suite of

equipment

17K sq. ft. cleanroom,

fully staffed

Expanded ecosystem

engagements

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A.I. – Big Data Era = the biggest

opportunity of

our lifetimes

Hardware renaissance

Materials innovation to enable new architectures, structures, ways to shrink and packaging approaches

New ecosystem playbook for Design and Manufacturing

UNLOCKED BY

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