formed by the algebraic sum of the ... be able to readjust or pad the capacito,rs without causing...

OPTIMIZATION OF ANALOG COMPUTER LINEAR SYSTEM DYNAMIC CHARACTERISTICS

By Charles H. Single and Edward M. Billinghurst BECKMAN/Berkeley Division

Richmond, California

Summary

The characteristics of the linear computing elements of the general-purpose electronic differential analyzer are discussed. Equivalent circuits are given for these elements. Criteria for optimization of the linear computing system in order to obtain maximum computational accuracy are given. Examples of the effects of optimization in improving system stability, transient response, and increasing bandwidth of high and medium accuracy computation are shown.

Introduction

The modern electronic differential analyzer (EDA) is widely used for solutions of various linear and non-linear mathematical eqlB.tions and for the simulation of complex physical systems. The modular construction of such computers allows a large problem range. 1 Optimization of individual unit characteristics does not always lead to best overall computer performance; therefore, unit design must be undertaken with as complete a knowledge of final system configurations aIJtd accuracy requirements as possible. 2, 3, ,5

This paper reviews proven design techniques that have been us ed to optimize the linear s ys -tem dynamic accuracy of the EDA. The techniques have resulted in simultaneous improvement in these important system areas: 1) stability margin, 2} transient response (both small and large signal), 3) bandwidth of high accuracy computation, 4) bandwidth of medium accuracy computation ..

For the EDA, improved stability margin considerably increases the flexibility of the computer. Difficult or unusual prdblems involving high gain loops, remote equipment operation, peculiar amplifier feedback and input networks, etc., can be patched with essentially no tendency for system oscillation.

The improved transient response and extenred bandwidth of high accuracy computation have considerably improved the most basic performance criterion: Computational accuracy. This should be of general interest since many of these techniques can easily be applied to existing computers at small cost.

With the recent extension of the EDA to also serve as an iterative differential analyzer (IDA), the bandwidth of medium accuracy computation becomes more important. The numerical techniques used with the IDA often res ult in repetitive steps to final problem solution. This is coupled with a desire for higher speed in the repeated partial-solution phase to minimize total problem time. The accuracy limitations associated with the extension of computing frequencies beyond a few hundred cycles per second are diE£ussed.

Basic Considerations

Static accuracy for both the EDA and the IDA is achieved through high-gain, low-drift dc amplifiers, precise and stable resistive networks, and stable, high-resolution coefficient potentiometers. Dynamic accuracy and stability margin are of at least equal importance. For optimization of these ac characteristics the composite system closed-loop transfer function should approach its ideal most closely. Contributing ac factors inclure integrator capacitor stability, equivalent circuit of network resistors and capacitors, potentiometer capacitive loading, amplifiersystem transfer characteristics, and amplifier output impedance. The interaction of these factors is further complicated by practical considerations such as system wiring capacity. All of these factors should be included in the system performance analysis.

The improved system stability margin of the optimized-computer is of great value for accurate simulation of complex and/ or highgain loops of either differential or algebraic form. It is also advantageous with simulations requiring unusual feedback configurations or large capacitive loads. The better acc uracy comes from the fact that no additional stabilizing capacitors are needed to avoid system oscillation. Such capacitors can cause large dynamic error. However, for many problems the stability margin typical of the non-optimized computer is still sufficient. In either case, the principal error limiting the bandwidth of high accuracy computation will be caused by net system phase error, since even slight phaseshift errors produce significant dynamic errors.

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From the collection of the Computer History Museum (www.computerhistory.org)

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The large effect of small undesired phaseshift can readily be shown by examination of a steady state sinusoidal signal with only small phase error. With error defined as the difference between the ideal and actual signal:

() (jw) = Ei (jw) - Ea (jw) = Ei [sinwt-sin(wt-</»]

(1)

The per-unit error due to this small phaseshift is:

() lEi (jw) = sin wt - sin (wt-</» ~ </> cos wt (2)

The maximum amplitude of the per-unit error is therefore equal to the phaseshift in radians:

(3)

In any problem the net phase error~ </>o~ is found by

m

</> = w ~ o j=l

(4)

where 'To is the equivalent first order time constant formed by the algebraic sum of the inevitable undesired high frequency poles and zeros introduced by the practical system. The lead or zero terms are taken as positive and the lag or pole terms taken as negative with ~ k the damping factor of any quadratic terms.

To hold the maximum amplitude error due to undesired phaseshift below 0.2% at 100 cps (0. 120 ) in a particular problem closedloop~ or between two signal voltages inside a loop, the equivalent first order time constant l 'TOI of the loop or signal path must be sma ller than 3. 2 JJ sec. If there were only one undesired pole l the breakpoint frequenc~ (f = 1 )' would have to be

~ higher than 50 1 000 cps for this 0.2% dynamic error at 100 cps. In practice more than one undesired pole will exist; this requires individual breakpoint frequencies to be much higher than 50,000 cps.

A conventional method of achieving lower phase error without the high bandwidth cited above is to allow individual elements to have a quadratic characteristic with a

damping factor less than O. 5. This method considerably reduces the stability margin and tends to cause oscillation in problems involving complex or high gain loops. A better technique avoids the underdamped quadratic characteristic by careful placement of a closed-loop dipole with the zero separated just sufficiently from its associated pole to mask the low frequency phase errors caused by the undesired poles. The amplitude peaking caused by the dipole can be limited to less than a few tenths of one decibel. Application of the technique will be discussed in detail later.

The amplitude erl"or from an undesired pole is the difference between the ideal and actual magnitude. For small phase error (</>~wT«lL the amplitude error is:

IMal = 1---

\/1 + (wT)2

2 2 1 - (1 -~ ) ~i¥L

Thus, the phase error from one pole, () , is much larger than the amplitude error: € p:

() A../ WT » p""""

2 (W'T) ""v

2 -"V€ P

Hence, amplitude error can be neglected with respect to phase error within the bandwidth of high accuracy computation.

Passive Component Characteristics

The passive components in the linear system are resistors, capacitors l and coefficient potentiometers. Their characteristics will be reviewed briefly~ followed by

(5)

(6)

a more detailed discussion of operational amplifier-system characteristics, and then the optimized linear system results will be shown.

Computing Resistors

Most computing resis tors at present are wire-wound because they have better long term stability than other types. This situation may well change with continuing development of other resistor types, e. g., metalfilm. Conventional specifications such as value~ stability, temperature coefficient, power rating, packaging and ac characteristics are somewhat inadequate. Value may


vary with self-heating, and with time due to changes in mechanical stress of the wire. Thermal potentials may exist from even small temperature gradients. Encapsulation can aggravate self-heating effects and may not be necessary within normal humidity limits. The resistors should be evaluated as used in their expected environments to establish such specifications.

The importance of relative or absolute value is primarily determined by the grouping of resistors allowed in the computer. If resistors aTe limited to definite groups, only the relative match of resistors within each group is important in establishing basic dc accuracy limits for the computer system. The more flexible arrangement, where resistors can be conveniently assigned to any amplifier, requires preCise matching throughout the computer system.

The ac characteristics of wire-wound resistors for frequencies below 100 Kc can be approxima ted by the circuit shown in Figure 1. The driving-point impedance of this approximation is:'

1 C

Er Z (s) =,.-- (s) =

r ~r

Rdc (~ s + 1) J:\dc

2 Rdc 1 s +,- s + 'LC""'

=

For resistors wi thin the conventiona 1 range of lOOK to 1 meg. the time constant. L • can beheld to less than

~ 10 -7 sec -1 (breakpoint beyond 1. 5 megacycles) whereas the capacitor time constant Rdc C will typically be between 2 x 10-6 and 4 x 10- 6 sec- 1(breakpoint as low as 40 Kc). This allows simplification of the resistor transfer characteristic to:

1 1

s+~ dc

(7)

(8)

In the summing amplifier. the undesired poles of the resistors contribute no lowfrequency phase error if Zf and Zi are perfectly ma tched. Mismatch in resistor capacity can cause either phase lead or lag as determined by Equation 4.

For integrator amplifiers, the resistor shunt capacity must be kept as low as possible since there is no convenient way to cancel its error effect. Four picofarads of capacity in para llel with 1 meg input resistors causes O. 25'fomaximum error at 100 cycles. With integrator feedback capacitors restricted to values greater than 0.01 /oAf, 100 cps computational frequencies can only be achieved with lOOK input resistors. Four pf in parallel with a lOOK input resistor causes only 0.0250/0 maximum amplitude error.

These considerations make the presently available wire-wound resistor ac characteristics acceptable, i. e., resistor phaseerrors essentially cancel in summing amplifiers and are small enough with the lOOK integrator input resistors normally necessary to achieve high computational frequencies.

Integrator Capacitors

The precision capacitor used for integration is a much less ideal component than the precision resistor, i. e., the practical capacitor approaches its ideal characte~- 6 istic Zc (s) = _1_ much less closely. '

sC Capacitors generally have a larger temperature coefficient, are less stable in value, and have more complex ,lectrical characteristics than resistors.

Most Polystyrene capacitors have a temperature coefficient of -0.010/0 10c to -0.0120/0/oc. To avoid value variation with ambient temperature changes they are generally mounted in an oven. The oven temperature usually is set above expected maximum ambient temperature to avoid the expense of a cooling system. Capacitor leakage increases with temperature, so the oven temperature should be set for the lowest temperature consistent with ambient requirements. '

Even carefully selected capacitors in a constant environment show, variation in value with time. Thus, it is desirable to be able to readjust or pad the capacito,rs without causing thermal disturbance.

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Variations in temperature coefficient between capacitors and the fact that some capacitors show a temperature retrace error~ i. e. ~ they do not return to the same exact value when returned to precisely the original temperature~ make the avoidance of temperature change desirable during adjus tment. Another physical characteristic that affects value is the change in mechanical stresses with applied voltage.

The electrical characteristics are quite complex as show~ 0/ the equivalent circuit of Figure 2. ~ This 1 JJf equiva-lent circuit is valid for 0.001 cps "f" 100 qls. It is consistent with these easily measured capacitor error effects:

1) integrator drift increases with voltage level~ due to dc leakage

2) effective leakage increases with frequency~ due to dissipation factor

3) capacitor value reduces with frequency~ due to dielectric characteristics

4). integrator output va'ries with capacitor history~ due to dielectric absorption.

The simplified equiva lent circuit, Figure 3~ is usefulior steady-state sinusoidal ana~yseos. The leakage reSistance, RL • var1es 1nversely with frequency. The capacity value can be considered constant for many analyses, as the variation is only about 0.02% per decade frequency change. However, this variation in value with frequency is quite important in adjusting or padding the capacitor to its "precise value." For computer use, capacitor value should be determined at frequencies consistent with those used in the computer. This can conveniently be done with the various resistance-time measurements where the time constant of the capacitor resistor combination is determined. 6, 7 ~ 8 Capacitor value is then based on the same resistance standard used for computer resistor measurement. Details of these electrical characteristics are given in Appendix 1.

Coefficient Potentiometers

For extension of the bandwidth of high accuracy computation~ the phaseshift from potentiometer input to wiper arm is an important c0nsideration. 9 An equivalent circuit for the typical computer multi-turn. copper-mandrel, coefficient potentiometer is shown in Figure 4.

Co of Figure 4 is essentially constant for all potentiometer settings~ and only slightly dependent on potentiometer value. This equiva lent circuit is va lid within the limits of Table I.

Table I

Equiv. Ckt. * Figure 5

Co Freq. Limit Freq. Limit

R (cps) (cps)

10K 200pf 1. 1(10)3 6.6(10)3

20K 204pf 550(10)3 3.3(10)3

30K 208pf 350(10) 3 2.1(10)3

50K 216pf 200(10) 3 1. 2(10) 3

lOOK 224pf 82(10) 3 590

* The equivalent circuit frequency limit is derived from potentiometer experimenta I step function data.

The transfer function of the equivalent circuit is

Eo "Y[(1-"Y)RCos+1]

Yi (s) = "Y (1 - "Y) R (2 Co + C ext ) s + 1

"Y (7'1 s + 1)

7'2 s+l

where "Y is the pot arm displacement from the grounded end.

(9)

Equation 9 is a simple lead-lag, or lag-lead transfer characteristic. Phaseshift~ cp, for

° °d 1 ° 1 ° -1 -1 SlnUS01 a slgna s 18 cp = tan W7' 1 - tan W 7' 2.

(10)

However. for both EDA and IDA error analysis the frequencies involved allow further simplification. For W7'l < 0.1 and W7'2<0.1, cp can be approxima ted by W (7' 1 - 7'2): .

CP~W7'net = w(7'l - 7'2) = W RCo(l-"Y) (1-2"Y- k y)

Cext where k=-

Co

(11)

Universa 1 curves showing normalized phaseshift cp/ W R Co~ are given in Figure 5. These curves are valid for any potentiometer value, displacement~ ca pacitive load.and frequency within the limits of Table I.

The amplitude error at low frequenCies


can be obtained from Equation 9 as:

1/2

(l2)

(13)

Comparison of Equations 11 and 13 shows that amplitude error is smaller than pmse error by an order of magnitude in the frequency variable, w. Thus the potentiometer error is adequately represented by considering only phase error if w T 1<0. 1 & wT 2<0.1.

From the simple equivalent circuit of Figure 4 it would be easy to compute a compensating capacitor placed from potentiometer wiper to either potentiometer input or ground that would exactly cancel phase error for any particular displacement and resistive-capacitive loading. However~ this is not practical with the large number of coefficient potentiometers of various displacements and loadings.

A more practical solution to this problem is to compensate the potentiometers by using tap-capacitors to avoid displacement dependence. 10,11 This makes it possible to achieve excellent square wave response to fast-rise step inputs and much improved phase error. Details of these teclmiques are given in Appendix 2 .. A few such capacitively compensated potentiometers will prove invaluable for critical simulations in even a moderate-sized computer.

From the above discussion it is apparent that higher potentiometer computational accuracy can be achieved by minimizing both external load capacity and potentiometer value.

At dc the potentiometer transfer characteristic is a function of displacement~ "I, and resistive load, RL :

Eo

Ei

where

"I (14) l+'Y(l-'Y)a

The slope as a function of displacement is:

2 1 +a "I

2 [1 + 'Y (1 - 'Y) al

At "I = 1 the largest slope is found:

=a+1 a'Y max

If coefficient-setting accuracy of one part in 10~ 000 is desired and minimum RL is lOOK:

* Std.

(15)

(16)

Set. Needed No. of Std. a max....!... Acc 'y. _ No. of Turns req.

Rp ~ slope· 2 '1Urns ~10%) (%)

30K O. 3 1.3

50K 0.5 1.5

1 5,000

1 5,000

7,500 11,950 159

* Maximum setting error is equal to 1/2 potentiometer resolution.

If standard potentiometers are used, the 30K value is preferred since it has 40% less computational error with the same capacitive load. Both potentiometers have adequate resolution.

Opera tional Amplifier System Characteristics

The operational amplifiers in an analog computer have important effects on the dynamic accuracy of linear computation. A knowledge of the performance of operational amplifiers and their associated passive networks in a large computer is necessary in order to make judicious choices in amplifier and system design for optimum results. The definition of optimum may vary with the particular problems to be solved. It may mean high accuracy at slow computing speeds, or medium accuracy at faster computing speeds. In any event~ accuracy will tend to decrease as higher frequencies are encountered in the problem solution.

General Purpose Computer Amplifiers

Computer amplifiers are primarily used to perform the opera tions of summation, integration with respect to time, and multiplication by a constant. In addition, they

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may be used with special networks as limiters" transfer function generators l dividers or square root extractors (in association with computing multipliersL inverse function generationl etc. The amplifiers are always operated in a feedback or closed-loop configuration. As a r.esult" their open-loop frequency response characteristics must be designed so that the amplifiers are stable under any permissible computing configura tions. They must also have low dc drift and low gridcurrent. 1 As operational amplifiers" they must accurately perform their mathematical functions. Accuracy of computation requires high open-locp gain; stability requires that the gain be re-duced in a fairly restricted manner. Thus" a compromise must be made between accuracy and stability.

Open-Loop Transfer Function

Figure 6 is a block diagram of a typical dc amplifier with chopper stabilization to minimize drift effects. The open-loop transfer function is given by:

Eo(S) -- = G (s) = (G 1 (5) + G2 (s) ) G3 (s)

e (s) (17)

G1 and G3 can be calculated from standard linear vacuum tube and network theory. G2.ean be satisfactorily approximated by considering the chopper modulated ac section as a frequency-independent amplifier associated with the input and output filters. G1 + G3 contribute a cluster of equal numbers of poles and zeros fairly close to the origin., 03 will usually have a pole in the neighborhood of 10 to 100 cps and other poles in the range between 100 Kc to several Mc. These are in addition to those contained in (Gl + G2). The lowfrequency pole is inserted to obtain a frequency response approximating a 20 db decade roll-off until the gain is below zero db. If the low frequency pole is at 10 cps with gain at that frequency of 105" the frequency response goes through unity gain at one Mc.

Once G1" G2 and G3 are known" the amplifier open-loop pole-zero plot can be drawn. A typical pole-zero configuration is shown in Figure 7. The poles and zeros nearest the origin are due to G1 -f: G2" the fourth pole is the low frequency pole of G3• The dotted dipole combinations represent incomplete compensation of inter-stage coupling networks. These generally have

negligible effect on the closed-loop response providing they are not widely separated. The cluster of poles far to the left rEWresents the high-frequency poles of G1 and G3. Since several decades separate the lowest and highest poles" the drawing is not to scalel but merely indicates the relative positions.

Determination of Closed-Loop Transfer Function

The amplifierl as actually installed in the computerl is represented by the diagram of Figure 8a. Figure 8b is the currentgenerator equivalent circuit.

Zi is the input impedanc e from a pa rticula r signal source" E i•

Zg is the impedance from summing junction to ground.

Zr is the feedback impedance.

Zo is the output impedance of the final stage of the amplifier.

ZL is the load impedance, including the output to ground capacity of wires connected to the output terminal. -G(s) is the open-loop" open circuit gain of the amplifier.

The following equations can be written from Figure 8b:

E.Y. ~ -E Yf + e(Y. + Y + Yf > ~ 1 0 1 g

Substitute Y == y. + Y + Yf a 1 g

Solving for Eo/Ei" we obtain:

~GYfYO r-

Eo _:f~a Vb - Yf 2 1 -Ei

i 1+ GYf Yo 2

YaYb-Yf

Yf (18)

GYo

The extension to multiple inputs results in the following expression:


E =1- ~ o \ i=1

Ei Zf) Z.

1

GYf YO

Ya Yb - Y/

GYf YO 1+-----"""l2~

Ya Yb - Yf

n Where Ya = Y +Yf + L Yi "

g i=1

(19)

The first bracket of Equation 18 is the ideal mathematical operation to re performed. The second bracket determines stability and error in computation. For most computing configurations~ the third bracket [ Yf I ,so this term can

,1-~1~1 L ~ usually be ignored. It is necessary to consider it if the respmse to very high frequencies (greater than approximately 300 Kc) is of interest. We note a Iso tha t Yf

1-~

will not generally produce a right-half plane pole, so it does not affect the stability.

L.i is usually a resistor with characteristics as discussed earlier. Zf will be the same type of resistor as Zi~ or an integrating capacitor. Zg i~ the input impedance. to the amplifier, including the chopper sectlOn~ in parallel with the capacity of wiring connected to the grid or summing junc tiona The amplifiers in a la rge computer must be located some distance away from the patchboard and passive elements. As a result~ the summing junction capacity~ Cg~ is usually of the order of 500 to 1000 pf.

Z will be adequately represented by a resista~ce if the output stage is designed for low impedance. This is generally a requirement in a computing amplifier to allow it to deliver several milliamps output current.

Ya is the parallel admittance of Yi~ yO' and Yf. lt can usually be replaced by a parallet R-C circuit. Yb can frequently be represented by a single R-C circuit since it is the parallel admittance of Yf • Yo ar;d Y • Ho~ever, Yb may be more complIcated tllan a smgle parallel R-C circuit if Y is not a pure R-C combination. For typicaIr summer configurations"

C will be large compa red to Ci and Cf , so th~se quantities will usually have small effect on Ya • Similarly C L dominates Cf in Yb •

Returning to Equation 18~ the expression in the first bracket, is the transfer function desired for the solution of problems. This expression is modified by the second bracket, thus introducing extraneous roots in the problem solution. For accurate computatim, the extraneous roots must be kept as far out as possible.

The middle bracket expression of Equation 18 is of importance in determining the amplifier closed-loop extraneous poles and zeros. It also indicates the amplifier stability. This expression is well su\t:fd to analysis by root-locus techniques, especially for qualitative determina tion of the effects of external summing junction and load capacity.

Figure 9 is a root-locus plot for unity gain summer using 1 M resistors. This is a typical configuration found in a general-purpose computer, where the summing junction and load capacities are fairly large due to the long lengths of interconnecting wires required. We see here that the dominant portion of the root-locus is bowed somewhat due to the action of the zero produced by Yf. Yb is a pole prirl1arily due to the loao capacity and open-loop output impedance. Ya is a pole due to the input and feedback resistors in parallel, shunted by the grid to ground capacity. Obviously .. as either CL or C g increases, the root-locus will be displaced more to the right, and the closed-loop poles will show less damping. This root-locus demonstrates the fact that the externa 1 networks and wiring capacity have a major effect in determining the actual summer response in the system.

The underdamped characteristic of the configuration of Figure 9 is undesirable due to low bandwidth and excessive phaseshift. Amplifiers of this type are particularly unsatisfactory when used in problems involving multiple closed-loops~ e. g. in high gain algebraic loops. Multiple loop configura tions have a large tendency toward self-oscillations.

Figure 10 shows a root-locus plot for a summer which has extra capacitors pa ralleled across Zf and Zio Proper selection of these capacitors gives an over-damped response with much wider bandwidth: e. g. 30 - 50 Kc instead of 12 - 15 Kc, and no peaking. The compensa tion also produces a dipole in the

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vicinity of the zero caused by Yf. This dipole adds a slight phase lead to help reduce low frequency phaseshift. Multiple loops using these compensated amplifiers have much less tendency to oscillate. The amplifiers can also drive larger capacitive loads then the uncompensated type. This is important when amplifiers must drive remote equipment. Load capacity can be increased by at least a factor of 10. Capacitor values must be selected so that Zf and Zi have equal tim~ constants. That iS I X10 (lOOK) resistors are compensated with 10 times the capacity associated with Xl (llVl) resistors. Addition of compensating capacitors is very important in increasing overall linear system stability and the bandwidth for a given accuracy of computation. It should be noted that input resistors associated with integrators must have no compensating capacitors~ since in this case the capacitors will cause additional undesirable phase error.

The selection of the proper values of compensating capacitors for the computing resistors is based on optimizing overall-performance of coefficient potentiometer-amplifier res'ponse~ rather than amplifier response alone. Summers are very often driven from coefficient pots~ and the capacitor associated with the amplifier input resistor loads the pot. Therefore~ the compensating capacitor value is chosen to give minimum phase error and maximum bandwidth from pot input to amplifier output. In computers using 30K pots J the best values of compensation are about 43 pf with 1M resistors~ and 430 pf with lOOK resistors.

Conclusions

We have discussed the linear computing elements from the standpoint of their actua 1 equiva lent circuits and their relationships to computing accuracy, system stability, and system bandwidth.

Computing resistors are shown to require minimum shunt capacity in their construction J and the shunt capacity must be equalized for all resistors. Minimization of the capacity is required for small phase errors in integrators. Capacity match is required for small pha se errors in summer amplifiers. They should have a means of adjustment if their value is likely to change with age.

Computing capacitors must be stable in va lue J have large leakage resistance, and minimum dissipation factor and dielectric absorption (soakage) effects. They should

be installed in a controlled temperature environment and be easily adjustable.

Coefficient potentiometers require high resolution for accurate settings~ and low resistance value to minimize capacitive loading errors.

Operationa I amplifiers must be designed to be stable under any permissible computing configuration in the computer system. In addition, summing resistors should be capacitively compensated to produce maximum bandwidth and stability in multiple loops and when the amplifier is driving large capacitive loads.

The following examples indicate the improved computer performance obtained by the careful consideration of the design of the linear system. The data was obtained from a standa rd BECKMAN EASE® 1100 Series computer using compensated resistors, 30K coefficient pots J Polystyrene computing capacitors and EASE® Model 1148 Operational Amplifiers.

Improved summer amplifier bandwidth is shown by Figure 11. The absence of overshoot indicates an overdamped (dominant first-order) system. The rise time of about 15 f,.t sec indicates a bandwidth of approxima tely 30 Kc.

Figure 12 shows the ability of a summer to operate with large summing junction or load capacity. The step response is still well damped with as much as O. 3 f,.tfd load capacity. The uncompensated amplifier would oscillate with as little as 0.02f,.tfd.

Figure 13 shows the stability of loops with up to 19 unity gain amplifiers. Unity ga in loops will oscillate with as few as 3 to 5 uncompensated amplifiers.

Figure 14 illustrates the gain possible in a three-summer loop with a coefficient pot. The response is still damped at a loop gain of 8~ while uncompensated amplifiers will oscillate at a gain of less tha n 2.

The steady-state error of a three-amplifier oscillator is easy to measure. It uses all of the basic components of the linear system: Resistors, capacitors, coefficient potentiometers~ and amplifiers. Therefore J it is useful in demonstrating the balanced or optimized system design.

The three-amplifier oscillator uses two integrators, one summing amplifier J and one


to two coefficient potentiometers. The frequency of the oscillator varies with loop gainl

f = Vloop ga in/2 1[.

The steady state error occurs as a slight divergence or convergence in voltage amplitude. This can be measured over many cyclesl or by reading successive peak voltages. Both techniques are useful over the frequency range of interest O. 001~ f ~ 100 cps. The data can be plotted more conveniently as damping" ~ = a/wn, i.e' l amplitude decrement per radian.

Figure 15 shows component damping l vs. frequency for a three-amplifier oscillator with a maximum loop gain of 105 which gives a maximum frequency of 50.4 cps. Note that the loop gainl or frequency, is varied by coefficient potentiometer displacement, 'Y. The capacitor loss is approximated by a constant dissipation factor of 1. 5 x 10- 4, causing a frequency independent convergent effect. The resistor ac mismatch can cause either a convergent of divergent effect as determined by the net lead or lag in summing am-plifier. Note that phase error effects in-crease with frequency. The large spread is for 3IJ.sec net mismatch; the smaller spread is for 21J. sec mismatch. Current production achieves less than 21J. sec worst case mismatch" or less than ±1. 0 pf spread in the one meg capacitively compensated resistor. A slight lead or convergent effect comes from the two integrator input resistors. The potentiometer effect is initially convergent due to lead then divergent due to lag" and finally zero at full displacement .. 'Y = 1. The potentiometer data is for uncompensated 30K potentiometers under 660 pf capacitive load. This error effect could be reduced by a factor of 5 with the two-tap compensated potentiometer" i. e. essentially eliminated.

Figure 16 shows the combined errors of Figure 15. Note that phase error of the uncompensated potentiometer causes the oscillator to go divergent between 22 and 34 cps. Typical cross-over frequency for non-opt~ized computers is between 4 and 5 cps. ThlS is very easy to check" since the oscillator amplitude is neither convergent nor divergent at the cross-over frequency.

A loop gain of 104yields an fmax of 16 cps whic h is more common for the EDA. The potentiometer error is too large at loop gains of 10 as shown above. For such high gain loops compensated potentiometers should be used. (10)5 loop gain will occur

more often in IDA problems. Figures 16 and 17 show the balanced error that is achieved for the EDA at loop gains less than 104• Note that the capacitor dissipation effect offsets the damping curve approximately the same amount that the summing amplifier resistor mismatch spreads the curve, and approximately the same amount the potentiometer capacitive load distorts the curve. It is on this basis that optimum design is claimed. No error source is over-emphasized. and the excellent system stability margin has been achieved.

Although there is a rather large class of problems for IDA application that do not depend on dynamic accuracy for correct solution there is an even larger class of problem~ whose accuracy will be severely limited if dynamic accuracy is poor. Caution should be exercised in extending IDA computationa 1 frequencies to obtain faster problem solutio~ unless careful attention is paid to the dynamlc error factors reviewed in this paper.

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APPENDICES

1. Capacitor Characteristics

Dc Leakage

The dc leakage of the integrator capacitor limits integra tor accilracy at low frequency and causes drift of non-zero integrator voltages (in the HOLD mode). Both effects can be used as a convenient means of cap~itor leakage measurement in the computer:

1 Rdc~ar (A. 1.0)

where a is the exponential decay coefficient for a three-amplifier sine-generator. The frequency should be below 0.001 cps and the circuit should use equa 1 capacitors in the two integrators. See Figure A. 1. o.

In the HOLD mode E

R max dc~--

C

1

(dEl dt ) max (A. 1. 1)

Emax should be both plus and minus to cancel the effects of amplifier input grid cUITent and grid to ground current due to offset. Averaging the two initial decay rates will yield a valid Rdc only if the Emax is estab-lished (in I. C. mode) for a few minutes to avoid dielectric absorption effects. 7 Rdc is typically 10 12 to 10 13 ohms for Polystyrent 1J,tf capacitors.

Dissipation Factor

Dissipation factor~ D, is conventionally used to evaluate dielectric materials for capacitors. f3It is a steady-state sinusoidal voltage characteristic defined as

D = Energy loss radian

Peak energy stored

1 w RL (f) C (f)

(A. 1. 2)

where C (f) and RL (f) are frequency dependent. ,and para.llele;d to form the steadystate equl\,;alent CIrCUIt of the capacitor, Figure 3. A three-amplifier Sine-generator with only capacitor loss (no net phase error) yields a per radian amplitude decrement~ ~ = a/w, equal to the capacitor dissipation factor" D.

For Polystyrene capacitors C (f) varies only about 0.02% per decade frequency change and

RL varies inversely with frequency. For 1 J,tfd Polystyrene capacitors

(A. 1. 3)

between 0.01 < f < 100 cps, or D~1. 5 (10)-4. Figures 15 through 18 in the main report use the steady-state approximation of capacitors in computing capacitor error.

Figure A.1. 1 shows diSSipation factors for various materials at a lower frequency range than typically specified, i. e. computer frequencies.

Figure A. 1. 2 shows dissipation factor data for a typical Polystyrene 1J,tfd capacitor. A selected Teflon capacitor's data is also shown to indicate possible reduction of this important dynamic error.

Figure A. 1. 3 shows the normalized dissipation factor of a large, perfect capacitor shunted by a series resistor and capacitor. It is possible to approximate the practical capacitor with a series of such resistorcapacitor shunts to achieve an approximately constant dissipation factor, as shown.

Equivalent Circuit

Figure A. 1. 4 shows the application of the technique of Figure A. 1. 3 to the measured Polystyrene dissipation factor of Figure A. 1. 2. This is the basis of the fixed-parameter equivalent circuit of Figure 2 in the main report. The fixed-parameter circuit is somewhat complex. but can be used for transient studies.

Value Variation with Frequency

Figure A. 1. 5 shows the capacity change predicted from the equiva lent circuit as the solid line. Note that the experimental points confirm the equivalent circuit's validity from this viewpoint. Approximately 0.02% variation in 'value per decade frequency change is observed.

Dielectric Absorption

Limited transient evaluation of the equivalent circuit has been done to explain dielectric absorption or history effects. The analysis is somewhat difficult~ as the equivalent circuit is complex. It is sufficient for this paper to point out that it is easy to get 0.02% to 0.04% differences in answers us ing 1 J,tfd capacitors even at low computational frequencies (f < O. 1 cps) due to capacitor history. A typical example is this: Soak the capacitor at +100 V in a false I. C. mode; establish zero


volts I. C., for 10 to 30 discharge time con -stants, and then integrate a small step input in the COMPUTE mode. The "ramp" integrator output voltage will differ 20 to 40 mv if the false I. C. is changed to -100 volts. After the first 15 to 20 seconds the difference is independent of time. This false I. C. can easily be a voltage computed in a previous cycle and soaked in a long HOLD interval before the next compute cycle is started.

Correspondingly, it is very difficult to HOLD a voltage after a rapid transient is computed. The long time constant terms of the equivalent circuit of Figure 2 (in the main report) will remain charged to essentially the 1. C. voltage during the compute interval. They will later reduce the voltage O. 020/0 to O. 040/0 as the HOLD interval continues. The basic answer to this problem is a better dielectric material than Polystyrene for the integrator capacitors. Teflon capacitors offer promise of some improvement, but are not yet in general use.

2. Copper-Mandrel Potentiometer 9 Characteristics and Compensation

Figure A. 2.0 shows the circuit used to determine the equivalent circuit of the coefficient potentiometer. The oscilloscope was used only as a phase null device, with null achieved by addition of Cx or Cy for the particular potentiometer displacement.

The Type A Helipot@ potentiometers checked (10K, 20K, 30K, 50K and lOOK) were symmetrical, i. e. Co equaled Cv which allows this simple computation:

'Y (C + C ) ... (1 - 'Y) C C = C = s x Y (A 2. 0)

o 1 1-2'Y

where 'Y is pot displacement, Cs is oscilloscope input capacitance, and either Cx or Cy is zero at any given displacement. For other manufacturer's potentiometers, construction details may cause a slight difference between Co and C 1. This difference is not important since Co and C 1 values can be similarly computed. The curves of this report can be used by combining any difference between Co and C 1 with the load capacity, Ceo

Co turns out to be invariant for all values of displacement, 0.05 < 'Y < O. 95. This results in the very simple equivalent circuit of Figure 4 and the normalized phase error vs. displacement of Figure 5.

P0tentiometer capacitive loads generally are limited to 1 ~ k = C e Co ~ 3 in the computer. From Figure 5, the normalized phaseshift, <b / w R Co, varies between +1. 0 and -0. 33 for k = 1, between +1. 0 and -0.8 for k = 3. The resulting phase error at 100 cps for 30K and 50K potentiometers is:

<b <b Rp k=Ce/Co <b/wRCo (Radians) (Degrees)

30K 1.0 +1. 0 +0.0039 +0.22

30K 1.0 -0.33 -0.0013 -0.075

30K 3.0 +1. 0 +0.0039 +0.22

30K 3.0 -0.8 -0.0031 -0.18

50K 1.0 +1 +0.0068 +0.39

50K 1.0 -0.33 -0.0023 -0.13

50K 3.0 +1 +0.0068 +0.39

50K 3.0 -0.8 -0.0054 -0.31

The largest positive phase error occurs at zero displacement. This particular displacement is of little interest in practice, but is approached with small potentiometer coefficients. Similarly, the largest negative phase error is restricted to displacements of 0.6< y<0.7., Therefore, Ittypical" potentiometer dynamic errors will depend on "typical" displacement values.

The amplitude error due to phaseshift is approximately equal to the phase error in radians, which means that the 30K potentiometer can cause up to 0.40/0 dynamic error at 100 cps. The capacitive load seldom will reach the k = C e Co = 3 value suggested here as an upper l1mit. If the typical value of k = 1 is used, and small pot displacements avoided, the Utypica 1" dynamic error of 30K potentiometers is O. 10/0 to O. 150/0 at 100 cps: 50K potentiometers,is O. 170/0 to O. 250/0 at 100 cps.

In critical simulations it may be essential to eliminate potentiometer dynamic error. Various means of compensating for potentiometer phase error have been suggested. Most are suitable for canceling only potentiometer error, but not capacitively loaded potentiometer error. 10 One technique, that of placing small capacitors from a few distributed taps to either pot input or ground, readily allows extension to include arbitrary capacitive loads. 11 A few examples of this technique are given to show possible potentiometer phase error reduction. The ana lysis is not included here. 9 These curves should be compa red with Figure 5.

Figure A. 2.1 - Normalized phase error, <b(w R Co vs. displacement 'Y; one tap a 'Y = O. o. Tap-capacitor value is

325 8.2


326

8.2

equal to the load capacitor.

Figure A. 2. 2 - c/J 1 w R C vs. 'Y; two taps at 'Y = 113 and 'Y = 293.

Figure A. 2.3 - c/J/w R Co vs. 'Y; three taps at 'Y =: 1/4~ 'Y 2:: 1/ 2~ and 'Y = 3/4.

Figure A. 2. 4 - Shows an experimentally determined circuit for a ten-tap capacitively compensated pot with 940 pf capacitive load.

Figure a. 2.5 - Shows the square wave response of the ten-tap pot compared with an uncompensated pot.

Figure A. 2. 6 - Shows the measured c/JI wR Co of the ten-tap pot compared with the uncompensated pot~ both potentiometers with 940 pf capacitive load.

Figure A. 2.7 - c/JI w R Co vs. 'Y; two taps at 'Y = 0.1 and 'Y::: 0.7. Note that the non-uniform tap spacing results in less error than the uniform tap spacing qf Figure A. 2.2. For 0.05 <'Y< 1. 0 and k = 4. 5~ the maximum c/JI w R Co is 0.24. This compares very favorably with the O. 18 maximum value of the ten-tap pot as shown in Figure A. 2.6.

Restriction of c/JI w R Co to a maximum va lue of 0.2 for k = 3 would result in a worst case dynamic error of 0.08% at 100 cps for the 30K potentiometer. This is a factor of 5 improvement over the uncompensated 30K potentiometer. A few such two-tap potentiometers are recommended for even small computers.

3. Optimized-System Amplifier Frequency Characteristics

It is felt that some readers might be interested in seeing the advantages of capacitive compensation of 2::- amplifier feedback and input resistors through Bode plots rather than the root-locus of the text. Such data has been included for the Model 1048B ® Operational Amplifier as ubed in the EASE 1100 Series ana log computer. Since this gives a somewhat detailed view of the 1048B characteristics from a frequency basis l an equally detailed s-plane plot of the amplifier system open-loop characteristics has been included for those more interested in the root-locus approach.

Figure A. 3. 0 is an s-plane plot of 1048B and 1148 operational amplifiers - 1100 system open-loop poles and zeros.

Figures A. 3. 1 through A. 3.4 show the theoretical and experimental frequency characteristics of the 1048B for various capacitive loads.

This analysis includes all three terms of Equation 19 for the transfer charac-teristics. The ~ _ Y

f J term has

l G(S)Y~ the interesting effect of introducing a right half-plane zero.

Note that the 3-~amplifier loop gain margin can be predicted by tripling the db margin at 60 degrees phaseshift.

Figures A. 3.5 and A. 3. 6 are a replot of the gain and phase for the same capacitive load data. Note that it takes a 0.01 capacitive load to achieve complex closed loop roots that are dominant.

Figures A. 3. 7 and A. 3. 8 show the bandwidth of a gain of 10 summer. Note that the stability margin remains excellent and the bandwidth is only slightly reduced.

Figures A. 3. 9 and A. 3. 10 show the effect of increased summing junction capacitance.

Figure A. 3. 11 shows that wider bandwidth can be achieved with larger than 43 pf capacity compensation. The data is for 100 pf compensa tion.

For a general purpose machine .. 100 pf compensation is not recommended since 1) the stability margin is considerably reduced for the amplifier and 2) 1000 pf capacitors would be required for X 10 input resistors. This would cause large coefficient pot phase errors.

Figure A. 3. 12 is included for 'a rough com-pa rison of bandwidth when the system used uncompensated input resistors and a 10 pf feedback shunting capacitor. This characteristic is typical of many existing computers. For many standard problems it is adequate. However l the stability margin is much less" as typified by 3-2:: amplifier oscillation at a loop gain of 1 8& and 2:: amplifier oscillation with O. 015 ~f capacitive load. Further" the phase error without a 10 pf input capacitor is O. 360 at 100 cps or 0.63% dynamic error.


References

1. Korn, G. A. and Korn~ T. M. ~ "Electronic Ana log Computers"~ 2nd Edition~ 1956. M~Graw-Hill.

2. MacNeed, A. B., "Some Limitations on Accuracy of Electronic Differential-equation Solvers", Proc. IRE 40:303, 1950.

3. Marsocci, V. A., "An Error Analysis of Electronic Analog Computers", Trans. IRE-PGEC, December, 1956. --

4. Dow, P. C. ~ tlAn Analysis of Cer.tain Errors in Electronic Differential Analyzers, 1-Bandwidth Limitations, II-Capacitors Dielectric Absorption", Trans. IRE-PGEC, December, 1957. --- -- ---

5. Miura, T. and Nagata, M., "Theoretical Considerations of Computing Errors of a Slow Type Electronic Analog Computer", Trans. IRE-PGEC, December, 1958.

6. Single, C. H. ~ "Precision Components For Analog Computers", I. S. A. Convention Record, Paper #56-2~eptember, 1956.

7. Brussolo, J. and Single, C. H • .J "Transient Analysis of Capacitor Equivalent Circuit"" BECKMAN/Berkeley Engineering Report CRD59-5.

" « 8. Meilander, W. C. and Hellman" B. H... A Technique for Absolute Measurement of Analog Computer CapaCitors", Goodyear Aircraft Technical Publication GER-9075, November~ 1958.

9. Single, C. H. and Brussolo, J., "CopperMandrel Potentiometer Dynamic Error & Compensation", July, 1960 - Available from BECKMAN/Berkeley Division" Richmond" California.

10. Logan, B. C., "AC Performance and Phase Compensation of Copper-Mandrel Potentiometers", Technical Paper 497 - Available from BECKMAN! Hehpot Division, Fulle rton" Ca lifornia.

11. Schneider, F., Hiroaka and Gauldin, "Measurement and Correction of PhaseShift in Copper-Mandrel Precision Potentiometers lt

, Technical Paper 552 - Available from BECKMAN! Hehpot Division, Fullerton, California.

12. Evans, W. R." "Control System Dynamics"" McGraw-Hill, 1954

c

Resistor Equivalent Circuit

FIGURE 1

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1IIII1! Fixed-Parameter Capacitor

Equiva lent Circuit

FIGURE 2

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Frequency Dependent Capacitor Equivalent Circuit

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Step-Response of Compensated

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Effect of Summing Junction and Load Capacity on Step· Response

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FIGURE 12

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n-AMPLIFIER LOOPS AT UNITY GAIN

n-Amplifier Loop with Unity Inverters

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Number of Amplifiers

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339 8.2


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