ge/soi finfet cmos process integration platform · 2018. 12. 11. · • ge/soi finfet cmos (zero...

Ge/SOI FinFET CMOS Process Integration Platform鍺鰭式場效電晶體與互補式金氧半導體製程整合平台

Baseline Guideline

CONFIDENTIAL 1

Disclaimer

• NDL shall not be liable for technical or editorial errors oromissions contained herein; nor for incidental orconsequential damages resulting from the furnishing,performance, or use of this material. The information in thismanual is subject to change without any prior notice for thepurposes of improving the performance and functionality ofits products.

• No one is allowed to copy or distribute the whole or a part ofthis document without prior written permission of NDL.

• NDL here means National Nano device Laboratories.

CONFIDENTIAL 2

Purpose

• This document is intended to help users who want to applyNDL Ge/SOI FinFET CMOS process to do fabrication.

• Please be notified that users should follow the processguideline in this document to do fabrication without anyviolation.

Contact information :

研究員：李耀仁博士 (#7793) [email protected]

助理研究員：葉沐詩博士 (#7620) [email protected]

CONFIDENTIAL 3

ContentsDisclaimer …..………………………………………………………………………………………………...….……………. 02

Purpose …..………………………………………………………………………………………………...….……………….. 03

Revision History …………………………………………………………………………………………..….……............ 05

Ge/SOI FinFET CMOS Process Flow Cost Estimate (Zero Mark→Active Layer_for 2 pcs) ……. 06

Ge/SOI FinFET CMOS Process Flow Chart (Zero Mark→Active Layer) …............................... 09

Run card of Ge/SOI FinFET CMOS Process Flow (Zero Mark→Active Layer_for 2 pcs) …….... 10

Ge/SOI FinFET CMOS Mask Layout ……………………………………………………………………................ 13

Appendix A - Equipment layout …….…………………………............................................................... 18

Appendix B - Zero mark→Metal layer process flow (Full version)………..………........................... 19

Appendix C - Gate layer→Metal layer process flow (6” Leica e-beam_for 2 pcs) ………............. 25

Appendix D - Gate layer→Metal layer process flow (ELS7500 _for 2 pcs) …………………............. 31

Appendix E - Assistance lists ……………………………………………………….…………………........................ 37

Cost estimates (Appendix B、C、D)…………….………………….……….……….……….…………................ 38

Electrical Measurements ……………………………………………………….…………….................................. 47

CONFIDENTIAL 4

Revision History

• 2018/02 Preliminary release.

CONFIDENTIAL 5

• Ge/SOI FinFET CMOS (Zero Mark→Active Layer process flow_for 2 pcs)

• Part 1. 8” Ge/SOI FinFET CMOS process (8” SOI可以提供的破片數量：36 pcs)

Laser mark

Zero mark

Epi Ge film

Active layer pattering

Active layer etching

Die saw (外送製程)

Pick up (取貨)

總共2道光罩、33道步驟，製程時間約2.5-3週。

CONFIDENTIAL 6

• Part 1. 8” Ge FinFET CMOS Process cost estimate

$26375/36 pcs= $733/pc

• Part 2. Die saw cost estimate

$3150/36 pcs= $96/pc

• Part 3. 8” SOI Wafer cost estimate (current price)

$21000/36 pcs= $584/pc

• 詳細經費預估說明，請參考p.7~p.8

Description of Service (s)

Unit QuantityUnit Price

(NTD)Total Amount

(NTD)

Part 1. 8” Ge FinFET CMOS Process (NDL)

pc 2 $733 $1,466

Part 2. 8” 晶圓切割 pc 2 $96 192

Part 3. 8” SOI wafer(700A/1450A)

時價(current price)pc 2 $584 $1,168

(Part 1.+2.+3.) Total Amount

$2,826/2 pcs

Ge/SOI FinFET CMOS Process Flow Cost Estimate

• Ge/SOI FinFET CMOS：zero mark→active layer• Part 1. 8” Ge/SOI FinFET CMOS process cost estimate

連續製程經費預估：應付費用(B+C) 26375.00 (10%)

第1頁第2頁

CONFIDENTIAL 7



(NTD)Total Amount

(NTD)

8” Si 晶圓切割 pc 1 3,000 3,000

Subtotal 3,000

Sales Tax (5%) 150

Total (Include Tax) 3,150



(NTD)Total Amount

(NTD)

8” SOI wafer(700A/1450A)

pc 1 21,000 21,000

Subtotal 20000

Sales Tax (5%) 1000

Total (Include Tax) 21000

第3頁

CONFIDENTIAL 8

• Ge/SOI FinFET CMOS：zero mark→active layer• Part 1. 8” Ge/SOI FinFET CMOS process cost estimate

連續製程經費預估：應付費用(B+C) 26375.00 (10%)

• 8” SOI可以提供的破片數量：36 pcs

• Part 1. 8” Ge FinFET CMOS Processzero mark→active layer cost estimate：$26375/36 pcs= $733/pc

• Part 2.外送製程經費預估切片(Die saw)Die saw cost estimate：$3150/36 pcs= $96/pc

• Part 3.時價(current price)8” SOI wafer經費估價，隨美金匯率報價異動。8” SOI Wafer cost estimate：$21000/36 pcs= $584/pc

Wafer clean Thin down Si 200 A~300 A & Hard mask=2000 A dep.

& Zero mark patterning

PR

E-Beam

P-type SOI

HM

Zero mark

Zero mark etching Remove PR & Hard mask

HM

Remove PR

PR

Epi Ge film=800 A-1000 A & Hard mask=100 A-200 A dep.

& Active layer patterning

PRHMGe

PR

E-Beam


PRHMGe

HMPR

SiBOX

Si-subBOX

Si-sub

BOX

Si-sub

BOX

Si-sub

BOX

Si-sub

Active layer

Die saw

• Ge FinFET CMOS

• zero mark→active layer process flow Chart

紅字說明為Ge FinFET CMOS元件之關鍵製程，下run前請與工程師討論。

12 mm

12 mm

Runcard step.1-step.8


Runcard step.17-step.20Runcard step.14-step.16

Runcard step.21-step.26Runcard step.27-step.29Runcard step.30Runcard step.31

Etch

Etch

SiSi

PRHM

PRHM

BOXSi-sub

Si

PRHM

PRHM Si

SiGe

HM

SiGe

PRHMGe

BOX

Si-sub

SiGe

~700A~300A

CONFIDENTIAL 9

Ge/SOI FinFET CMOS Process Flow Chart

Ge/SOI FinFET CMOS Process Flow• 對外服務系統→輸入帳密→製程與設備服務→設備委託操作申請→申請連續製程→提出申請

• 選擇奈米元件廠→CF-series-營運組連續製程委託申請→下一步。

• (僅用文字說明)進入”設備委託操作申請-編輯”，請選擇”一般連續製程”，輸入其他相關資料設定，即可建立一個新申請單編號→再到MES 系統CiMES)選取範本。

Step.1

Step.2

Step.3

Step.4Step.5

Step.6

Step.7

10CONFIDENTIAL

CONFIDENTIAL 11

Step.5

Step.6

Step.7

Step.2

Step.3

Step.4

Step.1

Ge/SOI FinFET CMOS Process Flow

Step.8 Step.9

• 對外服務系統申請連續製程→建立一個新申請單編號→再到MES 系統(CiMES) 。

• MES 系統(CiMES)：輸入帳密，登入後→委託單維護→選擇新申請單編號(初稿)→製程設定中，

製程範本選：“Ge_CMOS_On_SOI_wafer_(zeromark_to_active layer)” →複製範本流程→複製流程→完成。

Step.10

完成

初稿

如有特殊製程條件需求，請自行在每道製程步驟備註說明。

• Ge FinFET CMOS (Zero Mark→Active Layer process flow_for 2 pcs)

• Run card of zero mark→active layer→Die saw

第2頁

12

PESiO2=100~200A

Ge/SOI FinFET CMOS Process Flow

Pick up (取貨) Finish(不包含量測電性)

Epi Ge film=800-1000A

第1頁

CONFIDENTIAL

• Brief Lists of Ge/SOI FinFET CMOS recipesGe/SOI CMOS FinFET Mask (zero mark→active layer)

Lithography：8” e-beam (L19) 蔣曉白 (#7579)

檔名：ndl_msyeh_cmosv1

1) zero mark (Open mark正光阻)

• ndl_msyeh_cmosv1_L0_11x11

• 預估曝光時間2.0hr/pcs

– Cell 0

– Pad layer : 0

2) active (CAN負光阻)

• ndl_msyeh_cmosv1_act_CN01_11x11

• 預估曝光時間3.5hr/pcs

– Cell 0

– Pad layer : 1 Dose L1=116

– Channel layer : 2 Dose L2=64

CONFIDENTIAL 13

Ge/SOI FinFET CMOS Mask (8”e-beam)

12 mm

12 mm

6” Leica e-beam zero mark

ELS7500 zero mark

Die saw mark

8” e-beam zero mark

Die saw mark

CONFIDENTIAL 14

Ge/SOI FinFET CMOS Mask Layout

NFET

PFET

CONFIDENTIAL 15

CMOS area

Ge/SOI FinFET CMOS Mask Layout CMOS

width=20 nm, gate length=100 nm

CONFIDENTIAL 16

PFET

Ge/SOI FinFET CMOS Mask Layout PFET area


Ge/SOI FinFET CMOS Mask Layout

NFET

CONFIDENTIAL 17

NFET area


Appendix - A• NDL fab Equipment Layout

CONFIDENTIAL 18

H-k gate oxide deposition

TiN Metal gate deposition

Gate pattering (ELS7500)

Gate layer etching

1st Imp. pattering (ELS7500)

1st Imp. B doping

2nd Imp. pattering (ELS7500)

2nd Imp. P doping

MWA


總共7道光罩、72道步驟，製程時間約 2.5-3個月。

• Ge/SOI FinFET CMOS flow (Full version)

• Zero mark→metal layer process flow (Full version)

Passivation (TEOX=2000A)

Contact window patterning (ELS7500)

Contact window etching

Al-Cu deposition

Metal 1 patterning (ELS7500)

Metal 1 etching

Pick up (取貨)

CONFIDENTIAL 19

Laser mark

Zero mark

Epi Ge film

Active layer pattering


Die saw (外送製程)

Appendix - B

說明：額外提供完整版本，需自行操作 8” Ge FinFET CMOS Process (full version)cost estimate

自備 8”SOI wafer (不含外送切割服務)

實驗流程：8“整片zero mark到active layer+破片(2pcs) gate layer到metal layer=總計$42368 (10%)

CONFIDENTIAL 20

Wafer clean Thin down Si 200 A~300 A & Hard mask=2000 A dep.

& Zero mark patterning

PRP-type SOI

HM

Active layer

Zero mark etching Remove PR &Hard mask

HMSi

BOX

Si-subBOX

Si-subBOXSi-sub

Runcard step.1-step.8Runcard step.17-step.20Runcard step.14-step.16

SiSi

PRHM

PRHM

BOX

Si-sub

PRHM

PRHM

Si~700A

~300A

VINVOUT

Ge

Fin

BOX

Si

VDD

VSS

HK/MG

Gate Stack

Passivation

&

Contact Holes

Imp.: B doping

Imp.: 31P doping

1st Imp.

(p-FinFET)

Ge CMOS

2nd Imp.

(n-FinFET)

Metallization

Zero mark

E-BeamEtch

Active layer etching Gate ox. & metal gate dep. & Gate layer patterning

Runcard step.27-step.31 Runcard step.32-step.41 Runcard step.42-step.47

Runcard step.63-step.70 Runcard step.48-step.53



Epi Ge film =800 A~1000 A& Hard mask=100 A-200 A dep.

& Active layer patterning

PRHMGe

PR

E-Beam

BOXSi-sub

SiGe

HM


Ge FinFET CMOS

Gate layer

Appendix - B• Ge/SOI FinFET CMOS process flow (Full version)

1st Imp. pattering& 1st Imp. (PFET): B doping

& Remove PR

2nd Imp. pattering& 2nd Imp. (NFET): 31P doping

& Remove PR

Si

CONFIDENTIAL 21

Appendix - B

Step.8Step.9



製程範本選：“Ge_CMOS_on_SOI_full_version_(zeromark_to_metal)” →複製範本流程→複製流程→完成。

Step.10

完成

初稿


2

2

第1頁第2頁

CONFIDENTIAL 22

PESiO2=100~200A


Epi Ge film=800-1000A

注意：此步驟開始為破片製程，每張Runcard最多只能下2片破片

請自行修改片數為2片

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

第3頁第4頁

CONFIDENTIAL 23


2

2

2

第5頁 • Zero mark→metal layer連續製程經費預估：

應付費用(B+C) 42368.00 (10%)

CONFIDENTIAL 24

詳細經費預估說明，請參考p.39~p.41

Appendix - B


• Ge/SOI FinFET CMOS process flow (Full version)

Appendix - C



Gate pattering (6” Leica e-beam)

Gate layer etching

1st Imp. pattering (6” Leica e-beam)

1st Imp. B doping

2nd Imp. pattering (6” Leica e-beam)

2nd Imp. P doping

MWA

• Ge/SOI FinFET CMOS gate layer →metal layer process flow

• 破片曝光選擇6” Leica e-beam_自動對準曝光功能，只能委託代工，不能自行操作。


Contact window patterning (6” Leica e-beam)


Al-Cu deposition

Metal 1 patterning (6” Leica e-beam)

Metal 1 etching

Pick up (取貨)

CONFIDENTIAL 25

說明：額外提供後續gate layer到metal layer 版本，此版本為選擇6” Leica e-beam_自動對準曝光

實驗流程：破片(2 pcs) gate layer到metal layer=總計$18466 /2 pcs (10%)


總共5道光罩、39道步驟，製程時間約 2-2.5個月。

Imp.: B doping

Gate ox. & metal gate dep.& Gate layer patterning

PR

HMPR



metal gate

PR

E-Beam

BOXSi-sub

Gate layer etching

PR

HMPR


PR

Etch

Remove PR

PR

HMPR

Ge

Runcard step.10

BOXSi-sub

metal gateHK/gate ox.

Gate layer1st Imp. Pattering& 1st Imp. (PFET)

2nd Imp. Pattering& 2nd Imp. (NFET)


& Remove PR


& Remove PR

CONFIDENTIAL 26

MWA&

I-V electrical measurements

Passivation&

Contact Holes

Metallization&


Contact

Runcard step.32-step.39 Runcard step.25-step.31 Runcard step.23-step.24 Runcard step.17-step.22


MWA

BOXSi

(n-FinFET)

Imp.: 31P doping

Si

VINVOUT

VDD

VSS

SiGeGe

BOXSi-sub

metal gate

SiGe

HK/gate ox.

SiGe

Ge FinFET CMOS

• Ge/SOI FinFET CMOS

• gate layer →metal layer process flow Chart (破片曝光選擇 6” Leica e-beam)

Appendix - C

HK/gate oxide

CONFIDENTIAL 27

Step.5

Step.6

Step.7

Step.1Step.2

Step.3

Step.4

Appendix - C

Step.8 Step.9



製程範本選：“Ge_CMOS_on_SOI_chip(6-E-beam_gate_to_metal)” →複製範本流程→複製流程→完成。

Step.10

完成

初稿


2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Appendix - C• Ge/SOI FinFET CMOS (每張Runcard最多破片數量2 pcs)

• Run card of gate layer →metal layer (破片曝光選擇6” Leica e-beam_自動對準曝光)

第1頁第2頁

CONFIDENTIAL 28



2

2

2

2

2

2

2

2

2

2

2

2

Appendix - C• Ge/SOI FinFET CMOS (每張Runcard最多破片數量2 pcs)

• Run card of gate layer →metal layer (破片曝光選擇6” Leica e-beam_自動對準曝光)

第3頁

CONFIDENTIAL 29

破片2 pcs 詳細經費預估說明，請參考p.42~p.43


• gate layer→metal layer連續製程經費預估：

應付費用(B+C) 18466.00 (10%)

Appendix - C• Brief Lists of Ge/SOI FinFET CMOS recipesGe/SOI CMOS FinFET Mask (gate layer→metal layer)

Lithography：6” Leica e-beam (L02W) 鄭旭君 (#7644)

檔名： ndl_pw12_msyeh_cmosv1

1) gate layer (NEB負光阻)

• ndl_pw12_msyeh_cmosv1_gate

• 預估曝光時間0.5hr/pc

– Cell 0

– Pad layer : 4

– gate layer : 3

2) PFET imp. layer (P015正光阻)

• ndl_ pw12_msyeh_cmosv1_PFET


– Cell 0

– Pad layer : 5

3) NFET imp. layer (P015正光阻)

• ndl_ pw12_msyeh_cmosv1_NFET


– Cell 0

– Pad layer : 6

4) contact window (P015正光阻)

• ndl_pw12_msyeh_cmosv1_CW


– Cell 0

– Pad layer : 7

5) metal layer (NEB負光阻)

• ndl_ pw12_msyeh_cmosv1_metal


– Cell 0

– Pad layer : 8

CONFIDENTIAL 30

Appendix - D



Gate pattering (ELS7500)

Gate layer etching

1st Imp. pattering (ELS7500)

1st Imp. B doping

2nd Imp. pattering (ELS7500)

2nd Imp. P doping

MWA


Contact window patterning (ELS7500)


Al-Cu deposition

Metal 1 patterning (ELS7500)

Metal 1 etching

Pick up (取貨)

CONFIDENTIAL 31

說明：額外提供後續gate layer到metal layer 版本，此版本為選擇 ELS7500_需要手動對準曝光

實驗流程：破片(2 pcs) gate layer到metal layer=總計$18196/2 pcs (10%)


總共5道光罩、39道步驟，製程時間約 2-2.5個月。

• Ge/SOI FinFET CMOS gate layer →metal layer process flow

• 破片曝光選擇ELS7500_需要手動對準曝光，無自動曝光功能，可委託代工或自行操作。

Imp.: B doping

Gate ox. & metal gate dep.& Gate layer patterning

PR

HMPR



metal gate

PR

E-Beam

BOXSi-sub

Gate layer etching

PR

HMPR


PR

Etch

Remove PR

PR

HMPR

Ge

Runcard step.10

BOXSi-sub

metal gateHK/gate ox.

Gate layer1st Imp. Pattering& 1st Imp. (PFET)

2nd Imp. Pattering& 2nd Imp. (NFET)


& Remove PR


& Remove PR

CONFIDENTIAL 32

MWA&


Passivation&

Contact Holes

Metallization&


Contact

Runcard step.32-step.39 Runcard step.25-step.31 Runcard step.23-step.24 Runcard step.17-step.22


MWA

BOXSi

(n-FinFET)

Imp.: 31P doping

Si

VINVOUT

VDD

VSS

SiGeGe

BOXSi-sub

metal gate

SiGe

HK/gate ox.HK/gate oxide

SiGe

Ge FinFET CMOS

• Ge/SOI FinFET CMOS

• gate layer →metal layer process flow Chart (破片曝光選擇 ELS7500)

Appendix - D

CONFIDENTIAL 33



製程範本選：“Ge_CMOS_on_SOI_chip(ELS7500_gate_to_metal)” →複製範本流程→複製流程→完成。

Appendix - D

Step.5

Step.6

Step.7

Step.2

Step.3

Step.4

Step.1

Step.8 Step.9

Step.10

完成

初稿


2

2

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2

2

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2

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Appendix - D• Ge/SOI FinFET CMOS (每張Runcard最多破片數量2 pcs)

• Run card of gate layer →metal layer (破片曝光選擇ELS7500_需要手動對準曝光)

第1頁第2頁

CONFIDENTIAL 34



2

2

2

2

2

2

2

2

2

2

2

Appendix - D• Ge/SOI FinFET CMOS (每張Runcard最多破片數量2 pcs)

• Run card of gate layer →metal layer (破片曝光選擇ELS7500_需要手動對準曝光)

第3頁

CONFIDENTIAL 35

破片2 pcs 詳細經費預估說明，請參考p.44~p.45


• gate layer→metal layer連續製程經費預估：

應付費用(B+C) 18196.00 (10%)

Appendix - D• Brief Lists of Ge/SOI FinFET CMOS recipesGe/SOI CMOS FinFET Mask (gate layer→metal layer)

Lithography：ELS7500 (L12) 陳虹君 (#7575)

檔名： ndl_pw12_msyeh_cmosv1

1) gate layer (NEB負光阻)

• ndl_pw12_msyeh_cmosv1_gate


– Cell 0

– Pad layer : 4

– gate layer : 3

2) PFET imp. layer (P015正光阻)

• ndl_ pw12_msyeh_cmosv1_PFET


– Cell 0

– Pad layer : 5

3) NFET imp. layer (P015正光阻)

• ndl_ pw12_msyeh_cmosv1_NFET


– Cell 0

– Pad layer : 6

4) contact window (P015正光阻)

• ndl_pw12_msyeh_cmosv1_CW


– Cell 0

– Pad layer : 7

5) metal layer (NEB負光阻)

• ndl_ pw12_msyeh_cmosv1_metal


– Cell 0

– Pad layer : 8

CONFIDENTIAL 36

Appendix - E• Process Engineers for Assistance

1. Lithography 設備名稱 (機台編號) 工程師分機 E-mail

8” e-beam (L19) 蔣曉白 (#7579) [email protected]

6” Leica e-beam (L02W) 鄭旭君 (#7644) [email protected]

ELS7500 (L12) 陳虹君 (#7575) [email protected]

設備名稱 (機台編號) 工程師分機 E-mail

前段蝕刻機台：Lam2300 (E10)8吋前段多晶矽與介電層蝕刻機

薛富國 (#7557) [email protected]

後段蝕刻機台：Lam2300 (E11)8吋後段金屬與金屬層間引洞蝕刻機

許倬綸 (#7651) [email protected]

設備名稱 (機台編號) 研究員分機 E-mail

ASM四族磊晶機台(RDT 005)

羅廣禮博士 (#7660) [email protected]

研究員李耀仁博士 (#7793) [email protected]

助理研究員葉沐詩博士 (#7620) [email protected]

2. Etching

3. Epi Ge Thin Film

5. Integration

4. Gate Oxide 設備名稱 (機台編號) 工程師分機 E-mail

ALD原子層沉積系統(RDT 001)

侯福居博士 (#7636) [email protected]

CONFIDENTIAL 37

各步驟實驗經費估價cost estimates

CONFIDENTIAL 38

CONFIDENTIAL

CONFIDENTIAL 39

學界自行操作：以訂價*10%收費。學界（含中研院）委託代工：技術服務費以學界訂價* 10%收費，材料費100%收費。業界自行操作：不開放。業界委託代工：以業界訂價收費。

價格如有異動請參考網址：http://www.ndl.org.tw/tech/equipment

北區機台收費標準-列舉8台重要機台

CONFIDENTIAL 40

• Ge/SOI FinFET CMOS：zero mark→metal layer

• 連續製程經費預估：應付費用(B+C) 42368.00 (10%)

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CONFIDENTIAL 41



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CONFIDENTIAL 42



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(破片曝光可自行選擇 6” Leica e-beam_自動對準曝光)(破片曝光可自行選擇 ELS7500_需要手動對準曝光)

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• Ge/SOI FinFET CMOS：gate layer→metal layer (6” Leica e-beam)


• (每張Runcard最多破片數量2 pcs)

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CONFIDENTIAL 43

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CONFIDENTIAL 44

(破片曝光選擇 6” Leica e-beam_自動對準曝光)

• Ge/SOI FinFET CMOS：gate layer→metal layer (6” Leica e-beam)



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• Ge/SOI FinFET CMOS：gate layer→metal layer (ELS7500)



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CONFIDENTIAL 46

(破片曝光可選擇 ELS7500_需要手動對準曝光)

• Ge/SOI FinFET CMOS：gate layer→metal layer (ELS7500)



CONFIDENTIAL 47

NFET：Width=20 nm, Gate length=100 nmS/D imp : 31P, 1×15 cm-2, 15 KeVAnneal : MWA, 2.75 p, 100 sec

Electrical Measurements

pFETVTH

(V)

SS(mV/dec.)

DIBL(mV/V)

Ion/Ioff

Ratio (A/A)

VD=0.05V -0.2 88.9 53.6 5.4x106

VD=0.1V -0.19 88.0 49.6 1.9x106

VD=0.5V -0.16 95.7 53.6 2.7x105

VD=1.0V -0.14 145.1 49.6 9.7x103

nFETVTH

(V)

SS(mV/dec.)

DIBL(mV/V)

Ion/Ioff

Ratio (A/A)

VD=0.05V 0.26 69.7 29.6 2.0x105

VD=0.1V 0.25 71.2 70.7 2.7x105

VD=0.5V 0.23 92.3 29.6 2.9x104

VD=1.0V 0.19 139.1 70.7 1.7x103

PFET：Width=20 nm, Gate length=100 nmS/D imp : B, 1×15 cm-2, 10 KeVAnneal : MWA, 2.75 p, 100 sec

VD=-1.0V

VD=-0.5V

VD=-0.1V

VD=-0.05V

-1.5 -1.0 -0.5 0.0 0.510

-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

Full Ge IM pFET

LG=100nm

W=20nm

Gate Voltage (V)

Dra

in C

urr

ent

(A

/m

)

SS(-0.05V)

=88.9mV/dec.

VTH=-0.2V

Ion/Ioff ~106

VD=1.0V

VD=0.5V

VD=0.1V

VD=0.05V

-0.5 0.0 0.5 1.0 1.510

-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

Full Ge IM nFET

LG=100nm

W=20nm

Gate Voltage (V)D

rain

Cu

rren

t (

A/

m)

SS(0.05V)

=69.7mV/dec.

VTH=0.25V

Ion/Ioff ~105

ge/soi finfet cmos process integration platform · 2018. 12. 11. · • ge/soi finfet cmos (zero...

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