# inrush current analysis for switching large shunt...

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Abstract This paper presents the simulation and investigation of switching large shunt capacitor bank in a 230kV Thailand substation system. Simulation is performed using PSCAD/EMTDC. The inrush current is generated by energizing of the 4x72 Mvar, 230 kV shunt capacitor banks. The purpose is to observe the inrush current to ensure safe and successful operations of the shunt capacitor banks. In addition, the effects of parameters such as sizing of current limiting reactor (CLR), pre-insert resistor (PIR) and 6% detuning reactor are investigated. The results of simulations are shown that the 6% detuning reactor can reduce inrush current more than other methods.

I. INTRODUCTION Capacitor banks are normally used in low voltage (LV), medium voltage (MV) and high voltage (HV) networks to generate the reactive power to industries and utility. High voltage shunt capacitor banks for any power rating or voltage can be designed by series and parallel connection of single phase units. However, the energization of capacitor bank which is the capacitive load may lead to the high inrush current and transient overvoltage oscillation at the capacitor bank terminal. Capacitor bank energizing transients are becoming increasingly more important with the growing number of capacitor bank installations in power systems. This is because capacitor bank switching is one of the most frequent utility operations, potentially occurring multiple times per day and hundreds of time per year throughout the system, depending on the need for system voltage/var support from the banks. There are a number of important concerns when capacitor banks are applied at the transmission system voltage level. Transient related currents and voltages appearing on a power system associated with utility capacitor bank installations including the voltage transients at the capacitor bank substation and neighboring substations, power quality impact on sensitive customer loads due to variations in voltage when energizing capacitor banks and capacitor bank energization inrush currents. Moreover, the inrush current can cause the protective relay mal-operation. The application of shunt capacitor banks for compensation purposes is increasing; it is common that more than one capacitor bank is connected to the same bus. The capacitor bank is energized from a bus that does not have other capacitor banks energized. This situation is called isolated capacitor bank switching. On the other hand, the capacitor

bank is energized from a bus that has other capacitor banks energized. This situation is called back-to-back capacitor bank switching [1]. In several research papers [2-4], the inrush current was analyzed to investigate the behavior of high inrush current and oscillation overvoltage by comparing with the method of mitigation of capacitor bank switching such as applying pre-insert resistor, series reactor and synchronous switching controlled only, and simulated the shunt capacitor bank in LV & MV distribution system. Therefore, this paper presents the analysis of inrush current when switching shunt capacitor bank in HV substation is done to energize reactive power to the transmission system. The system under consideration is the typical configuration of capacitor bank switching in a 230 kV substation in Thailand. The typical sizes of each capacitor bank in a 230 kV system are 4-steps and size of each step is 72 Mvar, and are connected in parallel to the network systems. The inrush current and oscillation overvoltage are simulated using PSCAD/EMTDC, and their obtained waveforms are analyzed for several cases. A technique to reduce transient overvoltage and inrush current is examined with 3 system configurations such as base case (no-transient limiting), current limiting reactor, and detuning reactor (6% reactor). The result of inrush current and oscillation frequency will be compared between PSCAD/EMTDC and calculation method in accordance with IEC standard 60871-1:2005 and IEEE standard C37.012:2005 respectively [5, 6].

II. CAPACITOR BANK SWITCHING THEORY In a 230 kV substation, the shunt capacitor bank is connected in parallel on the network. The optimum connection depends on the best utilization of the available voltage ratings of capacitor units, fusing, and protective relaying. Normally, all substation banks are wye connected. Distribution capacitor banks, however, may be wye or delta connected. In this paper, these banks use an H-configuration on each phase with a current transformer in the connecting branch to detect the unbalance current [6]. As long as all the capacitors are normal, no current will flow through the current transformer. If a capacitor fuse operates, some current will flow through the current transformer. This bridge connection can be very sensitive. This arrangement is used on large banks with many capacitor units in parallel. The capacitor bank configuration is illustrated in Fig. 1.

Inrush Current Analysis for Switching Large Shunt Capacitor Bank in a 230 kV

Substation System T. Patcharoen1, A. Ngaopitakkul1, C. Pothisarn1,

1Department of Electrical Engineering, Faculty of Engineering, King Mongkuts Institute of Technology Ladkrabang, Bangkok 10520 Thailand

E-mail: [email protected]

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2013 International Conference on Electrical Machines and Systems, Oct. 26-29, 2013, Busan, Korea

978-1-4799-1447-0/13/$31.00 2013 IEEE

Fig. 1. The shunt capacitor bank connected in H-configuration.

In order to use the capacitors banks for compensation purpose is increasing the reactive power. It is common that more than one capacitor bank is connected to the same bus. Two different situations may occur as below.

A. Isolated capacitor bank From Fig. 2, when the switch is closed, a high frequency, high magnitude current flows into the capacitor, attempting to equalize the system voltage and the capacitor voltage. If the switch is closed at a voltage peak, the voltage on the capacitor attempts to immediately increase from the zero-voltage, de-energized condition to the peak voltage. The circuit consists then of the source inductance in series with the capacitor bank can be disregarded because . In this case, the peak of the inrush current peak and inrush current frequency are limited by the source impedance [6].

Fig. 2. System diagram and equivalent circuit for analyzing the transient inrush current generated by an isolated capacitor switching operation.

A shunt capacitor bank is considered isolated when the inrush current on energization is limited by the inductance of the source and the capacitance of the bank being energized. A capacitor bank is also considered isolated if the maximum rate of change, with respect to time, of transient inrush current on energizing an uncharged bank does not exceed the maximum rate of change of the symmetrical short-circuit current at the voltage at which the current is applied. Considering a discharged capacitor bank the current is given by equation;

2 max

scst

i Idd =

(1) 1max 2 IIi sci = (2)

1

IIff scsi =

(3) where,

= The power frequency (Hz) = The inrush current frequency (Hz) = The short circuit current of the source (A, rms)

The current through capacitor bank no. 1 (A, rms) i Maximum rate of change of inrush current (A/s)

s =The angular system frequency (rad/s)

B. Back-to-Back capacitor bank Back-to-back switching is shown in Fig. 3. When a capacitor bank is energized in close proximity to a previously energized capacitor bank. A high frequency inrush current flows when the capacitor bank is energized. However, the limiting inductance is the inductance between the capacitor banks rather than the system inductance [6].

Fig. 3. System diagram and equivalent circuit for analyzing the transient inrush current generated by back-to-back capacitor switching operation.

In Fig. 3, the capacitor bank 1, 2 and 3 are connected to the busbar and the capacitor bank 4 is to be connected, the inrush current associated with the charging of capacitor bank 4 is supplied by capacitor bank 1 to 3. (i.e., back-to-back switching). In this case, the inrush current magnitude and frequency can be calculated as follows in Equation (4) and Equation (5).

( )2121r

peak U35001

IILfIIi

eqsi +

(4)

( )21

21 .59 IIL

IIUffeq

rsi

+= (5)

where, = The inrush current peak (A, rms) , The capacitor bank currents (A, rms) The equivalent inductance (H)

The rated voltage (kV, rms)

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Typical amplitude of the inrush current for back-to-back energization is several kA with frequencies of 2 kHz to 5 kHz. The magnitude and frequency of this inrush current is, therefore, much higher than that of an isolated bank.

III. TRANSIENTS REDUCTION CONTROL Back-to-back switching is typified by the circuit shown in Fig. 3. The magnitude and frequency of the inrush current must be limited to ensure the proper operation of the switching device as well as relay, fuses, and etc. Where inrush currents are excessive, three system configurations were studied [6, 7].

A. Pre-insert resistors (PIR) The use of Pre-insertion resistors is an old technology. These resistors are designed to over-damp the circuit, preventing oscillations and allowing the capacitor to become essentially charged to line potential before main contacts of the switch close. In a switch first contacts the resistors before making contact with the capacitors. The operating time of switch is about one fourth of a cycle at 50 Hz (typically 5 ms).

B. Current limiting reactors (CLR) This method can be done by connecting a reactor in series with the capacitor bank to decrease the peak current and frequency of the oscillatory inrush transients. The reactor increases the magnitude of the surge impedance, effectively reducing the peak value of the inrush current.

C. 6% detuning reactor (6% reactor) The concept of this method is same as current limiting reactor. But this method can reduce the transients oscillation overvoltage and inrush currents better than CLR. However, the voltage at capacitor bank is increased and waveform of current and voltage are distorted from fundamental frequency. The main purpose of 6% reactor is to reduce inrush current and avoid the harmonic amplification from resonance problem. Practically, both the current limiting reactor and the 6% detuning reactor will limit the inrush current at the least step to the value not exceeding 50 times of the rated capacitor bank current.

IV. SYSTEM SIMULATION MODELING In order to obtain inrush current and transient oscillation voltage signals for investigation and analysis, PSCAD/EMTDC [8] was used in simulations with a sampling frequency rate of 250 kHz. The system under study includes cable and loop inductance between 4-step capacitor banks. The system under investigations is a part of Thailand electricity transmission network systems as shown in Fig. 4 [9]. The three phases voltage source model was represented by equivalent circuit with a short circuit value of 5 kA which is the connecting bus of the proposed capacitor bank. The impedance of bus (Zbus) is used to connect between each capacitor bank. Typical values of inductance per phase

between back-to-back switching capacitor banks and bank inductance for 230 kV voltage level is 0.935 H/meter [6]. This value does not include inductance of the capacitor bank itself. The tapping conductor from busbar to capacitor bank is a 1272 MCM ACSR conductor per phase. This cable conductor has an inductance of 0.707 H/meter. From Fig. 4, the group of capacitor bank no.1 was simulated while group of capacitor bank no. 2 to 5 disconnected. The capacitor banks switching in group no.1 was includes 4-step capacitors which have rated 72 Mvar, 230 kV and each step has bank configuration as Fig. 1. In order to give the switching transient patterns, the simulation cases to investigate the inrush current, the highest magnitude of transient overvoltage as well as inrush frequencies of oscillation were varied into 4 different cases as follows:

Base case (no transient limiting employed) by energizing the capacitor bank up to 4-step H-connection with grounded wye, rated 4x72 Mvar, 230 kV, 50 Hz.

Simulation using the pre-insertion resistor with a resistance value of about 10 .

Simulations using the current limiting reactors with an inductance value of about 1 mH per phase.

Simulations using the 6% detuning reactors with an inductance value of about 166 mH per phase.

Fig. 4. The system used in simulation [8] Finally, condition of the switching substation shunt capacitor banks was simulated without load connected in order to determine the worst case of highest inrush current.

A. Base case The capacitor banks are energized without transient reduction technique such as pre-insert resistor, current limiting reactor, and etc. The controlled capacitor bank was switched into the network and the worst-case switching occurs at the peak of the phase A system voltage. The peak of inrush current, highest magnitude of transient overvoltage and inrush

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current frequencies under system short-circuit 5 kA are summarized in Fig. 5 and Table I.

TABLE I PEAK CURRENT AND HIGHEST OVERVOLTAGE IN THE BASE CASE

Fig. 5. Inrush current when energizing step 4 at the peak of phase A system voltage, Ipeak_phA = 91.046 kA.

B. Simulation using the pre-insert resistor (PIR) In order to damp the transient inrush currents, the resistors were connected in series with the controlled switch capacitor bank. This mitigation method is conventional technology which requires the use of an additional switch to bypass the resistors one quarter of a cycle after the energization of the controlled bank [7]. The resistors were bypassed from the circuit for reduce the steady state losses. The simulation result was shown in Fig. 6 and Table II.

TABLE II PEAK CURRENT AND HIGHEST OVERVOLTAGE IN THE PIR

Fig. 6. Inrush current when energizing step 4 at the peak of phase A system voltage, Ipeak (phase A) = 18.107kA.

C. Simulation using the current limiting reactors (CLR) The inductance value is about 1 mH per phase. This reactor is used for limiting the peak inrush current between the banks. The inductor is selected to limit inrush current below the damage levels for the switching device, the capacitor unit and any associated equipment. From Fig. 7 and Table III. The magnitude of inrush current will be decreased while the highest of transient oscillation overvoltage decreases slightly when comparing with the base case. The use of current limiting reactor results in greater system inductance, which may be occurred to lower frequency of transient oscillation.

TABLE III PEAK CURRENT AND HIGHEST OVERVOLTAGE IN THE CLR

Fig. 7. Inrush current when energizing step 4 at the peak of phase A system voltage, Ipeak (phase A) = 10.829kA.

Since the current though the reactor cannot change

instantly, the higher frequency components of the transient are limited and the severity of the current inrush transient is reduced. Sometimes reactors are built intentionally with higher resistances to increase damping of the transient.

D. Simulation using the 6% detuning reactors The 6% detuning reactor or 6% detuned filter is mainly used to improve power factor same as shunt capacitor bank. But the 6% reactor is to limit the peak inrush current between the banks, which is the same mitigation method as using current limiting reactor. The simulation result was shown in Fig. 8 and Table IV. Moreover, 6% reactor also gives the advantage of reducing the harmonic voltages in the network by absorbing part of the harmonic currents with an order higher than the tuning frequency of the capacitor-reactor arrangement. Therefore, the inductance value in this paper is about 166 mH per phase which can be calculated in accordance with IEC 60871-1 [5] and IEC 61642 [11]. The 6% detuning reactor applied to avoid resonance problems is to keep the resonance frequency as far away as possible from the harmonic frequencies which have considerable amplitudes.

Peak current (kA)

Frequency (kHz)

Peak Bus voltage (kV)

Peak current (kA)

Frequency (kHz)

Peak current (kA)

Frequency (kHz)

Step 1 1.122 0.217 325.700 1.348 0.259 1.327 -Step 2 53.766 22.727 260.036 44.519 17.012 59.360 -Step 3 88.140 20.833 267.497 49.283 14.124 79.146 -Step 4 91.046 22.727 283.957 90.105 22.954 89.039 -

Step of switching

PSCAD/EMTDC IEEE Std C37.012 IEC Std 60871-1

PEAK CURRENT AND OVERVOLTAGE IN THE BASE CASE

0.824 0.825 0.826 0.827 0.828 0.829 0.83-100

-80

-60

-40

-20

0

20

40

60

80

100Capacitor Bank Inrush current when switching 4th bank

Inru

sh c

urr

ent

(kA

)

Time (sec)

Peak current (kA)

Frequency (kHz)

Peak Bus voltage (kV)

Step 1 1.011 0.212 312.947Step 2 14.901 22.727 256.154Step 3 16.718 22.727 257.380Step 4 18.107 22.727 278.313

PRE-INSERT RESISTORStep of

switchingPSCAD/EMTDC

0.825 0.83 0.835 0.84 0.845 0.85 0.855 0.86-5

0

5

10

15

20Capacitor Bank Inrush current when switching 4th bank

Inru

sh c

urr

ent (

kA)

Time (sec)

Peak current (kA)

Frequency (kHz)

Peak Bus voltage (kV)

Peak current (kA)

Frequency (kHz)

Peak current (kA)

Frequency (kHz)

Step 1 1.120 0.214 324.283 1.348 0.259 1.327 -Step 2 6.762 2.506 258.114 6.347 2.425 6.300 -Step 3 9.133 2.494 258.423 8.424 2.414 8.401 -Step 4 10.829 2.500 278.879 9.564 2.436 9.451 -

Step of switching

PEAK CURRENT AND OVERVOLTAGE IN THE CURRENT LIMITING REACTORPSCAD/EMTDC IEEE Std C37.012 IEC Std 60871-1

0.82 0.825 0.83 0.835 0.84 0.845 0.85-15

-10

-5

0

5

10

15Capacitor Bank Inrush current when switching 4th bank

Inru

sh c

urre

nt (

kA)

Time (sec)

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TABLE IV PEAK CURRENT AND HIGHEST OVERVOLTAGE IN THE DETUNING REACTOR

In case of 6% detuning reactor, the capacitance per phase is 3.647 F. Practically, reactors cannot be added to existing capacitors to make a detuned filter because the installed capacitors may not be rated for the additional voltage and/or current caused by the added series reactor. So, if designer need to design capacitor to be a 6% detuning filter, the rated of capacitor must be up sized Mvar. This presents significant improvement in the design and performance of 230 kV shunt capacitor bank to be the detuned filter bank in order to get rid of harmonic problem in the future.

Fig. 8. Inrush current when energizing step 4 at the peak of phase A system voltage, Ipeak (phase A) = 1.107kA.

V. CONCLUSIONS PSCAD/EMTDC was employed to evaluate and analyse the inrush current and transient oscillation overvoltage when energizing 230kV shunt capacitor bank in substation transmission system, including conventional calculation of inrush currents and frequencies. Both conventional calculation method based on published standards and transient simulations which are investigated in 4 different cases: base case, energization with pre-inserted resistor, using current limiting reactor and 6% detuning reactor for mitigation inrush current could be similarly in either conventional calculation or simulation (conventional calculation cannot determined in PIR case). From theory and simulation results, the pre-inserted resistors, current limiting reactor, and 6% detuning reactor have successfully mitigated transient inrush current and oscillation overvoltage. However, the simulation results show that the 6% detuning reactor can reduce inrush current and oscillation overvoltage better than other methods as shown in Fig. 9 and Table V. Practically, the network system of each substation is different, therefore, designer must investigate and consider the situation method to mitigate the inrush current and overvoltage especially devices with resistance provide for reducing voltage and current transients because it is loss in

circuit. The application of 6% detuning reactor will be done in the area of high distribution load (more than 4-steps of capacitor bank) and those in the industrial area.

TABLE V SUMMARIZATION OF PEAK INRUSH CURRENT FOR EACH MITIGATION METHOD

Fig. 9. Summarization of peak inrush current for each mitigation method (Result of 6% detuning reactor is satisfied).

ACKNOWLEDGMENT As the work presented in this paper is part of a research project sponsored by King Mongkuts Institute of Technology Ladkrabang (KMITL) research fund, Thailand, the authors would like to thank them for this financial support.

REFERENCES [1] IEEE Standard 1036-2010, IEEE Guide for Application of Shunt

Power Capacitors, 2011. [2] Ahmed Hassan Aly Amer, Transient over Voltages in Electric

Distribution Networks Due to Switching of Capacitor Banks Steps, International Conference on Electrical, Electronic and Computer Engineering (ICEEC2004), pp. 872-875, 2004.

[3] J. C. Das, Analysis and Control of Large-Shunt-Capacitor-Bank Switching Transients, IEEE Transactions on Industry Applications, Vol. 41, No. 6, pp. 1444-1451, 2005.

[4] L. Cipeigan, M. Chindris, J. Rull, A. Rusu, A. Sumper, R. Ramirez, and R. Alves, Mitigation of Capacitor Bank Energization Harmonic Transients, IEEE/PES Transmission & Distribution Conference and Exposition : Latin America, pp. 1-5, 2006.

[5] Thomas M. Blooming, and Daniel J. Carnovale, Capacitor Application Issues, IEEE Transactions on Industry Applications, Vol. 44, No. 4, pp. 1013-1026, 2008.

[6] IEEE Standard C37.012-2005, IEEE Application Guide for Capacitance Current Switching for AC High-Voltage Circuit Breaker, 2005.

[7] IEC Standard 60871-1, Shunt Capacitors for A.C. Power Systems Having a Rated Voltage Above 1000V Part 1 : General, 2005.

[8] M. F. Iizarry-Silvestrini, and T.E. Vlez-Seplveda, Mitigation of Back-to-Back Capacitor Switching Transients on Distribution Circuits, in Department of Electrical and Computer Engineering, University of Puerto Rico, 2006.

[9] Manitoba HVDC Research Centre, EMTDC: Transient Analysis for PSCAD Power System Simulation, Manitoba HVDC Research Centre Inc., Manitoba, Canada 2003.

[10] Switching and Transmission Line Diagram, Electricity Generation Authorization Thailand (EGAT), 2010.

[11] IEC Standard 61642, Industrial A.C. Networks Affected By Harmonics Application of Filters and Shunt Capacitors, 1997.

Peak current (kA)

Frequency (kHz)

Peak Bus voltage (kV)

Peak current (kA)

Frequency (kHz)

Peak current (kA)

Frequency (kHz)

Step 1 0.899 0.156 243.329 1.325 0.263 1.305 -Step 2 0.779 0.195 248.849 0.489 0.193 0.484 -Step 3 0.980 0.207 261.084 0.652 0.193 0.645 -Step 4 1.107 0.206 274.754 0.734 0.193 0.725 -

Step of switching

PEAK CURRENT AND OVERVOLTAGE IN THE 6% DETUNNING REACTORPSCAD/EMTDC IEEE Std C37.012 IEC Std 60871-1

0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9-1.5

-1

-0.5

0

0.5

1

1.5Capacitor Bank Inrush current when switching 4th bank

Inru

sh c

urr

ent (

kA)

Time (sec)

Mitigation

method Step 1 Step 2 Step 3 Step 4

Base case 1.122 53.766 88.140 91.046

PIR 1.011 14.901 16.718 18.107

CLR 1.120 6.762 9.133 10.829

6% Reactor 0.899 0.779 0.980 1.107

Peak Inrush Current (kA)

1 2 3 40

10

20

30

40

50

60

70

80

90

100Summarization of peak inrush current each of mitigation method

Inru

sh c

urre

nt (

kA)

Number of step switching

Base casePre-insert resistorCurrent limiting reactor6% detuning reactor

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