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iTOP readout firmware development

K. Nishimura and G. Varner 25-MAR-2011 lDAQ meeting

Not shown: Joshua Sopher (firmware)Lili Zhang (DSP coding)

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Overview• Status of various components

• Immediate deadline cosmic test in Japan• Essential gate prior to CERN beam test

• Today focus on this first deadlines• ASICs: BLAB3A or IRS2+amps• Progress on the 128-channel readout module

• Firmware/software development issues

• Kurtis will discuss schedule

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iTOP Readout Overview

8k channels1k 8-channel

waveform ASICs64 SRM

64 DAQ fiber transceivers

32 FINESSE8 COPPER

Precision timing requires 64 channels high-precision clock distribution (<~ 10ps) Approximately 30m runs

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Major milestone:1/16 system test

Third generation waveform

sampling ASIC

Clock jitter cleaners

A very crowded location!

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8k vs. 14k (CDC channels) << 10% of space!

First prototype iteration results

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Proposed modular solution

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Top view of new electronics showing the positions of the fiber transceivers and overall width

30mm

88.2mm

200.2mm

312.2mm

424.2mm

475.2mm

Top view of new electronics showing the positions of the fiber transceivers and overall width_030111.

30mm

88.2mm

200.2mm

312.2mm

424.2mm

475.2mm

Suzuki-san and Kohriki-san would like to see the fibers clustered into two ingress/egress positions.

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Such a change NOT a viable option

• Would require 2 completely different designs• Firmware would have to be different!• Timing would be different, different systematic effects, cannot interchange parts…

• Marc will discuss proposed reconfiguration• Helps with module seating/cooling• Other cable routing, cooling more plausible

• Rest of talk about components

Proposed modular solution

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BLAB3 Specifications32768 samples/chan (>5us trig latency)

8 channels/BLAB3 ASIC8 Trigger channels

~9 bits resolution (12[10]-bits logging)64 samples convert window (~16ns)4 GSa/s1 word (RAM) chan, sample readout

1+n*0.02 us to read n samples (of same 64)30 kHz sustained readout (multibuffer)

• Time alignment critical– Synchronize sampling to accelerator RF clock

– >5us a must for trigger, since single photon rates high

• Needs Gain!

BLAB3/IRS (amp/no-amp)

8x RF inputs(die upside down)

5.82mm

7.62mm

32k storage cells per channel(512 groups of 64)

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BLAB3/IRS Single Channel

• Storage: 64 x 512 (512 = 8 * 64)

• Sampling: 128 (2x 64 separate transfer lanesRecording in one set 64,

transferring other (“ping-pong”)

• Wilkinson (32x2): 64 conv/channel

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Sampling Simulation with full parasitic Extraction

0.000

0.500

1.000

1.500

2.000

2.500

3.000

3.500

4.000

4.500

5.000

0 0.5 1 1.5 2 2.5

RCObias [V]

Sam

plin

g R

ate

[GS

a/s]

Extracted

Sampling speed

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ARA Digitizer - 12-MAR-2011

IRS2 DC Linearity Calibration

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IRS2 Noise Measurement

<1mV

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Measurement via RF sine

Analog BW~1GHz

BLAB3A testing (carrier board)

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23mm x 50mm

Plan to submit soon BLAB3A

Proposed modular solution

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SCROD feasible?(mid-October)

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brainstorming the mechanical mockup(mid-November)

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Might work mechanically, if can really fit components…

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mechanical mockup(mid-November)

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brainstorming SCROD

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SCROD block diagram

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status of SCROD layout on Dec 23rd

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SCROD Fabricated

Rest of board stack needed: Firmware!!

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Proposed modular solution

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Data link margin (re-visited)

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Can work problem from other direction: 2.4Gbps (on 3Gbaud link)

At 30kHz L2 (100ns window, 0.3% RealTime) 80kbits/event at 512 bits/hit ~= 150 hits/link

~600 hits/event/iTOP counter Expect ~4 background p.e./event

Maintain > 10x link margin

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Beam test: a 1/16 system test

Third generation waveform

sampling ASIC

Clock jitter cleaners

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Summary/Open issues• Much firmware work needed

• Help from PNNL; write system documentation

• Hardware – confirm items previous slide• Complete BLAB3A carrier, routing boards• Interface board done, submit 3x designs soon

• Confirm performance of integrated module, including with MCP-PMTs

• Development manpower resource limited (next talk)

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Back-up slides

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Photo-detector: Hamamatsu SL-10• Micro-channel Plate:

– Operates in 1.5T B-field

– <50ps single photon timing

• Multi-pixel (4x4 anode pads)

• Enhanced Lifetime (Al protection layer)

• Interesting mechanical challenges (PMT case at HV)

Approximately 1” x 1”

BLAB3 status and scheduleSpecification BLAB3 BLAB3A BLAB3B FINAL

Analog Bandwidth

175 MHz 400MHz 500MHz? 400-600MHz

Gain [50 ref] 34-36x 60x 100x ? SNR>=50

Sampling speed [Giga-sample/s]

3.6 3.8 4.0 4.0

Usable sampling speed

~1.4 3.8 4.0 >= 3

Internal DACs no no yes yes

Design completion

Sept.2009

Sept.2010

January2011

Autumn2011

Delivery Jan. 2010 Nov. 2010 May 2011 Winter 2011

quantity 120 240* 120? 1000

* = not for Belle2, but will learn from design

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SL-10 Timing PerformanceNagoya Hawai’i

σ ~ 38.37

• Nagoya = constant fraction discriminator + CAMAC ADC/TDC

• Hawai’i = waveform sampling + feature extraction

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High speed Waveform sampling“oscilloscope on a chip”

• Comparable performance to best CFD + HPTDC

• MUCH lower power, no need for huge cable plant!

• Using full samples reduces the impact of noise

• Photodetector limited 6.4 psRMS

CH1

CH2

Advanced Detector Research award

NIM A602 (2009) 438

Belle2 barrel PID upgrade: iTOP

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references and further info

references: http://b2comp.kek.jp/~twiki/pub/Organization/

B2TDR/B2TDR.pdf http://www.phys.hawaii.edu/~idlab/

taskAndSchedule/ICBMS.pdf latest info:

http://idlab.phys.hawaii.edu/pcb-designs/scrod

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