1 Lab Manual

LINEAR INTEGRATED CIRCUITS LAB

2 Lab Manual

1. Measurements of Op-Amp parameters- CMRR, slew rate ,open loop gain,

input and output impedances

2. Inverting and non inverting amplifiers, integrators, and differentiators-

frequency response, comparators- zero crossing detector Schmitt trigger –

precision limiter

3. Instrumentation amplifier - gain ,CMMR & input impedance

4. Single op amp second order LPF & HPF, Narrow band active BPF

5. Active notch filter realization using op- amps

6. Wein bridges oscillator with amplitude stabilization

7. Square ,triangular and ramp generation using op- amps

8. Astable and monostable multi vibrators using IC 555

9. Astable and monostable multi vibrators using op- amps

10. Voltage regulation using Ic 723

11. Realisation of ADCs and DACs

3 Lab Manual

1.Measurements of Op-Amp parameters

AIM: To measure the following parameters of an op- amp

1. CMRR

2. slew rate

3. Input bias current

4. Input offset current .

Components and Equipments required: Power supplies, CRO, function

generator, op- amp, resistor ,capacitors & bread board.

THEORY:

1.CMRR- It is the ratio of differential mode gain to common mode gain . If a

signal is applied common to both the inputs of op –amp , signal will be attenuated.

CMRR is usually expressed in dB. When an input signal Vs is applied, common to

both inputs , common mode voltage gain Ac = Vo/Vs. Differential mode gain

Ad = Rf/Ri. Then CMRR is given by the expression CMRR = 20 log (Ad/Ac) in dB

2.Slew rate – slew rate is the maximum rate of rise of output voltage. It is the

measure of fastness of op- amp. It is expressed in V/µs. The internal output

capacitance prevents sudden rise of output voltage for a fast rising input . If the

slope requirements of the output voltage of the op-amp is greater than the slew

rate, distortion occurs.

3.Input bias current IB :

The inverting and non inverting non inverting terminals of an opamp are two

base terminals of the transistors of a differential amplifier. In an ideal op-amp no

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current flows through these terminals . However , a small amount of current flows

through these terminals which is of the order of nA in bipolar op- amps and pA

for FET pA for FET op-Amps .

Input bias current is defined as the average of the currents entering in to the

inverting and noninverting terminals of an opamp. To compensate for bias

currents, a compensating resistor Rcomp is used. Value of Rcomp is the parallel

combination of the resistors connected to the inverting terminal.

Input Bias current IB = (IB1 + IB2)/2 where IB1 and IB2 are the base bias currents

of the op-amp.

5. Input offset current IOS:

The bias currents IB1 and IB2 are not equal in an opamp. Input offset

current is defined as the algebraic difference between the currents into the

inverting and noninverting terminals . Typical and maximum values of

offset current are 20nA and 200 nA

Input offset current IOS= IB1 - IB2

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CIRCUIT DIAGRAMS:

RF 100K

R 100Ω 2 +15V

R 100Ω 3

-15V

Vin

100K

Circuit to measure CMRR

+15V

2 7

- 6 Vo

+

3 4

-15V

Circuit to measure slew rate

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2 +15v

- 7 6

+ Vo

3 4

1M -15v

0.01µF

bias current Ib1

Rf 100k

0.01µF

2

- 6 Vo

+

3

bias current Ib2

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7 Lab Manual

PROCEDURE:

1) Setup the circuit for finding CMRR. Apply a dc signal of 0.5 V at the input and

measure Vo. Calculate CMRR using the expression

CMRR = Vi(Rf/Ri)

Vo

Express CMRR in dB using the expression 20log(CMRR)

2) Feed a square wave to input and calculate slew rate using the expression

SR = ΔVo/t; where ΔVo is the voltage swing and t is the time taken to change

the voltage levels

3)Set up the circuits for measuring input bias current and input offset current.

Measure the output voltage . Using the expression Vo = IB1R and Vo = IB2 R, IB1

and IB2 are calculated. Use the expression

IB = (IB1 + IB2)/2 ,

IOS = IB1 - IB2

RESULT:

Measured the parameters of an Op- Amp.

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2.Basic Operational Amplifier Circuits

AIM: To design and setup the following basic operational amplifier circuits

1. Inverting and non inverting amplifiers,

2. Integrators, and differentiators

3.Comparators- zero crossing detector

4.Schmitt trigger

Components and Equipments required: Power supplies, CRO, function

generator, op- amp, resistors ,capacitors & bread board.

THEORY:

1 a)Inverting amplifier :

This is one of the most popular op- amp circuits . The polarity of the

input voltage gets inverted at the output. If a sine wave is fed to the input of this

amplifier , the output will be an amplified sine wave with 1800 phase shift. The

gain of the inverting amplifier is given by the expression A = - Rf/Ri where Rf is

the feed back resistance and Ri is the input resistance . Inverting amplifier can be

used as a scalar because the amplitude of the output can be varied by varying either

of the resistors Rf or Ri.

CIRCUIT DIAGRAM:

t

t

9 Lab Manual

Rf 10k

+15v

Ri 1K 2 7

- Vo

+

Vin 2Vpp 3 4

-15v

Design:

Gain of an inverting amplifier A = - Rf/Ri

Let the required gain be -10

Then, Rf/Ri = 10 take Ri = 1K, Therefore , Rf = 10k

PROCEDURE:

1. Setup the inverting amplifier on the bread board

2. Feed a 2 Vpp sine wave and observe the input and output

simultaneously on CRO. Verify whether the output is 20Vpp sine

wave with 1800 out of phase with the input.

3. Vary the frequency of the input from 0 to a few MHz. Note down the

output voltage . draw the frequency response characteristics.

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Tabular column and frequency response

20 log vo/vin dB

3 dB

fc Log f

b) Non inverting amplifier:

This circuit provides a gain to the input signal without any change in

polarity. The gain of the non inverting amplifier is given by the expression

A = 1 + Rf/Ri

Where Rf is the feedback resistance and Ri is the input resistance . The input

impedance of non inverting amplifier is extremely large ,typically100 MΩ.

F (Hz) Vo(volts) Log f 20 log (vo/vin)db

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CIRCUIT DIAGRAM:

t

t

Rf 10k

+15v

Ri 1K 2 7

- Vo

+

Vin 2Vpp 3 4

-15v

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Design:

Gain of non inverting amplifier A =1+ Rf/Ri

Let the required gain be 11

Then, Rf/Ri = 10 take Ri = 1K, Therefore , Rf = 10k

PROCEDURE:

1. Setup the non inverting amplifier on the bread board

2. Feed a 2 Vpp sine wave and observe the input and output

simultaneously on CRO. Verify whether the output is 20Vpp sine

wave in phase with the input.

3. Vary the frequency of the input from 0 to a few MHz. Note down the

output voltage . draw the frequency response characteristics.

Tabular column and frequency response

20 log vo/vin dB

3 dB

fc Log f

F (Hz) Vo(volts) Log f 20 log (vo/vin)db

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2 a) Integrators:

The circuit performs the integration of the input waveform. The output voltage

Vo can be expressed as Vo = -1/RC ∫Vidt +k where k is the constant of the

integration which depends upon the value of Vo at t = 0. The peak of the output

waveform VT is given by the expression VT = VT / 4RC, where T is the time

period of the input square wave . Integrators are commonly used in analog

computers and wave shaping networks.

At low frequencies of the input voltage , capacitor behaves as an open circuit.

Op-amp may saturate at low frequency even for a very low voltage at the input.

This is because the open loop gain is very high . A high value feed back resistor Rf

is connected across the capacitor to prevent the op amp from going saturation.

When Rf is connected , gain will be reduced considerably at low frequencies . At

higher frequencies circuit behaves as an ordinary integrator. In other words at low

frequencies Rf is effective and C is effective at high frequencies in the feed back

path. Integrator is a first order Low pass Filter . It permits low frequencies to pass

to output.

CIRCUIT DIAGRAM:

150K

0.01µF

R 7 +15V

15K - 2

Vin 6 Vo

2Vpp + 3 4

-15V

Integrator

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Wave forms

Vin +V

-V

Vo

VT/4RC

Design:

Let the input frequency be 1 kHz. We have , f = 1/2πRC

Let C = 0.01 µF. Then R = 15.9 k. Use 15k std.

Select RF = 10 R = 150k so that break frequency is 100 hz.

Tabular column and frequency response

F (Hz) Vo(volts) Log f 20 log (vo/vin)db

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20 log vo/vin dB

3 dB

…………………………………….

fc Log f

PROCEDURE:

1. Setup the integrator circuit on the bread board

2. Feed a 2 Vpp 1ms square wave and observe the difference at the

input and output simultaneously on CRO.

3. Vary the dc offset of the square wave and observe the difference in

the output waveform.

4. Repeat the experiment by feeding the triangular wave and sine wave

at the input and observe the output

5. Feed a sine wave to the input and note down the output amplitude by

varying the frequency of the sine wave . Enter it in the tabular column

and plot the frequency curve.

b) Differentiators:

If the input resistance of the inverting amplifier is replaced by a capacitor , it

forms an inverting differentiator . The output of the circuit is the derivative of the

input. Gain of the differentiator increases with increase in frequency which makes

the circuit unstable. This is the drawback of this circuit.

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The output voltage Vo can be expressed as Vo = -RFCi(dVi/dt).

Differentiator functions as High pass filter . At high frequency it becomes unstable

and breaks into oscillation. Input impedance decreases with increase in frequency

which makes the circuit very susceptible to high frequency noise.

CIRCUIT DIAGRAM:

Wave forms

Vin +V

-V

Vo R2C2

15K

0.01µF

0.01µF 56K 2 7 +15V

- Vo

+ 6

Vin 2Vpp 3 -15V

4

Differentiator

17 Lab Manual

Design:

We have T 2 RFC take T = 1 ms and C – 0.01 µF

Then RF = 15.9k use 15k std

Select T = RiCi = RFCF =1/2πf wher f is the highest frequency to be

differentiated

Take Ci = CF = 0.01 µF

PROCEDURE:

1. Setup the differentiator circuit on the bread board

2. Feed a 2 Vpp 1ms square wave and observe the difference at the

input and output simultaneously on CRO.

3. Repeat the experiment by feeding the triangular wave and sine wave

at the input and observe the output

4. Feed a sine wave to the input and note down the output amplitude by

varying the frequency of the sine wave . Enter it in the tabular column

and plot the frequency curve.

Tabular column and frequency response

F (Hz) Vo(volts) Log f 20 log (vo/vin)db

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20 log( Vo/Vin)dB

3 dB

Log f

Zero crossing detector (ZCD):

It is a comparator that switches the output between +Vsat and – Vsat when

input crosses zero reference voltage. The output is drive into -Vsat when the input

signal passes through zero to positive direction . Conversely, when the input signal

passes through zero to negative direction , the output switches to +Vsat. This

circuit can be used to check whether the op amp is in good condition.

CIRCUIT DIAGRAM:

+15V

2 7

- 6

Vin + 3

4

-15V

Zero crossing Detector

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19 Lab Manual

Wave forms

Vo +Vsat

-Vsat

Vo

+Vsat

Vin

20 Lab Manual

PROCEDURE:

1. Wire up the op amp as zero crossing detector.

2. Feed a 100mV sine wave at the input and

verify whether the output is square wave swinging from +13V to - 13V

approximately

COMPARATOR:

It is a circuit which compare a signal voltage applies at ona input of an

opamp with a Known reference voltage at the other input. It is basically an

openloop opamp with output ± Vsat.

CIRCUIT DIAGRAM:

+15V

2 7

- 6

Vin + 3

2V 4

-15V

COMPARATOR

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21 Lab Manual

+Vsat

-Vsat -Vsat

Schmitt trigger:

Schmitt trigger is a comparator and it is known as squaring circuit because it

converts an irregular shaped waveform to a square wave. The output voltage

changes state every time when input voltage crosses the threshold levels. The input

voltage at which output switches from + Vsat to – Vsat is called the Upper

triggering point (or upper threshold point ,UTP). The input voltage at which output

switches from _ Vsat to + Vsat is called and lower Triggering point(or Lower

Threshold point, LTP)

These threshold voltages are obtained by the voltage divider R1 – R2. Suppose

the output voltage is +Vsat. Now the voltage across R2 is

VUTP = +Vsat R2/(R1 +R2).

When the input voltage exceeds the voltage across the resistor R2, output goes to

-Vsat. Now the voltage across R2 is VLTP = -Vsat R2/ (R1 + R2). When the input

voltage goes lower than this voltage , output goes to + Vsat.

PROCEDURE:

1. Verify whether the op amp IC is in good condition . This can be done by

using it as ZCD or voltage follower .

2. Set up the ckt one by one . Observe the input and output on the CRO screen

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3. Observe the transfer characteristics .

+15

2 7

- Vo

+ 3

4 -15V

Vin 10K

20Vpp 3.3K

Schmitt Trigger

Vin

+vsat

-3v +3v Vin

+Vsat

-Vsat Vo

Hysteresis curve -Vsat

RESULT:

Designed and setup basic operational amplifier circuits and observed the

waveforms.

-3v

741

23 Lab Manual

3.Instrumentation Amplifier

Aim:

To design and setup an instrumentation amplifier using three op amps to

obtain a minimum gain of 3 for the difference of inputs.

Components and equipments required

DC source ,CRO, breadboard , op- Amp, breadboard ,potentiometer and resistors.

Theory:

Instrumentation amplifier s are widely used in data acquisition systems,

remote sensing applications and instrumentation systems to measure temperature

,humidity, light intensity and weight etc. Most of the instrumentation systems use a

transducer in a bridge circuit. Instrumentation amplifier facilities the amplification

of potential difference taking place due to the imbalance of a bridge circuit

proportional to a change in physical quantity . The main features of

instrumentation amplifiers are high gain , high input resistance, high CMRR etc.

Procedure:

1.Set up V1 = 0.5V dc and V2 = 0.4 V dc and measure output voltage on CRO

or using multi meter, keeping RA in minimum position.

2.Repeat the above step by keeping RA in minimum position. Measure the

difference in gain . This is the difference mode gain Ad

3.Feed V1 = V2 = 0.5V and observe the gain keeping RA in minimum

position . This is common mode gain Ac. Calculate CMRR from the relation

CMRR = 20log (Ad /Ac)

24 Lab Manual

Circuit Diagram:

+15

3 7

6 Ri 10k

V2

2 4 Ri Ri 10k +15V

-15 10k 2 7

- 6 V0

RA +

10k pot Ri 10K 3 4

-15V

+15 Ri Ri 10k

2 7 10k

- 6

3 + 44

V1 4

-15

Design

We have ,Vo = (V1 – V2)[1+(2Ri /RAmax)]

Given, 2 Ri/RAmax = 3. Take R and RA = 10 k

Result:

Common mode gain AC = ………

Difference mode gain Ad = ……... CMRR = …………

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25 Lab Manual

4. SINGLE OP-AMP SECOND

ORDER LFF AND HPF , NARROW BAND ACTIVE BPF

4a)Second order Low pass filter

AIM: To design and set up a second order low pass Butterworth filter for a higher

cutoff frequency of 1 kHz.

Components and Equipments required

Op amp, resistors, capacitors ,dual DC source or two DC sources, signal

generator , Bread board and CRO.

THEORY:

The roll – Off of the second order filter is 40dB/decade. A first order low pass

filter can be converted into a second order type simply by using an additional RC

network. The gain of second order filter is set by R1 and RF, while the higher cut

off frequency fH is determined by R2 , C2 R3 and C3 as a given by the

expression. fH = 1/2π

At low frequencies , both capacitors appear open, and a circuit becomes a voltage

follower . As the frequency increases , the gain eventually starts to decrease .

26 Lab Manual

CIRCUIT DIAGRAM;

RF 15k

Ri 10k +15V

7

6 V0

R2 22k R3 22k 4

-15v RL 10k

C2 C3 0.01 µF

0.01µF

DESIGN:

Required cutoff frequency fH = 1 kHz

We have fH = 1/2π

Take C2 = C3= 0.01µF . Then R2 = R3= 22K

For R2 =R3 and C2 = C3, the pass band gain AF 1 + RF/R1 must be 1.586.

That is ,RF = 0.586R1 take R1 = 27k. Then RF = 15 .82k . Use 15k

PROCEDURE:

1. Setup the circuit and feed a 2Vpp

sine wave from the signal generator.

2. Vary the frequency of sine wave

in steps and note down corresponding output voltage . Plot the frequency

on a semi log graph sheet.

3. Mark higher cut off frequency on

the graph sheet and calculate the roll off in dB/decade from the graph sheet

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27 Lab Manual

Tabular column and Graph

Vin = 2Vpp

20 log (V0/Vin)dB

-------3dB------------------

Log fH log f

RESULT:

Theoretical fH = ………Hz Observed fH = ……

Theoretical pass band gain = ……. Observed pass band gain = …….

Roll – Off = ………dB/decade

F (Hz) Vo(volts) Log f 20 log (vo/vin)db

28 Lab Manual

4b) Second order high pass filter

Aim:

Design and setup a second order high pass filter for a lower cut off

frequency of 1 Khz.

Components and equipments required:

Op- amp, resistors , capacitors , dual DC source , signal generator ,bread board and

CRO.

Theory:

A second order high pass filter can be constructed from a second order high pass

filter by interchanging the frequency deciding resistors and capacitors .

Consider the circuit diagram . At low frequencies the capacitors appear open

and voltage gain approaches zero. At high frequencies , the capacitors appear short

circuited and circuit becomes a non inverting amplifier . The cut of frequency of

the filter is given by the expression

If C2 = C3 = C and R2 = R3 = R. then f L = 1/2πRC

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CIRCUIT DIAGRAM:

27k RF 15k

Ri 10k +15V

- 7

2 6 V0

0.01µF 0.01µF 3 4

+ -15v RL 10k

15k 15k

Vin 2V pp

Design :

Required cut off frequency fL = 1 kHz. We have ,

If C2 = C3 = C and R2 = R3 = R . Then fL = 1/2πRC

We have , fL

We have , fL = 1/2πRC

Assume ,C 0.01 F. Then R = 15.9k. Use R2 = R3 15 k std

The pass band gain AF = 1+ RF/R1 = must be 1.586 for butterwort filter.

That is ,RF =0. 586 R1 Take R1 = 27k. Then RF . Then = 15.82k. use 15k

PROCEDURE:

1. Setup the circuit and feed a 2Vpp

sine wave from the signal generator.

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30 Lab Manual

2. Vary the frequency of sine wave

in steps and note down corresponding output voltage . Plot the frequency

on a semi log graph sheet.

3. Mark higher cut off frequency on

the graph sheet and calculate the roll off in dB/decade from the graph sheet

Tabular column and Graph

Vin = 2Vpp

RESULT:

Theoretical fH = ………Hz Observed fH = ……

Theoretical pass band gain = ……. Observed pass band gain = …….

Roll – Off = ………dB/decade

4.cBAND PASS FILTER

AIM:

To design and setup a band pass filter have fo = 1khz,Q = 3, and gain AF = 10

Components and equipments required . Op- amp, resistors ,capacitors ,dual

DC source, signal generator, bread board and CRO

THEORY:

A band pass filter passes a particular band of frequencies with zero

attenuation and attenuates all other frequencies. It is very widely used in analog

and digital communication applications . The classification of narrow band and

wide band filters made based on the quality factor Q. If the quality factor Q<0.5 it

is called as wide band filter and if Q >0.5, it is narrow band filter .

F (Hz) Vo(volts) Log f 20 log (vo/vin)db

31 Lab Manual

If an LPF having cut off frequency fH is cascaded with HPF having cut off

frequency fL such that fH > fL ,it forms a BPF with band FH - FL . Narrow band

filters are constructed with single stage. Multiple feedback method is used in the

narrow band BPF for which the following relationships are important.

Q = fo/BW = fo/ (fH - fL) where fH = upper cutoff frequency, fL = lower cutoff

frequency, fo = centre frequency and BW = band width

This filter uses only one op -amp in the inverting mode. It has two feedback

paths . To simplify design calculations ,take C1=C2=C

Where is the gain at fo i..e… = R3/2R1. It should satisfy the condition

CIRCUIT DIAGRAM

C1, 0.01µF

Rr 100k

R1 4.7k C1, 0.01µF +15v

2 7 Vo

6

Vv vin 2vpp 3 4

R2 6.2k -15v

R3100k

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32 Lab Manual

Band pass filter

DESIGN:

Take C1= C2= 0.01 µF

R1 = 3/2π(103)(10

-8) 10 = 4.77k. use 4.7k std

R2 = 3/2π(103)(10

-8) (18-10 ) = 5.97k. use 6.2 k std

R3 = 3/π(103)(10

-8) = 95.5k. use 100k std., Use RL = 10k

PROCEDURE:

1. Set up the circuit and feed a 2 Vpp sine wave from the signal

generator

2. Vary the frequency of the sine wave in steps and note down

corresponding output voltage .

3. Plot the frequency response on a semi log graph sheet . mark

the pass band.

4. Tabular column and Graph

Vin = 100mV

F (Hz) Vo(volts) Gain in

dB

33 Lab Manual

gain in dB

--------------------------- M dB

------------------------------- (M-3)dB

Log f

Log fl logfH

RESULT: Bandwidth :………Hz

5. ACTIVE NOTCH FILTER USING OP- AMPS

Aim: To design and set up a narrow band elimination filter (notch filter)

and to draw the frequency response characteristics.

Components and equipments required Op- amp, resistors ,capacitor s,dual

DC source, signal generator ,bread board and CRO

Theory

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Band elimination filter is also known as band rejection filter or band

stop filter . Wide band rejection filter can be setup by connecting a low pass

filter and high pass filter in parallel .If an LPF with fL is connected in

parallel. If an LPF with f L is connected in parallel to HPF with f H such

that f H > f L ,it forms a BEF with bandwidth f H - f L.

Narrow band reject filter is also known as notch filter . Notch filter

provides maximum attenuation at the frequency fo = 1/2πRC. This is

achieved by a twin – T RC network. Passive twin – T network has

relatively low figure of merit Q . The Q can be increased by associating

with a voltage follower using op- amp.

Notch filter has wide application in communication field. It is used to

eliminate undesired frequencies. The very common application is to remove

power supply hum occurring at 50 Hz.

PROCEDURE :

Setup the circuit and feed a 2vpp sine wave from the signal generator.

Vary the frequency of the sine wave in steps and notedown the corresponding

output voltage.

Plot the frequency response on the semilog graph sheet.

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CIRCUIT DIAGRAM :

2 7

R 15k R 15k - 6 V0

+

-15V 10K

R/2

2C Notch filter

0.022µ

Design

Required notch frequency fN = 1/2πRC = 1 kHz

Take C = 0.01µF . Then R = 15k.

Take 2C = 0.022µF and R/2 = 8.2k.

F (Hz) Vo(volts) Gain in

dB

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36 Lab Manual

Gain in db

Log fN Log f

RESULT

Designed and setup notch filter plotted the frequency response characteristics

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6.WIEN-BRIDGE OSCILLATOR WITH AMPLITUDE STABILISATION

AIM

To design and set up a Wien-bridge oscillator with amplitude stabilization for

a frequency of 1 kHz.

COMPONENTS REQUIRED

741IC, resistors, capacitor, diode, dc source

CIRCUIT DIAGRAM

R 1.5K Rf 4.7K +15V

2 7

C 0.01µF - 6 VO

+

3 4 D

-15V

BFW10

0.01µF Rs

1.5 Cs 0.01µF 1M

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38 Lab Manual

DESIGN

The frequency needed is 1 kHz.

f0 = 1/2πRC = 1 kHz let C = 0.1µF, then

R= 1.6k. ; R=1.5kstd

For sustained oscillations, 1+ ( Rf/ Ri ) = 3

Select Ri = 1 kΩ and Rf = 2.2k take 4.7k pot

Use Rs = 1M andCs = 0.1µF

THEORY

The Wien bridge oscillator is a circuit for generating low frequency in the

range of 10Hz to about 1MHz. It is widely used in commercial generators. The

basic network forms a bridge in the feedback circuit. That is why it is called as

Wien bridge oscillator. The Wien bridge consists of a series RC circuit and parallel

RC circuit as shown in figure

The circuit shown here uses both negative and positive feedback. Circuit behavior

is strongly affected by whether positive or negative feedback prevails. Here the

feedback factor is found to be of the form β =1/[3+j(f/fo – fo/f)];which is of band

pass nature ,which has a maximum value of 1/3 at f= fo =1/(2πRC).At this point

the loop phase is 0o

.Hence by barkhausen criteria, oscillation will start if A β>1,i.e

if the gain of the amplifier is greater than 3.Hence for the oscillation to start,

initially gain should be greater than 3 slightly and finally it should settle down at a

gain of 3,where the amplitude of oscillation stabilizes. For this we use an

amplitude stabilization circuitry consisting of resistors and diodes.

The frequency of oscillation can be varied by varying the capacitors

simultaneously. These capacitors are variable air-gang capacitors. We can change

the frequency range of the oscillator by connecting different values of resistors.

The Wien bridge oscillator is therefore suitable for audio frequency generators.

39 Lab Manual

PROCEDURE

Check the op-amp. Setup the circuit on the breadboard as shown in figure.

Ensure that op-amp is operating as an amplifier of required gain. Observe the

output on the CRO. Adjust the potentiometer to get the sine wave without any

distortion or clipping. The amplitude is almost equal to Vsat.

RESULT:

Designed and setup Wien Bridge oscillator using opamp.

40 Lab Manual

7.SQUARE, TRIANGULAR & SAWTOOTH WAVE GENERATORS

AIM:

To design and set up a square with amplitude ± Vsat and triangular wave

with amplitude ± 2.5V for a frequency of 1 KHz

To design and set up a triangular wave generator with amplitude +2.5 V

and a frequency of 2 KHz

To design and set up a saw tooth wave generator with amplitude ± 2.5 V &

for a risetime t1 = 2ms and fall time t2 = 0.2 ms

To design and setup a saw tooth wave generator with amplitude + 2.5 ms

and for a rise time t1 = 1ms and fall time of t2 = 0.1 ms

COMPONENTS AND EQUIPMENT REQUIRED:

IC 741 (2), resistors (5.6-(2), 15K, 1K, 56K), capacitors (0.1µF), diode 1N4001(3),

DC source (±15 V), bread board and CRO

THEORY:

The square wave triangular wave generator uses two operational

amplifiers. One (A1) functions as a comparator and other (A2) as an integrator.

Comparator compares the voltage at point P continuously with the inverting input

that is at 0V. When the coltage at P goes slightly above or below 0V, the output of

A1 is at negative or positive saturation level respectively. At the output of the

comparator we get a square wave with amplitude ± Vsat. Suppose the output of A1

is at positive saturation + Vsat. Since this voltage is the input of the integrator, the

output of A2 will be a negative going ramp. At time t = t1, when the negative going

ramp attains values of –Vramp, the effective voltage at point P is slightly less than

zero. This switches the output of A1 from positive saturation to negative

41 Lab Manual

saturation. During the time when output of A1 is –Vsat, the output of A1 increases

in positive direction till it reaches +Vramp. At this point P is slightly above 0V,

therefore the output of A1 is switched back to positive saturation level +Vsat. The

cycle repeats and generates a triangular waveform. The frequency of triangular

waveform is given by . Peak to peak amplitude is .

In the triangular wave generator with amplitude +Vramp, a diode is

connected in the feedback path. The circuit has 2 op-amps. One A1 functions as a

comparator and the other A2 functions as an integrator. Suppose output of A1 is at

negative saturation –Vsat. Since this voltage is the input of integrator, its output will

be a positive going ramp. Thus one end of the voltage divider is at –Vsat and the

other end at positive going ramp. When the positive going ramp attains a value

Vramp the output of A1 switches from negative saturation too positive saturation.

Since the output of A1 is at positive saturation, then the diode is reverse biased.

Output of A2 is a negative going ramp and when the output of A1 reaches zero, the

output of A1 switches from +Vsat to –Vsat, and the cycle repeats.

In a sawtooth wave generator, the rise time is higher than fall

time or vice versa. A triangular waveform generator can be converted to a

sawtooth by a diode resistor network shown in the circuit. During positive

saturation at output of A1, upper diode D1 conducts and R3’ will be effective. The

current for charging the capacitor will be high if R3’ is effective because R3’< R3”.

Hence the output of A2 which is a negative going ramp with steeper slope and

hence the fall time of a sawtooth wave decreases. Similarly during negative

saturation at output of A1, upper diode D1 is everse biased and lower diode D2

conducts and R3” will be effective. The current through the capacitor will be less

because R3”> R3’. Hence the output o A2 is a positive going ramp with less steeper

slope. Hence the rise time of the sawtooth wave increases.

In a sawtooth wave form generator with amplitude +Vramp , a diode

is connected in the feedback path. It consists of 2 op-amps. One (A1) functions as a

comparator and the other (A2) functions as an integrator. Consider the instant at

which the output of A1 is at negative saturation –Vsat; then the lower diode D2

42 Lab Manual

conducts and R3” will be effective. The output of A2 will be a positive going ramp.

When the output of A2 goes reaches of +Vramp the effective voltage at P is slightly

less than zero. This switches the output of A1 from negative to positive saturation.

When output of A1 is +Vsat , the diode in the feedback path is reverse biased and

upper diode D1 conducts. Therefore the output of A2 is a negative going ramp and

when the ramp reaches zero, the output of A2 switches from +Vsat to –Vsat and the

cycle repeats.

CIRCUITDIAGRAM

DESIGN

Vramp =Vsat R2/R3

Let Vramp= 6V , Vsat= 13V

Then for R2= 1K , R3= = 2.6K Select 2.7K std .

Also time period T =

43 Lab Manual

For T = 0.1 ms

Let C = 0.01 μF, then R1 = = 6.75 K Select 6.8K std

PROCEDURE:

Set up the circuit of square cum triangular wave generator on

the breadboard after checking all components and op-amps. Observe the square

wave output of the first op-amp. Note down the amplitude and frequency of the

square wave Observe the output of the second op-amp which is a triangular wave

Note down the amplitude and frequency of the waveform Set up the triangular

wave generator for amplitude +Vramp , after checking all components and op-amps

Observe the triangular wave form at the output of the second op-amp Note down

the amplitude and frequency of the triangular waveform generator Set up the

circuit of the saw tooth generator on the breadboard after checking all the

components and op-amp Observe the sawtooth waveform at the output of the

second op-amp. Note down the amplitude, time period of rise time & time period

of fall time Set up the circuit of sawtooth wave generator with amplitude +Vramp,

after checking all the components and op-amp. Observe the output waveform at the

output of the 2nd

op-amp Note down the amplitude and time periods of rise and fall

times

Vsawtooth

44 Lab Manual

RESULT:

A square wave generator cum triangular waveform generator was designed and

setup for square wave amplitude = ±Vsat, Triangular wave amplitude = ±2.5V,

Frequency =2 KHz

Observed amplitude of the square wave =

Observed amplitude of the triangular wave =

Observed frequency =

A triangular wave generator is designed and setup for an amplitude +2.5 V and a

frequency of 2 KHz

Observed amplitude of triangular wave =

Observed frequency =

A saw tooth wave generator was designed and setup for an amplitude of 2.5 V, rise

time of 2ms and fall time 0.2 ms

Observed sawtooth amplitude =

Observed rise time =

Observed fall time =

45 Lab Manual

A sawtooth wave form generator was designed and setup for an amplitude of 2.5V,

rise time t1 =1 ms and fall time t2 = 0.1 ms

Observed sawtooth amplitude =

Observed rise time =

Observed fall time =

46 Lab Manual

8. ASTABLE & MONOSTABLE MULTIVIBRATOR USING IC 555

AIM

To design and setup a monostable multivibrator using 555 timer for a pulse-width

of 1ms

COMPONENTS REQUIRED

555 IC, resistors, capacitors, dc source

CIRCUIT DIAGRAM

47 Lab Manual

DESIGN

Take VCC=10 V

Pulse width T = 1.1 RC = 1ms

Let C = 0.1 uf, then R = 9.09 kΩ, select standard value of 10 kΩ

Trigger RiCi=0.016 Tt Take Tt =3ms

For Ri=5.6K, then Ci=0.01 uF

THEORY

The circuit diagram is shown in fig. Here the resistor R and the capacitor C are

external to the chip and their values determine the output pulse-width. The three

equal resistance R inside the chip establish the reference voltages 2Vcc/3 and

Vcc/3 for comparators C1 and C2 respectively.

Before the application of the trigger pulse Vt, the voltage at the trigger input is

high which is equal to Vcc.With this high trigger input , the output of the

comparator C2 will be low causing the FF output Ǭ to be high. Now the discharge

transistor Q1 will be saturated and the voltage across the timing capacitor C will be

essentially zero.

At t=0, application of trigger V t, less than Vcc/3 causes the output of the

comparator C2 to be high. This will set the FF with Ǭ now low. The discharge

transistor will be turned off. Now the timing capacitor charges up towards Vcc via

resistor R, with a time constant τ=RC .When this charging voltages reach the

threshold level of 2Vcc/3,comparator C1 will switch states and its output voltage

will now be high. This causes the FF to reset so that Ǭ will go high. The high value

of Ǭ turns on the discharge transistor Q1.The time duration of quasi-stable state is

given by the equation, T=1.1RC seconds

48 Lab Manual

ASTABLE MULTIVIBRATOR

Initially capacitor C starts charging through RA and RB towards Vcc with a

time constant (RA + RB) C. During this time , R = 0 ,S = 1, Q = 0 the output is

high. When capacitor voltage equal 2/3 Vcc the upper capacitor triggers the control

flipflop so that Q = 1. This makes transistor Q1 ON and capacitor C starts

discharging towards ground through RB and transistor Q1 with a time constant

RBC

During the discharge of the timing capacitor C, as it reaches Vcc/3 the

lower comparator is triggered and at this stages S =1,

R = 0,which turns Q = 0 . This makes transistor Q1, OFF and again capacitor

starts to charge. Thus the capacitor periodically charges and discharges between

2/3Vcc and 1/3 Vcc

The charging period of the capacitor C = 0.69(RA +RB)C`

The discharge period of the capacitor C = 0.69RBC

Vcc

Ra 6.8k

V0

Rb 6.8k

C = 0.1µF 0.01µF

8 4

7 3

555

2

6 1 5

49 Lab Manual

Design.

Take Vcc = 10 v and t = 1ms and td = 0.5ms

We take, tc = 0.69(RA + RB)C and td = 0.69 RBC

RA and RB should be in the range of 1K to 10 k to limit the collector current of the

internal transistor

Take RA = RB = 6.8k

Let C = 0.1µF, and C1 = 0.01 µF

PROCEDURE

1. Set up the circuit after verifying the condition of the IC using analog IC tester.

2. Use positive pulses of amplitude Vcc and frequency 300Hz as the trigger.

3 .Observe the waveforms at pin numbers 3 and 6 of the chip.

4. If pulse generator isn’t available, use square wave generator along with a

differentiator circuit

Output waveforms:

Trigger pulses

50 Lab Manual

Output waveform:

RESULT

Designed and set up a monostable & Astable multivibrator and observed it

output waveforms

51 Lab Manual

9. ASTABLE AND MONOSTABLE MULTI VIBRATORS USING OP- AMPS

Aim:

To design and setup an astable and mono stable multi vibrators using Op

amp for a frequency of oscillation of 1 Khz

Components and equipments required :

Power supplies ,CRO, op amp resistors and capacitors

THEORY:

Astable multi vibrator is capable of producing square wave for given

frequency , amplitude and duty cycle. The output of the op amp is forced to swing

repetitively between positive saturation +vsat and –ve saturation –Vsat , resulting

in a square wave output. The circuit is also called free running or square wave

generator. The output of the op amp will be in positive saturation if differential

input voltage is negative and vice versa.

Astable multi vibrators is particularly useful for the generation of frequency

in the frequency range . Higher frequencies are limited by the delay time and slew

rate of the op amp.

52 Lab Manual

CIRCUIT DIAGRAM:

4.7K

2 7 +15V

Vc - 6

+ V0

0.1µF 3 4

-15V R1 10K

R2 10K

Astable Multivibrator

Vo

+vsat

-Vsat

Vc

+βVsat

+βVsat

741

53 Lab Manual

Design;

Required period of oscillation T = 1ms with duty cycle 50%

Time period T = 2RCln[(1+β)/(1-β)]

Take β = 0.5 and R2 = 10 k. Then R1 = 10 k

When β = 0.5, T = 2.2 Rc. Let C be 0.1µF. Then R = 4.7K

PROCEDURE: Check the op amp and setup the circuit of an astable multi

vibrator on the bread board and observe the output wave forms from pin nos 6 and

2 and measure the amplitude and frequency.

MONOSTABLE MULTI VIBRATOR

Monostable multivibrator is also called one shot. It has a stable state and a quasi

stable state . The circuit remains in stable until trigging signal causes a transition to

quasi- stable state . After a time interval, it returns to the stable state . So a signal

pulse is generated when a trigger is applied.

Consider the instant at which the output Vo = +Vsat. Now the diode D1

clamps the capacitor voltage VC at 0.7V. Feedback voltage available at no –

inverting terminals is +βVsat. When the negative going trigger is applied such that

the potential at non inverting terminal becomes lass than 0.7V. The output switches

to –Vsat. Now the capacitor charges through R towards –vsat, the diode becomes

reverse biased. When the capacitor voltage more negative than – βVsat , the

54 Lab Manual

comparator switches back to +Vsat, and capacitor C starts charging to +Vsat

through R until Vc reaches 0.7V and C becomes clamped to 0.7V. The pulse width

is given by T = RCln1/(1-β) approximately. If β = 0.5, T = 0.69RC. The time

period of trigger must be larger than the output pulse width T. The circuit does not

respond to a trigger that appears before the specified output pulse width and hence

it is called non-retriggerable monoshot.

R 15k

+15v

2 7

D1 6

IN4007 C 0.1µF 3

4 _15v R1 10k

Cd 0.01µF

D2

Vin Rd 8.2k R2 10k

20vpp

Monostable Multivibrator

741

55 Lab Manual

Vo

+vsat

-Vsat

Vc

+βVsat

+βVsat

Procedure:

Setup the monostable multivibrator and feed 6Vpp,200Hz square wave at the

trigger input

Observe the waveforms at pin no.6 and 2 of op amp and note down its amplitude

and frequency.

DESIGN:

We have , T= RCln1/1-β. Let β be 0.5. then T = 0.69 RC

Take T = 1 ms and C = 0.1 µF, then R = 14.5 k use 15k std.

Since β = R2/(R1+ R2), R1 = R2= 10 k.

For the differentiating circuit RdCd <<0.16 Tt

Trigger time period should be greater than output pulse width of the multi vibrator

Take trigger time period Tt = 5mS and Cd 0.01 µF. Then Rd = 8.2k

56 Lab Manual

RESULT:

Designed and setup astable and mono stable multi vibrators using Op amp.

57 Lab Manual

10 a.VOLTAGE REGULATION USING IC 723

AIM:

To familiarize with general purpose regulator IC 723 and design and setup a

low voltage regulator for an output voltage of 6V using it.

Components and equipments required:

DC sources ,CRO, bread board ,723IC, capacitors and resistors.

THEORY;

723 Ic is general purpose voltage regulator , which can be adjusted over a wide

range both positive or negative regulated voltage. Though the IC is a low

current device, current can be boosted to provide 10 amperes or more. It has

short circuit protection and no short circuit current limits. It can operate with an

input voltage from 9.5V to 40V and provide output voltage from 2V to 37V. It

provides 150mA output current without external output transistors.

Pin out of 723 DIP

1.NC 4.Inverting input 7.V- 10.Vout 13.Fre.Com

2.Current limit 5. Non inverting input 8.NC 11.Vc 14.NC

3.Current sense 6.Vref 9.Vz 12. V+

58 Lab Manual

723 as low voltage regulator Vref point is connected through a resistance to

the non inverting terminal and the output is feedback to the inverting terminal

of the error amplifier. Error amplifier controls the conduction of series pass

transistor Q1. If the output voltage becomes low, the voltage at the inverting

terminal of error amplifier also goes down. This makes the output of the error

amplifier become more positive ,thereby driving the series pass transistor Q1

more into the conduction. This reduces the voltage across Q1 drives more

current into the load causing voltage across load to increase. Thus the initial

decrease in the load voltage gets regulated.

PROCEDURE:

1. Set up the circuit on a bread board and switch on the input

voltage source.

2. Vary the input voltage from 6V to 15V in steps and note

down the corresponding output voltage in the tabular column.

3. Draw the line regulation graph with Vin along X- axis and

Vo along y –axis. Calculate the percentage line regulation using the

expression

Sv = Change in output voltage/Change in input voltage = ∆Vo/∆Vi

4. Set the input power supply at 9V and vary the rheostat and

note down the corresponding change in output current. Draw the load

regulation characteristics with IL along x – axis and Vo along y- axis.

5. Note the output voltage by disconnecting the rheostat from

the output terminals. It is V NL.

Note the output voltage by adjusting the rheostat to read the rated output current

of 100mA. It is VFL. Calculate the percentage load regulation using the

expression.

59 Lab Manual

CIRCUIT DIAGRAM:

Vin

30V

R1 R3 RL +

1k 2.2k V0

C2 1K 0-10V -

C1 R2 100PF 1A(Rh)

0.1µF 5.6k

Design

Required output voltage Vo = 6V.

Let the current through load resistor RL be 100mA. Then RL = 6V/ 100mA = 60Ω.

Use a rheostat to vary the load current to find load regulation.

Let the current ID through the resistor – divider R1 and R2 be 1 mA.

Hence ,R1 = (Vref – V0)/ID = (7.15 – 6)1mA = 1.1k use 1K std.

R2 =Vo/ ID = 6V/1mA = 6K . use 5.6k std

For stebility R3 = R1R2/(R1+ R2) as per data sheet , 1k<R3<3.52k

Take R3 = 2.2k Choose C1 = 0.1 µF and C2 = 100pF

12 11

6 10

723

5 4

7 13

V

A

60 Lab Manual

Line regulation

IL = 100mA Vo(volts)

Vin Volts

Vo Volts

6V Vin(volts)

Load regulation Vo(volts)

Vin = 9V

……………………

IL 100mA

RESULT:

Designed and setup a low voltage regulator for an output voltage of 6V.

IL mA

Vo Volts

61 Lab Manual

10.b HIGH VOLTAGE REGULATOR USING 723 IC

Aim

To design and set up a voltage regulator for 12V output.

Components and equipments required

DC sources, CRO, bread board, 723 IC, capacitor and resistors.

Theory

In order to produce regulated output voltage greater than 7V , a small change

should be made in the circuit for low voltage regulator. The non inverting terminal

is connected directly to Vref through R3. So the voltage at the non inverting

terminal is Vref. The error amplifier operates as a non inverting amplifier with a

voltage gain of Av = 1+R1/R2., Notice that Av is always greater than 1. So the

output voltage of the circuit is Vo = 7.15(1+R1/R2).

Procedure

1.Set up the circuit on a bread board and switch on the input voltage source.

2.Vary the input voltage from 15V to 30V in steps and note down the

corresponding output voltage in the tabular column.

3.Draw the line regulation graph with Vin along X- axis and Vo along y –axis.

Calculate the percentage line regulation using the expression

Sv = Change in output voltage/Change in input voltage = ∆Vo/∆Vi

4.Set the input xpower supply at 15V and vary the rheostat and note down the

corresponding change in output current. Draw the load regulation

characteristics with IL along x – axis and Vo along y- axis.

5.Note the output voltage by disconnecting the rheostat from the output

terminals. It is V NL.

62 Lab Manual

Note the output voltage by adjusting the rheostat to read the rated output current

of 100mA. It is VFL. Calculate the percentage load regulation using the

expression.

30V

R3

10k R1 10k +

RL -

100pF 1k, 1A 10V

R2 15k +1A

Design

Required output voltage Vo = 12V.

Let the current through load resistor RL be 100mA. Then RL = 12V/ 100mA =

120Ω.

Use a rheostat to vary the load current to find load regulation.

Vo is given by the expression, Vo = 7.15(1 + R1/R2)

Take R1 = 10K. Then R2 = 17.7k. Use 15k std.

Take RL = 1k rheostat and C = 100pF

12 11

6 10

723

5 4

7 13

V

A

63 Lab Manual

Line regulation

IL = 100mA Vo(volts)

Vin Volts

Vo Volts

6V Vin(volts)

Load regulation Vo(volts)

Vin = 9V

……………………...

Result

Designed and setup a high voltage regulator for an output voltage of 12V

IL mA

Vo Volts

64 Lab Manual

11. GENERATION AND DEMODULATION OF PWM AND PPM

Aim : To design and setup a Pulse Width Modulator and Pulse Position Modulator

Components and Equipments required:

555 IC, resistors ,capacitors , DC power source, signal generator, diode, bread

board and CRO.

THEORY:

PWM is also known as Pulse Duration Modulation or Pulse length

modulation . It utilizes the advantages of constant amplitude pulses. In PWM,

width of the pulses is varied according to the amplitude of AF signal.

Basic principle of operation of this circuit is nothing but varying the period

of the monostable multivibrator according to the AF input. Consider the internal

diagram . The upper comparator input output goes to logic high state when the

voltage at the non inverting terminal is more than the voltage at inverting terminal.

Since the AF is coupled to the control voltage terminal of 555 using a capacitor ,it

sits on this 2/3 Vcc. That means that the voltage at the control terminal goes up or

down with repect to 2/3 Vcc by an amount of AF signal peak. Thus the peak to

which capacitor charges also vary thus the width of output pulse varies

PROCEDURE:

Setup the circuit and verify whether 555 is working as a monostable

multivibrator.

Apply modulating signal and observe the output.

CIRCUIT DIAGRAM;

65 Lab Manual

Design:

Take Vcc = 10 V and T =1.5ms. WE have T = 1.1RC

Take C = 0.1µF, then R = 13.6 k use 15k std.

For the triggering circuit RC <<0.0016Tt , where Tt is the time period of carrier .

Tt = 2 ms. Takr Ri = 1k. Then Ci = 0.1µF.

Use 10K resistor and 10 µF capacitor for AC oupling.

Wave forms:

Modulating

input

t

Carrier t

Input

PWM

output t

66 Lab Manual

In PPM , position of the carrier pulse from a reference position is varied according

to the modulating signal . The trailing edge of the PWM signal initiates the

beginning of the PPM pulses.

PPM demodulation is done by converting PPM to PWM first and then to anlog

output. PPM to PWM conversion is done by an RS flip flop using two NAND

gates. Clock pulses and PPM signal are fed to S and R respectively. Finally , PWM

signal is converted to analog input using an integrator.

CIRCUIT DIAGRAM;

Design;

Here both 555ICs function as monostable multivibrators. First monostable

multivibrator generates PWM output.

Take Vcc = 10 V and T = 1.5ms

We have T = 1.1RC

Take C = 0.1µF. Then R = 13.6k. Use 15k,Choose C1 = 0.01µF.

Triggering circuit RTCT 0.016Tt where Tt is the time period of carrier = 2 mS

Take RT = 1k. Then CT ≈ 0.1µF

Select coupling capacitor Cc = 10 µF

PROCEDURE:

Set up the PWM circuit , feed the modulating signal sin wave having amplitude

10 Vpp .100Hz and carrier signal as trigger having amplitude 10Vp,500Hz.

Observe the PWM signal output.

67 Lab Manual

Setup the second monostable circuit and feed the PWM output to it and observe the

PPM output.

Wave forms:

Modulating

input

t

Carrier t

Input

PWM

output t

PPM t

Output

68 Lab Manual

RESULT:

Designed and setup PWM and PPM circuit

69 Lab Manual

STUDY OF ADC AND DAC ICs

Aim : To study the function of ADC and DAC IC.

Components and equipments required

ICs ADC0800, DAC0800, resistors, capacitors, dc supply and bread boaed.

Theory : The ADC0800 is an 8-bit monolithic ADC using p- channel ion

implanted MOS technology. It consists of a high input impedance comparator, 256

series resistors and analog switches, control logic and output latches. Conversion is

performed using a successive approximation technique where the analog voltage is

compared using analog switches. When the appropriate tie point voltage matches

the unknown voltage, conversion gets completed. The digital output contain an 8-

bit complimentary binary corresponding to the unknown voltage. The binary

output is tristate to permit using one common data lines.

DAC0800 is a 16 pin IC. Its resolution is 1 paert in 256. The accuracy

is defined as the percentage of full scale or maximum output voltage.

It is an 8-bit current output multiplying DAC with setting time of

100ns., input compatible with most of the logic families, power supply required is

5V to 18V. To provide a corresponding output voltage for the current output of

DAC 0800 a current to voltage converteris used. When unipolar output voltage is

required, Vref is grounded and when bipolar output voltage is required, Vref is

connected to +10V.

70 Lab Manual

CIRCUIT DIAGRAM

+5V Vin -12 -5V

Clock

MSB

B8 B7 B6 B5 B4 B3 B2 B1

B8 B7 B6 B5 B 4 B3 B2 B1 +10V

MSB 10K

10K

4.7K

VO

+15V

0.1µF -15V 0.1µF

RESULT:

15 10 12 8 5

11

18 ADC0800

13 14 15 16 1 2 3 4

5 6 7 8 9 10 11 12

14 4

15

ADC0800 2

3 18 16 13 1

4